GB2225670A - Carrier substrate for electrical circuit element - Google Patents

Carrier substrate for electrical circuit element Download PDF

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Publication number
GB2225670A
GB2225670A GB8926971A GB8926971A GB2225670A GB 2225670 A GB2225670 A GB 2225670A GB 8926971 A GB8926971 A GB 8926971A GB 8926971 A GB8926971 A GB 8926971A GB 2225670 A GB2225670 A GB 2225670A
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United Kingdom
Prior art keywords
layer
carrier substrate
terminals
connection
insulating
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Granted
Application number
GB8926971A
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GB2225670B (en
GB8926971D0 (en
Inventor
Hidetaka Shigi
Takashi Takenaka
Fumiyuki Kobayashi
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Hitachi Ltd
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Hitachi Ltd
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Priority to JP63302396A priority Critical patent/JPH02148862A/en
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB8926971D0 publication Critical patent/GB8926971D0/en
Publication of GB2225670A publication Critical patent/GB2225670A/en
Application granted granted Critical
Publication of GB2225670B publication Critical patent/GB2225670B/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01077Iridium [Ir]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01087Francium [Fr]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Description

- __1 "I,- 1 r 1 - :;1p-:2::1- ss -7 .5,1 1 - CARRIER SUBSTRATE AND METHOD

FOR PREPARING THE SAME : q 1 This invention generally relates to a circuit element package, and more particularly relates to a carrier substrate for the circuit element package and a method for preparing the same, which is suitable for packaging a large scale integrated circuit such as a semiconductor integrated circuit.

Recently, circuits, especially semiconductor circuits are packaged in a package more and more at a higher density and integrated more and more, requiring increased number of pins available externally. To meet these requirements, a flip-chip bonding method has been proposed for the semiconductor integrated circuits, in which terminals are provided on every face of a chip instead of providing terminals only on the peripheral faces of the chip as had been done before. To cope this technique, terminals of the semiconductor package including such semiconductor integrated circuits are led out in grid, accordingly.

The semiconductor package of the type as referred to above generally comprises circuit elements such as semiconductor chips and a carrier substrate on which the semiconductor chips are mounted. The carrier substrate employed in the semiconductor package is generally a ceramic substrate which is made from metals of a k.

2 - high melting point which are baked simultaneously.

On the other hand, a matched termination system is employed for circuits connected with a computer system. In the matched termination system, a transmission line is terminated in a resistance equal to the characteristic impedance of the line, so that there are no reflections and no standing waves.

For this reason, terminating resistances are put on around the package of the semiconductor integrated circuit or the chip to effect termination of the transmission lines when the semiconductor integrated circuit are mounted on the substrate.

The terminating resistors heretofore employed are discrete resistance chips. This imposes serious limitation on the size reduction task of the semiconductor integrated circuit package because such discrete resistance chips themselves have a limitation of small-sization and require substantial areas or spaces to be mounted on. Thus, the discrete resistance chips are not quite suitable for attaining increased packaging density. In other words, only a limited number of semiconductor integrated circuit packages or chips can be assembled to a circuit board as far as the discrete resistance chips are employed.

To solve this problem, a technique which is related to terminating resistance chips, but is capable of assembling an increased number of LSIs, is disclosed in Japanese Patent Un-examined Publication (KOKAI) No. 58 199552.

More particularly, this publication discloses a resistance chip comprising an insulator base and a plurality of resistance elements formed on the base, which is connected, at one end of the respective resistance element, to a through-hole connecting a 1 semiconductor chip and a circuit board and, at another end of the respective resistance element, to an electrode layer provided in the board. The resistance elements are formed on the insulator base such as a ceramic base by a thin-film forming technique or a thick-film forming technique and connected to the through-holes by wiring, respectively. The resistivities of the resistance elements are adjusted by laser trimming after the resistance elements have been prepared.

According to the technique disclosed in the publication, the resistance elements are preliminarily prepared as described above, and only the resistance elements which are needed for semiconductor chips and/or logical wirings provided on the board are left, removing the remaining resistance chips by cutting the wirings with laser beam. These resistance chips are connected to the semiconductor chips by soldering and the so formed assemblies are further connected to a board by soldering to be served for use.

This conventional art, however, fails to teach how to provide a number of resistance elements on the board.

As described above, the resistivity of the resistance element such as a resistance module must be adjusted by trimming during manufacture. More specifically, in the case the resistance elements are provided as a thin film formed on a ceramic base, the resistivity of the film significantly varies locally due to roughness or irregularity of the surface of the ceramic base, which requires adjustment of resistivity. Whereas, in the case the resistance elements are provided in a thick film, accuracy of the resistivity can not be assured, which again requires adjustment of resistivity.

In this connection, it is to be noted that recent highly-integrated semiconductor circuit requires several r, k, hundreds of or even more resistances and it is quite difficult to make adjustment for every resistances by measuring the respective resistivity and trimming the same.

Thus, the conventional technique as disclosed in the publication is not practical or even inpracticable in reality.

This conventional technique further fails to disclose desired arrangement of the resistances. More particularly, the resistances are provided adjacent to the through-holes which connect the circuit board to the semiconductor chips mounted thereon. Therefore, if the integration further increases and bumps are disposed more closely, the areas for mounting the resistances will be reduced. This will impose restriction on the size and arrangement of the resistances.

As can be seen from the foregoing, there is actually some difficulty to apply the technique as described above to a carrier substrate. Therefore, it is a task to solve the difficulty to realize a circuit package using the carrier substrate.

It is therefore an object of the present invention to provide a carrier substrate which is capable of providing thin-film circuit elements, for example, reistance elements with a reqired accuracy and a method for preparing the same.

It is another object of the present invention to provide a carrier substance and a method for preparing the same, which carrier substrate is capable of providing circuit elements such as resistance elements without substantial limitation of size and layout even when it is - 5 required to mount a highly-integrated circuit elements in which bumps for connection are provided closely each other.

It is a further object of the present invention to provide a circuit element package using the carrier substrate as specified above.

To attain the objects as described above, there are provided three inventions for the carrier substrate.

A first invention features a carrier substrate comprising an insulator base with terminals for external connection and a wiring portion provided on the insulator base for connecting a circuit elements to be mounted on the carrier substrate with said terminals for external connection. The wiring portion includes a plurality of insulating films, an electrode layer provided on the uppermost insulating layer for connection with the circuit elements, a circuit element layer or layers provided on the insulating layer or layers other than the uppermost insulating layer and having circuit elements provided in the form of a thin film, and conductors provided on the insulating films for connecting the electrode layer to the terminal for external connection through the circuit element layer or layers.

A second invention features a carrier substrate comprising an insulator base with terminals for external connection and a wiring portion formed on the insulator base for connecting a circuit elements to be mounted on the carrier substrate to the terminal for external connection. The wiring portion includes a plurality of insulating films, an electrode layer provided on the uppermost insulating film and having electrodes for connection with the circuit elements, a wiring layer provided on any other insulating layer than the - 6 uppermost insulating layer for coordinating the arrangement of the electrodes on the electrode layer with the terminals for external connection to connect the electrodes to the terminals, and conductors provided on the insulating layers for connecting the electrode layer to the terminals for external connection through the wiring layer.

A third invention features a carrier substrate comprising an insulator base with terminals for external connection and a wiring portion provided on the insulator base for connecting circuit elements to be mounted on the carrier substrate to the terminals for external connection; the wiring portion including a plurality of insulating films, an electrode layer provided on the uppermost insulating layer for connection with the circuit elements, a circuit element layer provided on the insulating layer other than the uppermost insulating layer and having circuit elements formed in a thin film, a wiring layer provided between the circuit element layer and the electrode layer for coordinating the arrangement of the electrodes on the electrode layer with the terminals for external connection to connect the electrodes to the terminals, and conductors provided on the insulating layers for connecting the electrode layer to the terminals for external connection through the wiring layer.

There is further provided a circuit element package wherein circuit elements are mounted on the carrier substrate as specified above for connection to the electrode layer of the carrier substrate.

There is still further provided a method for preparing a carrier substrate comprising an insulator base with terminals for external connection and a wiring portion provided on the insulator base for connecting t X.

- 7 circuit elements to be mounted on the carrier substrate to the terminals of the insulator base for external connection, which method comprises the steps of: providing the wiring portions by forming an insulating film on the insulator base; forming circuit elements in a film on the insulating film; forming another insulating film on the film of the circuit elements; forming a wiring layer on said another insulating film for coordinating the circuit elements to be mounted on the carrier substrate with the external connection terminals of the insulator base for attaining connection therebetween; forming a further insulating film on the wiring layer; and forming an electrode layer on said further insulating film for connection with the circuit elements; and providing through-holes and wiring conductors in association with the respective insulating films.

In the carrier substrate according to the present invention, a ceramic base is preferably employed as the insulator base. The insulator base are provided with through-holes communicating with the upper and the lower surface of the base.

The thin-film circuit element may, for example, be a thin-film resistance element which may be used as a terminating resistance. The thin-film resistance element may be prepared by vacuum deposition with Cr cermet.

The insulating films are preferably made from organic materials such as polyimide.

The circuit element package according to the present invention is prepared preferably by mounting the circuit elements on the carrier substrate having the thin-film resistace elements. In this case, the the thin-film resistance elements may be used as terminating resistances.

The circuit elements to be assembled in the circui Ir- k- 8 - element package according to the present invention may be integrated circuits. Especially, a large scale integrated circuit such as a semiconductor LSI wherein elements are disposed at a high density may be suitably combined with the carrier substrate having a wiring layer.

According to the present invention, the insulating film is formed on the insulator base to form thin-film circuit elements such as thin-film resistance elements.

Therefore, the irregularity or warp of the insulator base such as a ceramic base is levelled or evened by the insulating film provided under the thin-film circuit elements. Thus, the circuit elements can be free from undesired influences by the surface roughness of the insulator base. By this reason, circuit elements of a desired coefficient, for example, a resistivity can be prepared accurately. As a result of this, adjustment such as trimming is not needed any more for the circuit elements or thin-film resistance elements after they have been formed.

In the case the carrier substrate has a wiring layer on the insulating layer which connects, while coordinating, the electrode layer for connection with the circuits elements to be mounted on the carrier substrate with the terminals of the insulator base for external connection. Consequently, the terminals of the circuit elements to be mounted on the carrier substrate can be connected to the terminals of the insulator base for external connection even when the terminal layout of the circuit elements is not aligned with the terminal layout of the insulator base.

In addition, when the circuit elements to be mounted on the carrier substrate have terminal arrangement in which terminals are disposed very closei-y each other, the c 9 terminal density of the terminal arrangement can be attained by the wiring layer. Consequently, when it is required to mount the circuit package which includes such circuit elements onto a printed circuit board, the connection operation can be handled more easily.

Furthermore, since the high-density terminal arrangement can be reduced to a lower-density terminal arrangement and the terminal arrangements can be coordinated with each other by the wiring layer, the signal or power supply positions can be changed freely, allowing the circuit designing to be more free. This makes the pattern or size of the circuit element formed on the circuit element layer can be determined more freelv.

The present invention will now be described in greater detail by way of example with reference to the accompanying drawings, wherein:- FIG. 1 is a sectional view showing one form of a carrier substrate according to the present invention and a circuit element package using the carrier substrate; and FIG. 2 is a pattern diagram of conductor portions and resistor portions of the carrier substrate in section taken along a line II - II.

An embodiment of the present invention will now be 25 described referring to the drawings.

FIG. 1 illustrates, in section, a configuration of the carrier substrate according to the embodiment.

The carrier substrate as illustrated comprises a ceramic base 6 and a thin-film wiring portion 4 provided 30 on the ceramic base 6.

r A..

The ceramic base 6 is formed, for example, from ceramic powder containing alumina as a main material. The ceramic base 6 is formed with throughholes 7 and provided with terminals 10 to 13. The terminals 10 to 13 are to be used for connection when the ceramic base 6 is mounted to a printed circuit board (not shown). The ceramic base 6 may further be provided with a power supply layer or layers and/or a grounding layer or layers.

The terminal 10 is used as a common electrode terminal for resistance elements 8 which will be described in detail later. Each of the terminal 11 is used as an electrode terminal for the resistance element 8. The terminals 12 are general power supply terminals and the terminal 13 are general signal pins for a large scale integrated circuit (LSI) mounted on the carrier substrate. In the embodiment as illustrated, the terminal 10 is used as a specific power supply terminal for LSI as well as it is used as the electrode for the resistance element as mentioned above. Of course, separate terminals may be provided for these functions, respectively.

The thin-film wiring portion 4 is formed of insulation layers comprising insulating films 9a, 9b and 9c which are provided in this order from the bottom. A resistance layer 15 is provided between the insulating films 9a and 9b for forming the resistance elements 8. Similarly, a wiring layer 14 is provided between the insulating films 9b and 9c for forming conductor wiring 5a. On the top of the insulating film 9c is provided an upper connection layer 3a for connection with circuit elements which are to be mounted above the layer 3a. The insulating film 9a which forms the lowermost layer of the thin-film wiring portion 4 has, on the bottom surface thereof, a lower connection layer 3b formed at positions 14-1, k corresponding to the terminals 10 to 13 of the ceramic base 6 for connection with these terminals 10 to 13, respectively.

The materials of the insulating films 9a, 9b and 9c are not critical and they may be made from any material so long as the material is capable of flushing or leveling the surface of the ceramic base 6. In the embodiment as being referred to, the insulating films 9a, 9b, 9c are made from an organic material such as polyimide resin. The materials of the respective layers may be different. However, the materials of these insulating layers 9a, 9b and 9c are preferably made of the same or similar materials to minimize a thermal stress which might be caused between the layers. The film on which the resistance layer is formed and which functions as a substrate for the resistance elements is preferably made from a material having a coefficient of thermal expansion similar to both the thermal expansion coefficient of the ceramic base and the thermal expansion coefficient of the resistance elements. Most preferably, a material having a coefficient of thermal expansion which is intermediate between the two thermal expansion coefficients.

The resistance layer 15, the wiring layer 14, the upper connection layer 3a and the lower connection layer 3b are connected with each other through the conductor wiring 5a and through-holes 5b and connected to the through-holes 7 of the ceramic base 6. The through-holes 5b are prepared by making holes in the insulating films 9a, 9b and 9c by etching and filling the holes with conductors.

The resistance elements 8 are formed by a thin film and they are formed in the shape of a ring as illustrated in FIG. 2. An inner periphery and an outer periphery of r ve the ring are connected to electrodes, respectively. Of course, the shape of the resistance elements 8 is not limited to the ring and they may be provided in another shape.

Although resistance elements 8 are provided as circuit elements in the embodiment as illustrated, another type of circuit elements may be provided alternatively or additionally. For example, capacitors may be provided. In the case where circuit elements such as terminating resistors are not required, the resistance elements 8 may be omitted.

FIG. 2 illustrates a plane of the resistance layer 15. As shown in the figure, the resistance layer 15 includes a plurality of resistance elements 8 and conductors 5a and through-holes 5b which also function as electrodes of the resistance elements 8.

In the embodiment as illustrated, one wiring layer 14 is provided as described before. This wiring layer 14 is provided for effecting adjustment with respect to differences in arrangements or layouts of terminals provided in the upper connection layer 3a which functions as an electrode layer for connection with circuit elements to be mounted above the connection layer 3a and the lower connection layer 3b to attain coordination between the upper connection layer 3a. and the lower connection layer 3b. In the embodiment as illustrated, the wiring layer 14 enlarges the high- density terminal arrangement of the upper connection layer 3a into a terminal arrangement suited for the lower connection layer 3b. The wiring layer 14, therefore, may be omitted if there is no significant difference in terminal arrangement between the two connection layers. Or, a plurality of wiring layers may be provided according to necessity.

z 1 13 - The wiring layer 14 is provided above the resistance layer 15 in the embodiment as illustrated.

The upper connection layer 3a has a terminal arrangement corresponding to an arrangement of bumps or balls provided on LSI 1 to be mounted on the wiring portion 4. The lower connection layer 3b has a terminal arrangement corresponding to an arrangement of the terminals 10 to 13 of the ceramic base 6.

The integrated circuit elements, i.e., LSI 1 is mounted on the thin-film wiring portion 4. LSI 1 is assembled with its bumps (not shown) placed on the terminals of the upper connection layer 3a, respectively, and bonded thereto by solder 2. Thus, a circuit element package or LSI package can be provided.

The configuration of the carrier substrate will now be described in detail, while referring to the method for fabricating the same.

The ceramic base 6 is prepared by a known method. For example, a dispersion or slurry of ceramic powder and liquid vehicle is prepared and cast into thin sheets by passing a leveling or doctor blade over the slurry. After drying, the sheets are cut to size, through-holes and cavities are mechanically punched, wiring paths are provided, and the through-holes are filled with metal.

Several of these sheets are laminated and the entire structure is fired to form a monolithic sintered body for the ceramic base. In the course of the preparation process, the terminals 10 to 13 are formed on the ceramic base 6. The thin-film wiring portion 4 is provided on the ceramic base 6.

In the thin-film wiring portion 4, the lower connection layer 3b, the insulating film 9a, the resistance layer 15, the insulating film 9b, the wiring layer 14, the insulating film 9c and the upper connection del 14 layer 3a are laminated in this order from the bottom.

The lower connection layer 3b is formed on the ceramic base 6 at positions corresponding to openings of the through-holes 7 which connect to the terminals 10 to 13, respectively. The layer 3b may be formed when the through-holes of the ceramic base 6 are filled with a conductive material.

The insulating films 9a, 9b and 9c are formed by coating a solution of varnish including polyimide, and drying and baking the same. Each of the insulating films 9a, 9b and 9c is provided with the conductors 5a and the through-holes 5b. The insulating films 9a, 9b and 9c are each subjected to etching to form holes or cavities therein and conductive materials are filled in the holes or cavities to form conductors Sa and through-holes 5b. The conductive materials are applied by metallizing or plating.

The insulating film 9a is first made. This insulating film 9a. is formed as thick as it is capable of filling concaves or warp on the surface of the ceramic base 6 to form a smooth surface. It would suffice for the insulating film 9a to have a surface as smooth as the resistance elements 8 to be provided on the insulating film 9a is formed with a high accuracy. For example, the insulating film 9a. is 10 to 30 pm thick.

On an upper surface of the insulating film 9a is provided the resistance layer 15. The resistance elements 8 are formed in this layer by a known method such as a vacuum deposition, sputtering, or the like.

The resistance elements 8 are made from a resistive material such as Cr., Cr cermet, or the like. The resistance elements 8 are shaped in a desired pattern by applying vacuum deposition through a mask or applying photoetching after deposition. The thickness of the resistance element 8 is determined by a resistivity of the resistive material employed and a pattern of the resistance element formed. The thickness is for example 0.05 to 30)1m. 5 The insulating film 9b is formed on the resistance layer 15 in a manner as stated with reference to the film 9a. The wiring layer 14 is provided on the insulating film 9b. The conductors 5a of the wiring layer 14 are made of aluminum. The conductors 5a of the wiring layer 14 are formed, for example, by vacuum deposition etc. in the same manner as described with reference to the resistance layer 15. In this step, a masking means may be used for obtaining desired wiring conductor patterns.

Alternatively, a film of the conductor may be formed first, and then the patterns may be formed, for example, by photo-etching.

The insulating film 9c may be formed in a similar manner to that as described above after the wiring layer 14 has been formed.

The upper connection layer 3a is formed on the insulating film 9c. The conductors of the connection layer 3a are formed by the metal applied to the through holes 5b formed between the wiring layer 14 and the upper connection layer 3a. Therefore, the conductors of the layer 3a can be formed simultaneously with the metal filling into the through-holes 5b. Alternatively, electrodes may be formed separately from the through holes 5b and connected to the through-holes 5b.

The carrier substrate of the embodiment is thus prepared and LSI 1 may be mounted on the carrier substrate to provide an LSI package. For connection of LSI 1, solder balls 2 of a high melting point are applied to the upper connection layer 3a and LSI 1 is put on the 16 - connection layer 3a with its bumps (not shown) placed on the corresponding solder balls 2, respectively, followed by melting the solder balls 2 to attain the desired connection.

The so prepared LSI package is mounted, for example, on a printed circuit board with the terminals 10 to 13 of the ceramic base 6 connected with the board by using solder having a melting point lower than that of the solder ball 2.

As described above, the insulating film 9a is provided on the ceramic base 6 and the resistance elements 8 are formed on the insulating film 9a. With this arrangement, the irregurality of the surface of the ceramic base 6 is evened by the insulating film 9a. As a result of this, the resistance elements 8 can be formed accurately.

The wiring layer 14 provided between the resistance layer 15 and the upper connection layer 3a presents the following advantageous effects.

First, it functions as an interface means for coordinating the terminal arrangement of the ceramic base and the terminal arrangement of the integrated circuit elements to be mounted on the ceramic base.

Secondly, the resistance elements can be free from restriction in position and area where the elements are provided, which restriction may possibly be caused in case leads of the terminals for the integrated circuit elements and the terminating resistance elements are present together. With this arrangement, a plurality of resistance elements may be provided in a desired arrangement and sizes without deteriorating the function of inputting and/or outputting with reference to the integrated circuit elements.

Thirdly, the terminal arrangement of the large scale integrated circuit in which the terminals are provided at a high density is changed into the arrangement in which the terminals are provided at a reduced density due to the interface function of the wiring layer as described above. Consequently, the connection to the printed circuit board can be attained easily. In addition, since the size of the package itself becomes large, the handling of the package can be easier.

Although the invention has been described heretofore with reference to the carrier substrate for LSI and the LSI package employing the same as illustrated, the present invention is not limited to them.

The insulating films of the embodiment as given above are made of polyimide, but they may be made of another material, preferably an organic material.

Although both the resistance layer and the wiring layer are provided in the embodiment as illustrated, they are not necessarily needed when only the function of either one is required.

18

Claims (15)

CLAIMS:- 1 1. A carrier substrate comprising an insulation 2 base with terminals for external connection and a wiring 3 portion provided on the insulator base for connecting a 4 circuit elements to be mounted on the carrier substrate 5 with said terminals for external connection; 6 said wiring portion including a plurality of 7 insulating films, an electrode layer provided on the 8 uppermost insulating layer for connection with the 9 circuit elements, a circuit element layer or layers 10 provided on the insulating layer or layers other than 11 said uppermost insulating layer and having circuit 12 elements formed in a thin film, and conductors provided 13 on the insulating films for connecting said electrode 14 layer to said terminal for external connection through 15 said circuit element layer or layers. 1 2. A carrier substrate comprising an insulator base 2 with terminals for external connection and a wiring 3 portion formed on the insulator base for connecting a 4 circuit elements to be mounted on the carrier substrate 5 to the terminal for external connection; 6 said wiring portion including a plurality of 7 insulating films, an electrode layer provided on the 8 uppermost insulating film and having electrodes for 9 connection with the circuit elements, a wiring layer 10 provided on any other insulating layer than said 11 uppermost insulating layer for coordinating the 12 arrangement of the electrodes on the electrode layer with 13 the terminals for external connection to connect the 14 electrodes to the terminals, and conductors provided on 15 the insulating layers for connecting the electrode layer 1 1 - 19 16 to the terminals for external connection through the 17 wiring layer.
1 3. A carrier substrate comprising an insulator base
2 with terminals for external connection and a wiring
3 portion provided on the in.sulator base for connecting 4 circuit elements to be mounted on the substrate to the 5 terminals for external connection; 6 said wiring portion including a plurality of 7 insulating films, an electrode layer provided on the 8 uppermost insulating layer for connection with the 9 circuit elements, a circuit element layer provided on 10 the insulating layer other than said uppermost insulating 11 layer and having circuit elements formed in a thin film, 12 a wiring layer provided between the circuit element layer 13 and the electrode layer for coordinating the arrangement 14 of the electrodes on the electrode layer with the 15 terminals for external connection to connect the 16 electrodes to the terminals, and conductors provided on 17 the insulating layers for connecting the electrode layer 18 to the terminals for external connection through the 19 wiring layer.
4. A circuit element package wherein circuit elements are mounted on the carrier substrate according to claim 1 for connection to the electrode layer of the carrier substrate.
1
5. A circuit element package wherein circuit 2 elements are mounted on the carrier substrate according 3 to claim 2 for connection to the electrode layer of the - 20 carrier substrate.
1
6. A circuit element package wherein circuit 2 elements are mounted on the carrier substrate according 3 to claim 3 for connection to the electrode layer of the 4 carrier substrate.
7. A carrier substrate according to claim 1, wherein 2 the thin film circuit elements are thin film resistance 3 elements.
1 8. A carrier substrate according to claim 3, wherein 2 the thin film circuit elements are thin film resistance 3 elements.
2 3 1 9. A circuit element package wherein said circuit elements are mounted on the carrier substrate according to claim 7 for connection to the electrode layer of the 4 substrate.
1 10. A carrier substrate according to claim 1, 2 wherein the insulating films are made of organic 3 materials.
1 11. A carrier substrate according to claim 2, 2 wherein the insulating films are made of organic 3 materials.
n 1 c 1 12. A carrier substrate according to claim 3, 2 wherein the insulating films are made of organic 3 materials.
2 f ilm; 1 13. A method for preparing a carrier substrate comprising an insulator ba,se with terminals for external 3 connection and a wiring portion provided on the insulator 4 base for connecting circuit elements to be mounted on the carrier substrate to the terminals of the insulator base for external connection, which method 7 comprises the steps of:
8 providing the wiring portions by:
9 forming an insulating film on the insulator base;
10 forming circuit elements in a film on the insulating
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 forming another insulating film on the film of the circuit elements; forming a wiring layer on said another insulating film for coordinating the circuit elements to be mounted on the carrier substrate with the external connection terminals of the insulator base for attaining connection therebetween; forming a further insulating film on the wiring layer; and forming an electrode layer on said further insulating film for connection with the circuit elements; and providing through-holes and wiring conductors in association with the respective insulating films.
31 ( 1 22 14. A carrier substrate constructed substantially as herein described with reference to and as illustrated in the accompanying drawings.
15. A method for preparing a carrier substrate substantially as herein described with reference to accompanying drawings.
PublishedI990 at The Patent Office.State House, 66 71 High Holborn. LandonWC1R4TP.Purther copies maybe obtained from The Patent Office Sales Branch, St Mary Cray. Orpington. Kent BR5 3RD- Printed by Multiplex techniques ltd. St Ma-y Cray. Kent. Con. 1'87
GB8926971A 1988-11-30 1989-11-29 Carrier substrate and method for preparing the same Expired - Fee Related GB2225670B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63302396A JPH02148862A (en) 1988-11-30 1988-11-30 Circuit element package, and carrier board and manufacture thereof

Publications (3)

Publication Number Publication Date
GB8926971D0 GB8926971D0 (en) 1990-01-17
GB2225670A true GB2225670A (en) 1990-06-06
GB2225670B GB2225670B (en) 1992-08-19

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Country Status (5)

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JP (1) JPH02148862A (en)
KR (1) KR930006274B1 (en)
CN (1) CN1015582B (en)
DE (1) DE3939647A1 (en)
GB (1) GB2225670B (en)

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EP0457583A2 (en) * 1990-05-18 1991-11-21 Nec Corporation Multilayer interconnection substrate
EP0626727A2 (en) * 1993-05-24 1994-11-30 International Business Machines Corporation Thin-film wiring layout for a non-planar thin-film structure
US5403679A (en) * 1992-06-15 1995-04-04 Gnb Industrial Battery Co. Modular battery cabinet assembly
WO1996019829A1 (en) * 1994-12-22 1996-06-27 Pace Benedict G Device for superheating steam
US5904499A (en) * 1994-12-22 1999-05-18 Pace; Benedict G Package for power semiconductor chips
US6384344B1 (en) 1995-06-19 2002-05-07 Ibiden Co., Ltd Circuit board for mounting electronic parts
US6614110B1 (en) 1994-12-22 2003-09-02 Benedict G Pace Module with bumps for connection and support
US7217999B1 (en) * 1999-10-05 2007-05-15 Nec Electronics Corporation Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semiconductor chip on the interconnection board
USRE44251E1 (en) 1996-09-12 2013-06-04 Ibiden Co., Ltd. Circuit board for mounting electronic parts

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JPH10308565A (en) * 1997-05-02 1998-11-17 Shinko Electric Ind Co Ltd Wiring board
JP4023076B2 (en) 2000-07-27 2007-12-19 富士通株式会社 Front and rear conductive substrate and a manufacturing method thereof
JP2005045073A (en) 2003-07-23 2005-02-17 Hamamatsu Photonics Kk Backface incident photo detection element

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Publication number Priority date Publication date Assignee Title
EP0457583A2 (en) * 1990-05-18 1991-11-21 Nec Corporation Multilayer interconnection substrate
EP0457583A3 (en) * 1990-05-18 1992-03-04 Nec Corporation Multilayer interconnection substrate
US5320894A (en) * 1990-05-18 1994-06-14 Nec Corporation Multilayer interconnection substrate
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EP0626727A2 (en) * 1993-05-24 1994-11-30 International Business Machines Corporation Thin-film wiring layout for a non-planar thin-film structure
EP0626727A3 (en) * 1993-05-24 1995-04-19 Ibm Thin-film wiring layout for a non-planar thin-film structure.
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US6614110B1 (en) 1994-12-22 2003-09-02 Benedict G Pace Module with bumps for connection and support
US6384344B1 (en) 1995-06-19 2002-05-07 Ibiden Co., Ltd Circuit board for mounting electronic parts
USRE44251E1 (en) 1996-09-12 2013-06-04 Ibiden Co., Ltd. Circuit board for mounting electronic parts
US7217999B1 (en) * 1999-10-05 2007-05-15 Nec Electronics Corporation Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semiconductor chip on the interconnection board
US8008130B2 (en) 1999-10-05 2011-08-30 Renesas Electronics Corporation Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semicondutor chip on the interconnection board

Also Published As

Publication number Publication date
DE3939647A1 (en) 1990-05-31
GB2225670B (en) 1992-08-19
KR930006274B1 (en) 1993-07-09
CN1015582B (en) 1992-02-19
JPH02148862A (en) 1990-06-07
GB8926971D0 (en) 1990-01-17
CN1043407A (en) 1990-06-27

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