TWI263215B - Memory device having delay locked loop - Google Patents

Memory device having delay locked loop

Info

Publication number
TWI263215B
TWI263215B TW093119097A TW93119097A TWI263215B TW I263215 B TWI263215 B TW I263215B TW 093119097 A TW093119097 A TW 093119097A TW 93119097 A TW93119097 A TW 93119097A TW I263215 B TWI263215 B TW I263215B
Authority
TW
Taiwan
Prior art keywords
clock
delay
outputted
memory device
output
Prior art date
Application number
TW093119097A
Other languages
English (en)
Other versions
TW200539175A (en
Inventor
Eun-Jung Jang
Hyung-Dong Lee
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200539175A publication Critical patent/TW200539175A/zh
Application granted granted Critical
Publication of TWI263215B publication Critical patent/TWI263215B/zh

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F15FLUID-PRESSURE ACTUATORS; HYDRAULICS OR PNEUMATICS IN GENERAL
    • F15BSYSTEMS ACTING BY MEANS OF FLUIDS IN GENERAL; FLUID-PRESSURE ACTUATORS, e.g. SERVOMOTORS; DETAILS OF FLUID-PRESSURE SYSTEMS, NOT OTHERWISE PROVIDED FOR
    • F15B15/00Fluid-actuated devices for displacing a member from one position to another; Gearing associated therewith
    • F15B15/20Other details, e.g. assembly with regulating devices
    • F15B15/26Locking mechanisms
    • F15B15/261Locking mechanisms using positive interengagement, e.g. balls and grooves, for locking in the end positions
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012Marginal testing, e.g. race, voltage or current testing of timing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222Clock generating, synchronizing or distributing circuits within memory device
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F15FLUID-PRESSURE ACTUATORS; HYDRAULICS OR PNEUMATICS IN GENERAL
    • F15BSYSTEMS ACTING BY MEANS OF FLUIDS IN GENERAL; FLUID-PRESSURE ACTUATORS, e.g. SERVOMOTORS; DETAILS OF FLUID-PRESSURE SYSTEMS, NOT OTHERWISE PROVIDED FOR
    • F15B2211/00Circuits for servomotor systems
    • F15B2211/70Output members, e.g. hydraulic motors or cylinders or control therefor
    • F15B2211/705Output members, e.g. hydraulic motors or cylinders or control therefor characterised by the type of output members or actuators
    • F15B2211/7051Linear output members
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F15FLUID-PRESSURE ACTUATORS; HYDRAULICS OR PNEUMATICS IN GENERAL
    • F15BSYSTEMS ACTING BY MEANS OF FLUIDS IN GENERAL; FLUID-PRESSURE ACTUATORS, e.g. SERVOMOTORS; DETAILS OF FLUID-PRESSURE SYSTEMS, NOT OTHERWISE PROVIDED FOR
    • F15B2211/00Circuits for servomotor systems
    • F15B2211/70Output members, e.g. hydraulic motors or cylinders or control therefor
    • F15B2211/72Output members, e.g. hydraulic motors or cylinders or control therefor having locking means

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Fluid Mechanics (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
TW093119097A 2004-05-17 2004-06-29 Memory device having delay locked loop TWI263215B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040034831A KR100546135B1 (ko) 2004-05-17 2004-05-17 지연 고정 루프를 포함하는 메모리 장치

Publications (2)

Publication Number Publication Date
TW200539175A TW200539175A (en) 2005-12-01
TWI263215B true TWI263215B (en) 2006-10-01

Family

ID=35309253

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093119097A TWI263215B (en) 2004-05-17 2004-06-29 Memory device having delay locked loop

Country Status (5)

Country Link
US (1) US6985401B2 (zh)
JP (1) JP4754191B2 (zh)
KR (1) KR100546135B1 (zh)
CN (1) CN100587840C (zh)
TW (1) TWI263215B (zh)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100532973B1 (ko) * 2004-04-30 2005-12-01 주식회사 하이닉스반도체 메모리 장치의 데이타 출력 드라이버 제어 장치
JP4923395B2 (ja) * 2004-08-30 2012-04-25 富士通株式会社 半導体回路、半導体回路特性監視方法、半導体回路試験方法、半導体回路試験装置及び半導体回路試験プログラム
KR100678463B1 (ko) * 2004-12-24 2007-02-02 삼성전자주식회사 데이터 출력 회로, 데이터 출력 방법, 및 반도체 메모리장치
US7576580B2 (en) * 2005-04-27 2009-08-18 University Of Connecticut Energy efficient clock deskew systems and methods
KR100615700B1 (ko) * 2005-08-23 2006-08-28 삼성전자주식회사 메모리 제어장치 및 그의 메모리 제어방법
KR100834400B1 (ko) 2005-09-28 2008-06-04 주식회사 하이닉스반도체 Dram의 동작 주파수를 높이기 위한 지연고정루프 및 그의 출력드라이버
US7449930B2 (en) * 2005-09-29 2008-11-11 Hynix Semiconductor Inc. Delay locked loop circuit
KR100776736B1 (ko) 2005-12-28 2007-11-19 주식회사 하이닉스반도체 클럭 동기 장치
KR100728905B1 (ko) * 2006-02-13 2007-06-15 주식회사 하이닉스반도체 반도체 메모리의 가변 지연장치 및 그 제어방법
KR100779381B1 (ko) * 2006-05-15 2007-11-23 주식회사 하이닉스반도체 감소된 면적을 가지는 dll과 이를 포함하는 반도체메모리 장치 및 그 락킹 동작 방법
JP4499065B2 (ja) * 2006-05-24 2010-07-07 株式会社日立製作所 情報再生装置及び情報再生方法
KR100832021B1 (ko) 2006-06-29 2008-05-26 주식회사 하이닉스반도체 반도체 메모리 소자 및 그 구동방법
KR100891326B1 (ko) 2006-07-31 2009-03-31 삼성전자주식회사 반도체 메모리 장치의 내부 클럭 신호를 데이터 스트로브신호로서 이용하는 반도체 메모리 장치의 테스트 방법 및테스트 시스템
KR100815187B1 (ko) * 2006-08-31 2008-03-19 주식회사 하이닉스반도체 반도체 메모리 장치
TWI302318B (en) 2006-09-06 2008-10-21 Nanya Technology Corp Memory control circuit and method
KR100832007B1 (ko) 2006-10-31 2008-05-26 주식회사 하이닉스반도체 반도체 메모리 소자와 그의 구동 방법
KR100834401B1 (ko) 2007-01-08 2008-06-04 주식회사 하이닉스반도체 반도체 메모리 소자와 그의 구동 방법
KR100813554B1 (ko) * 2007-01-10 2008-03-17 주식회사 하이닉스반도체 데이터 출력 스트로브 신호 생성 회로 및 이를 포함하는반도체 메모리 장치
KR100834397B1 (ko) * 2007-01-10 2008-06-04 주식회사 하이닉스반도체 내부클럭을 테스트할 수 있는 반도체 메모리 장치
TWI328177B (en) * 2007-01-30 2010-08-01 Ind Tech Res Inst Method of evolutionary optimization algorithm for structure design
KR101308047B1 (ko) * 2007-02-08 2013-09-12 삼성전자주식회사 메모리 시스템, 이 시스템을 위한 메모리, 및 이 메모리를위한 명령 디코딩 방법
KR100868015B1 (ko) * 2007-02-12 2008-11-11 주식회사 하이닉스반도체 지연 장치, 이를 이용한 지연 고정 루프 회로 및 반도체메모리 장치
KR100910853B1 (ko) 2007-03-29 2009-08-06 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 구동방법
KR100903371B1 (ko) * 2007-11-02 2009-06-23 주식회사 하이닉스반도체 듀티 싸이클 검출 회로와 검출 방법
US7816961B2 (en) * 2008-02-08 2010-10-19 Qimonda North America System and method for signal adjustment
KR100929654B1 (ko) * 2008-04-15 2009-12-03 주식회사 하이닉스반도체 레지스터 제어형 지연고정루프회로
KR100917630B1 (ko) * 2008-04-30 2009-09-17 주식회사 하이닉스반도체 지연 고정 루프 회로
KR100948067B1 (ko) * 2008-07-10 2010-03-16 주식회사 하이닉스반도체 반도체 소자
KR20100044625A (ko) * 2008-10-22 2010-04-30 삼성전자주식회사 주기적으로 활성화되는 복제 경로를 구비하는 지연 동기 루프를 구비하는 반도체 장치
KR100974217B1 (ko) * 2008-11-11 2010-08-06 주식회사 하이닉스반도체 온도 감지 장치 및 이를 포함하는 dll 회로
KR101022669B1 (ko) * 2008-12-02 2011-03-22 주식회사 하이닉스반도체 지연고정루프회로
TWI401693B (zh) * 2009-01-05 2013-07-11 Nanya Technology Corp 電壓提供電路、以及使用此電壓提供電路的訊號延遲系統
JP5687412B2 (ja) * 2009-01-16 2015-03-18 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. 半導体記憶装置及びそのリード待ち時間調整方法、メモリシステム、並びに半導体装置
KR101605463B1 (ko) * 2009-03-04 2016-03-22 삼성전자 주식회사 피브이티 변동에 둔감한 딜레이 라인을 갖는 지연 고정 루프회로
KR101115474B1 (ko) * 2009-03-30 2012-02-27 주식회사 하이닉스반도체 지연회로
CN101930790A (zh) * 2009-06-26 2010-12-29 扬智科技股份有限公司 数据存取系统与其适应性频率信号控制器
US9160349B2 (en) * 2009-08-27 2015-10-13 Micron Technology, Inc. Die location compensation
US8862973B2 (en) * 2009-12-09 2014-10-14 Intel Corporation Method and system for error management in a memory device
KR101040245B1 (ko) * 2010-02-24 2011-06-09 주식회사 하이닉스반도체 반도체 장치
KR101046274B1 (ko) * 2010-03-29 2011-07-04 주식회사 하이닉스반도체 클럭지연회로
KR20120044061A (ko) * 2010-10-27 2012-05-07 에스케이하이닉스 주식회사 지연고정루프 및 이를 포함하는 집적회로
CN102075167B (zh) * 2010-11-22 2014-03-12 西安电子科技大学 时钟调整电路和时钟电路的调整方法
CN103065677A (zh) * 2012-12-14 2013-04-24 东南大学 基于延迟单元的自校准系统
KR102006243B1 (ko) * 2012-12-24 2019-08-01 에스케이하이닉스 주식회사 반도체 장치의 데이터 라이트 회로
KR20140082174A (ko) * 2012-12-24 2014-07-02 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이를 이용한 동작 방법
JP2014230029A (ja) * 2013-05-21 2014-12-08 日本電波工業株式会社 発振装置
US9111607B2 (en) * 2013-05-31 2015-08-18 Freescale Semiconductor, Inc. Multiple data rate memory with read timing information
US9658642B2 (en) 2013-07-01 2017-05-23 Intel Corporation Timing control for unmatched signal receiver
US9203387B2 (en) * 2014-02-24 2015-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Delay line circuit with variable delay line unit
US9111599B1 (en) * 2014-06-10 2015-08-18 Nanya Technology Corporation Memory device
KR20160029391A (ko) * 2014-09-05 2016-03-15 에스케이하이닉스 주식회사 반도체 장치의 출력 타이밍 제어 회로 및 방법
CN105913873B (zh) * 2016-04-08 2020-01-24 上海电机学院 一种用于超高速非易失性存储器的精准读时序控制电路
US10069496B1 (en) 2017-05-02 2018-09-04 Nxp Usa, Inc. Circuit for compensating for both on and off-chip variations
US10026462B1 (en) * 2017-05-16 2018-07-17 Micron Technology, Inc. Apparatuses and methods for providing constant DQS-DQ delay in a memory device
KR102469133B1 (ko) * 2018-03-07 2022-11-22 에스케이하이닉스 주식회사 지연 회로
US10361690B1 (en) * 2018-06-14 2019-07-23 Sandisk Technologies Llc Duty cycle and skew correction for output signals generated in source synchronous systems
KR102639707B1 (ko) * 2018-07-31 2024-02-26 에스케이하이닉스 주식회사 메모리 장치
CN111541446B (zh) * 2020-05-18 2024-03-22 上海兆芯集成电路股份有限公司 时钟同步电路
KR20230119506A (ko) 2022-02-07 2023-08-16 삼성전자주식회사 파인 지연 모사 회로를 포함하는 지연 고정 루프 및 이를 포함하는 메모리 장치
CN118244841B (zh) * 2024-05-29 2024-08-09 苏州元脑智能科技有限公司 一种服务器时钟架构及其配置方法、设备、产品及介质

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100244456B1 (ko) * 1997-03-22 2000-02-01 김영환 데이터 출력 버퍼를 위한 클럭 조절 장치
JP2000067577A (ja) * 1998-06-10 2000-03-03 Mitsubishi Electric Corp 同期型半導体記憶装置
US6043694A (en) 1998-06-24 2000-03-28 Siemens Aktiengesellschaft Lock arrangement for a calibrated DLL in DDR SDRAM applications
JP2000163961A (ja) * 1998-11-26 2000-06-16 Mitsubishi Electric Corp 同期型半導体集積回路装置
JP2000183172A (ja) * 1998-12-16 2000-06-30 Oki Micro Design Co Ltd 半導体装置
US6704881B1 (en) 2000-08-31 2004-03-09 Micron Technology, Inc. Method and apparatus for providing symmetrical output data for a double data rate DRAM
KR100513806B1 (ko) * 2000-12-30 2005-09-13 주식회사 하이닉스반도체 반도체 장치
JP2002324398A (ja) 2001-04-25 2002-11-08 Mitsubishi Electric Corp 半導体記憶装置、メモリシステムおよびメモリモジュール
KR100399941B1 (ko) 2001-06-30 2003-09-29 주식회사 하이닉스반도체 디디알 에스디램의 레지스터 제어 지연고정루프
US6556489B2 (en) * 2001-08-06 2003-04-29 Micron Technology, Inc. Method and apparatus for determining digital delay line entry point
US6759911B2 (en) 2001-11-19 2004-07-06 Mcron Technology, Inc. Delay-locked loop circuit and method using a ring oscillator and counter-based delay
JP2003297083A (ja) 2002-03-29 2003-10-17 Mitsubishi Electric Corp 半導体記憶装置
KR20040008594A (ko) 2002-07-19 2004-01-31 주식회사 하이닉스반도체 지연고정루프
JP2004103061A (ja) 2002-09-05 2004-04-02 Renesas Technology Corp 半導体記憶装置
KR100482736B1 (ko) * 2002-09-12 2005-04-14 주식회사 하이닉스반도체 지연고정루프의 지연 모델 및 그의 튜닝 방법
KR100518547B1 (ko) 2002-12-28 2005-10-04 삼성전자주식회사 출력 드라이버의 구동력 변화에 따른 내부클락신호의지연을 보상할 수 있는 반도체 메모리 장치의 지연동기루프

Also Published As

Publication number Publication date
TW200539175A (en) 2005-12-01
CN100587840C (zh) 2010-02-03
JP2005332548A (ja) 2005-12-02
US6985401B2 (en) 2006-01-10
KR100546135B1 (ko) 2006-01-24
KR20050109813A (ko) 2005-11-22
CN1700353A (zh) 2005-11-23
US20050254318A1 (en) 2005-11-17
JP4754191B2 (ja) 2011-08-24

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