TWI254398B - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
- Publication number
- TWI254398B TWI254398B TW091135033A TW91135033A TWI254398B TW I254398 B TWI254398 B TW I254398B TW 091135033 A TW091135033 A TW 091135033A TW 91135033 A TW91135033 A TW 91135033A TW I254398 B TWI254398 B TW I254398B
- Authority
- TW
- Taiwan
- Prior art keywords
- gold
- substrate
- wafer
- bonding
- wiring
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910052737 gold Inorganic materials 0.000 claims abstract description 215
- 239000010931 gold Substances 0.000 claims abstract description 215
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 214
- 239000000758 substrate Substances 0.000 claims abstract description 156
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000010410 layer Substances 0.000 claims description 63
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 32
- 239000011347 resin Substances 0.000 claims description 28
- 229920005989 resin Polymers 0.000 claims description 28
- 238000007747 plating Methods 0.000 claims description 18
- 229910000679 solder Inorganic materials 0.000 claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 16
- 229910052759 nickel Inorganic materials 0.000 claims description 16
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 14
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 13
- 230000009477 glass transition Effects 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 9
- 229910052786 argon Inorganic materials 0.000 claims description 7
- 229910052763 palladium Inorganic materials 0.000 claims description 7
- 239000000945 filler Substances 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 5
- 239000011368 organic material Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 4
- 239000002689 soil Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- 239000010970 precious metal Substances 0.000 claims 5
- 239000007787 solid Substances 0.000 claims 2
- 238000000992 sputter etching Methods 0.000 claims 2
- 229910000831 Steel Inorganic materials 0.000 claims 1
- 239000011247 coating layer Substances 0.000 claims 1
- 239000012792 core layer Substances 0.000 claims 1
- 230000001747 exhibiting effect Effects 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 239000007788 liquid Substances 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 239000007921 spray Substances 0.000 claims 1
- 239000010959 steel Substances 0.000 claims 1
- 238000004544 sputter deposition Methods 0.000 abstract description 7
- 230000008569 process Effects 0.000 abstract description 6
- 238000005476 soldering Methods 0.000 abstract description 3
- 230000001351 cycling effect Effects 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 112
- 239000010408 film Substances 0.000 description 36
- 239000011295 pitch Substances 0.000 description 16
- 229910052782 aluminium Inorganic materials 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 210000001503 joint Anatomy 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 238000012546 transfer Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- -1 argon ion Chemical class 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 3
- 239000011256 inorganic filler Substances 0.000 description 3
- 229910003475 inorganic filler Inorganic materials 0.000 description 3
- 238000012552 review Methods 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 241000251468 Actinopterygii Species 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 235000009854 Cucurbita moschata Nutrition 0.000 description 1
- 240000001980 Cucurbita pepo Species 0.000 description 1
- 235000009852 Cucurbita pepo Nutrition 0.000 description 1
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011104 metalized film Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000035935 pregnancy Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 231100000241 scar Toxicity 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 235000020354 squash Nutrition 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L21/607—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of mechanical vibrations, e.g. ultrasonic vibrations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01007—Nitrogen [N]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01018—Argon [Ar]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01021—Scandium [Sc]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01043—Technetium [Tc]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01052—Tellurium [Te]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01065—Terbium [Tb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Description
1254398 ⑴ 玖、發明說明 兒月應敘月^明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明) 【發明之技術領域】 个知日w有關經由貴重金屬凸塊面朝下地將矽晶片安裝 於配線基板上之半導體裝置及安裝方法,尤其是有關可減 少安,時之晶片損傷,可大幅改善連接部之对熱性、溫度 周期壽命、高溫高濕及高溫保持可靠性之晶片/基板間之 接合構造、接合端子之金屬喷鍍構造及金屬接合方法。 【先前技藝】 先刖之使用金凸塊之半導體晶片之倒裝片安裝法包含: 1) 金/金之直接接合, 2) 以絕緣樹脂之晶片接著進行金/金接觸連接, 3) 以異方導電性樹脂之晶片接著進行金/銀粒子/金接觸 連接, 4)金/錫之熔融接合 2。2),3)項之樹脂接著的接觸連接方式,存在經暴露於 高濕度環境下後之各種可靠性測試,惡化顯著缺乏可靠性 之問題,4)項之使用低溶點金屬之炼融接合方式,則存在 接合界面形成脆弱金屬間化合物’接合後之冷卻過程及溫 度,期測試時容易產生裂痕之強度可#性低的問題。目前 可罪性最佳之安裝法係金/金直接接合方式。 孟/金接合方式之先前技術,於特開平10-107078號及電 子通信學會技術報告書(1995年7月)中作為領先技術而揭 不有H線基板之金凸塊1,面朝下地施加超音波進行 金屬接合而搭載形成金凸塊之表面波裝置的方法。此等領 (2) 1254398 發明說明續頁 先技術’為使金凸塊/金凸塊間確實地金屬接合,金凸塊 之膜厚在0·5 μιη以上,適切接合條件為:接合負载為乃gf/ bump〜3 00 gf / bump,接合溫度為150〜25〇。〇,超音波施 加時間為500〜800 ms。在該條件下之金凸塊接合部之剪切 強度可獲得40 gf/bump〜1〇〇 gf/bump。表面波裝置之電介 質基板因係複合氧化物系之電介質材料,因此強度極強, 於接合負載300 gf/bump内無接合損傷。若下降至接合條 件下限值之接合負載75 gf / bump,接合溫度15(rc,超音 波施加時間300 ms以下時’將導致接合強度降低且接合= 穩定,產生未接合品及未接合凸塊而良率降低及連接可靠 性降低,屬於製品組裝困難的條件。此外,配線基板僅述 及陶瓷基板。 另外’在包含有機材料之配線基板上,面朝下地藉由金 屬接合搭載形成金凸塊之半導體晶片的安裝方法,作為領 先技術而揭示於特開平⑻275826號中。該領先技術係^ 配線基板上之覆蓋硬質全屬·鋰 、 是盈又貝鱼屬•鎳(3〜5 μπι)/金(〇 〇3〜〇〇5 μ 之接合焊塾部,於接合前在真空中照射離子或原子予以潔 淨化’晶片於形成凸塊之後保管於非氧化性環境中,使用 保持潔淨度者彼此接合。接人 佼口接口係在空氣中將此等配線基板 與晶片予以加熱及施壓,侔拄 — 保持特疋日守間,於硬質金屬與金 凸塊之間形成合金層來進行金人 〃、 丁隻屬接a。此時適切之接合條 件為:其接合溫度在晶片 ^ - 11 為 150 〜300 C,在基板側為 6〇 20C ’ 接 s 負載為 2〇gf / bUm f 為H50秒。以日3射離μ P 〇gf/bUmP’接合時間 …、射離子或原子予以潔淨化後之焊墊表 (3) 1254398 發明說明繽頁 面僅殘留少許金^]链@ 的私度,在上述條件下藉由接合於硬質金 屬鎳與金凸塊間形成合合 ^ 強固地接合,直至鋅Μ \ &部進行破壞測試時可 至鎳層的一部分缺損,附著於凸塊電極頂 端的狀態下斷孕〗。秘、$ ' '賦予超θ波時雖可促使接合溫度低溫化 及縮短接合時間,但以未詳細揭示。 【發明所欲解決之問題】 ^明人於開發微電腦、圖像處理裝置及搭載記憶體等 2:新LSI晶片之快速·高性能之多晶模組時,檢討評估 月'J之金/金接合方式。模組基板為求配合LSI晶片之電極 間距’須使最小配線間距達到90〜40叫間距。一般之印 刷配線基板係以貼附銅荡經银刻予以圖案化的方法製造, 不過微細間距化方面仍有限制,僅達約100障間距。可對 應於其以上之微細間距之配線基板之於核心基板上形成薄 絕緣層後,以焊接法形成圖案之逐次堆疊方式的組合基板 在生產,、可罪性及成本上最佳。但是該組合基板存在以 逐次堆豐形成之有機絕緣膜的玻璃轉移溫度較低(l〇〇〜15()t:) ’彈性率低,因鏟處理限定於無電解鑛,以致在成本上形 成厚鍍膜固難’且因形狀·尺寸受限而微細配線的剛性低 ’導致以先前之金/金金屬接合之倒裳片安裝困難的問題 。具體檢討例顯示於下。 藉由上述之超音波接合技術,以金/金接合在上述組合 基板上倒裝片安裝最新的LSI晶片。結果判明在接合負載 hgf/bump,接合溫度150〜 250t,接合時間3⑽的條 件下,於形成金凸塊之晶片的鋁電極下絕緣層上產生微小 -10- (4)1254398 發明說明績頁 ,於接合温度15〇°C中,因有機基板之熱膨脹率17 ppm與 L/I晶片之熱膨脹率3ppm之差異,在i〇mm尺寸的晶片上 最大產生約20 4爪的初期位置偏差,在超音波接合時之金 凸塊變形過程中,更助長其位置偏差,容易產生與鄰接端 裂痕,晶片損傷係本安裝法的重大問題。此外判明於組合 基板被加熱時,因施加於微細配線部之接合負載與超音^ 振動致使微細配線嚴重變形,表面鍍成之鎳層上產生I痕 及產生斷線。並判明為求避免此等問題,而降低接合負載 時則無法確實接合,50接腳以上之LSI晶片不易避免因接 合不良導致初期接通不良而達到1〇〇%接合率。此外判明 子的短路不良。並判明在接合間距大的圖案時,雖不致產 生位置偏差及短路不良,但是在接合後的冷卻過程中,於 晶片^基板間產生大的熱畸變,晶片上之鋁膜厚度變薄而 底層薄弱之LSI上產生晶片損傷(底層絕緣層的裂痕)。 、另外,將基板表面予以潔淨化並予以熱壓著之先前的上 述金/金接σ A ’在錄(5㈣/金(〇 〇5㈣規格之組合基板 上倒衣片女裝最新的LSI晶片時,在晶片溫度i 5〇它/基板 溫度6〇t ’接合時間10〜15〇s,接合負載20〜30gf/bump 的條件下於空氣中熱麼著接合時,無法達成確實的金屬 接合。接合狀態之評估係以於氫氧化納水溶液中腐㈣電 極’除去晶片’檢查金凸塊對基板側之轉印率的方法進行 接合抽樣’判斷有無金屬接合。檢討可獲得金凸塊轉印率 %之接口條件的結果,在接合溫度為晶片溫度/基 板溫度⑽,接合負載μ,#/—,接合時間⑽以 1254398 (5) 發明說明續頁 上的條件下,確認轉印率1〇〇%。但是即使在上述任何條 件下,由於接合時間長達丨0〜丨5 0 s,而判明組合基板之溫 度上昇,逐次堆疊之絕緣層的彈性率降低。藉由該現象瞭 解於底層上核心基板具有銅圖案配線之區域的微細配線部 與無銅圖案配線區域之微細配線部的變形程度產生差異。 因此判明產生金凸塊的變形率不均一,變形率大之凸塊可 G得確貫的金屬接合,但是變形率小的金凸塊則接合不足 。此係以玻璃轉移溫度及彈性率高之材料所構成之先前印 刷配線板上未產生的問題。若提高接合溫度則提高整體接 e等、、及,即使變形率小的金凸塊亦可達成金屬接合,但是 基於隨基板之熱膨脹導致凸塊/微細配線間之位置偏差增 加,及微細配線部嚴重變形隨之位置偏差增加等兩個因素 ,未達100 μιη之微細間距LSI的安裝困難。此外,生產性 方面亦存在因接合時間長而導致製造成本提高的問題。 士此外由先前之金/金接合法,於各種配線基板上倒 裝=安裝模擬LSI之TEG晶片,製作於基板/晶片間填充含 熱膨脹率約30Ppm之無機絕緣填料之樹脂的安裝抽樣,進 行-55/ 150。〇之溫度周期測試作評估時,判明金凸塊對基 板側之轉印率為100%之條件的抽樣,其金凸塊的變形大 而晶片/基板間之間隙小,纟晶片之链電極與金凸塊間產 生裂痕’力1000周期等級產生斷線。#制金凸塊變形之條 件的抽樣,若金凸塊之轉印率未達100%,即使為初期可 確認接通者,經數百周期的測試,判明金凸塊與金連接端 子之接合界面形成開口,於短時間即斷線。 -12- 1254398 (6) 發明說明繽頁 本發明之目的在提供一種於具有最小配線間距丨〇〇 以 下之微細配線層,具有低玻璃轉移溫度之表面絕緣層的有 機配線板上,將具有最小電極間距在100 μιη以下,50接腳 以上之電極焊墊之LSI晶片,不產生基板/晶片間之位置偏 差,且不產生晶片損傷,藉由金/金之金屬接合確實地倒 裝片連接全部接腳之半導體的製造方法。 本發明之其他目的在提供一種可以高可靠且低阻抗之特
性將多接腳•微細間距之LSI晶片搭載於具有微細配線層 之有機配線基板上,組裝良率高且生產性優異之安裝構造 及安裝處理。 本务明之其他目的在提供一種於表面層上具有包含微舍 配線層與低玻璃轉移溫度之有機絕緣層之組合層之有機酉 線基板上,藉由倒裝片連接搭載具有50接腳以上之電極火 墊之多接腳LSI晶片,且倒裝片連接部之耐熱性、電性、 高溫高濕及溫度周期可靠性優異之半導體裝置。 【解決問題之手段】
、為求達成上述第一目的,本發明於LSI晶片之電極上 成1有基座部之直徑或矩形之一邊大小係電極尺寸之60 1〇〇/。或是最小電極間距之5G〜90%大丨,高度為5〜4〇 大小,於甘 μ 印 八 σ ’頂端部進一步縮小至基座部之直徑」 7 0 %以下的+ | 小,自底面至頂端之整個高度在30 μπι以上」 金凸塊。另外^ θ ^ Α 於具有微細配線層之有機配線基板側之4 配線的連接端+ $主 二 于取表面上形成金鍍膜。將兩者倒裝片接< 於大氣壓或〇·1〜數Pa之減壓的氬氣環境下,藉由月 -13- 1254398 ⑺ 發明說明繽頁 厚為5—上之1離子賤射法物理性姓刻金凸塊表面,於 由5 nm以上或金膜厚之約1/10〜Μ之氬離子濺射法物理; ㈣連接端子側之錢表面。兩者均在減壓下物理性姓刻 日寸,以氣氣或除去水分之乾燥空氣昇壓,分別放入空氣中 。將有機配線基板搭載於接合裝置的載台i,使⑶ 在超音波接合頭之接合工且而 B9 貞^ 口工具面上反轉吸附,進行兩者的對 接5頭下降重疊。此時載台或接合工具保持在特定 溫度,並使有機配線基板及LSI晶片之溫度在對準步驟中 到達特疋/皿度。於重疊後,自晶片底面施加壓力與超 传Ί:仃ί凸塊與金鍍膜之金屬接合。此時之接合條件 係自加加於每1 bump之負載ρ為 1/2 S㈣ X 丨2。(MP㈣ _丨(m2) χ i8〇 (Mpa) (此時Sl :金凸塊/電極間之接觸面積) 〇) 。此因高於該條件的負荷時’將於金凸塊/ 產生隨伴金凸塊變形之晶片損傷,低 生L變:“積明顯小於凸塊尺寸,在晶片/基板間產 ^ 凸塊本身不變形,畸變集中於接入界 線的概率增加。 艾接口界面而k/f 於Sit條件係接合環境濕度在6〇%以下’接合溫度設 二c =之載?為室溫〜,C,在接合頭側為室溫 巳 接合時間在5〇〜500 ms的範圍,於曰# 振幅為50 kHz時,据動㈣於曰曰片之 於接合工具/晶片間' : ·3 2·0 μΐΏ ’因此工具振幅 、 3振動傳送效率為1/2時在0.6〜4.〇 μπι -14- Ϊ254398 (8) r~- 發明說明繽頁 的範圍,並配合工作潠摆 採用施加超音波中,=:此外負載的施加方法 面如低負載上昇至高負载的方式,自表 以二% η之接合工作暴露於空氣中的時間在分鐘 ^ , 條件靶圍,確認可將金凸塊之變形 ^於頂端部分近旁,避免基板/晶片間產生位置偏差 ,二“上不造成損傷地達成全部接腳之金/金金= =結果之—例顯示於圖12及圖13。圖Μ顯示以金厚 又、’·勺〇細之氬濺射洗淨有機基板側與晶片側之兩面,以 :::幅3卿超音波接合時之接合部剖面與 =電子顯微鏡影像。可知減少接合負載,將基板侧之接 積與晶片側之接合面積比較,即使約小i/5,仍於伸 =剖面上確認凸塊的一部分附著於基板側,而達成金屬接 二此時所謂金屬接合之定義’於藉由伸張力在接合界面 ^成斷裂時,係指在金/金接合部達成呈現隨局部伸展之 延伸性斷裂的接合,可確認於凸塊側與鑛膜侧之斷裂面上 可觀察出金的突起。圖13顯示將凸塊尺寸為5〇μιηφ,電 極間距為80 μηι之晶片接合於組合基板上的剖面照片。因 將基板側之接合溫度設定在室溫而無熱變形,自低倍之剖 面影像可知於連接端子之大致中央,金凸塊精度良好地接 合的狀恶°.此外’自中高倍率之影像可知金凸塊之組織僅 於基板側壓碎扁平形成金屬性接合的狀況。對該條件之接 合抽樣調查晶片損傷時,並無損傷產生。從此等檢討結果 可確認,即使具有最小電極間距在1〇〇μιη以下,5〇接腳以 上之電極焊墊的LSI晶片,仍可提供基板/晶片間不產生位 -15- (9) 1254398 發明說明繽頁 置偏差,且不產生晶片損傷,藉由金/金之金屬接合確實 地倒裝片連接全部接腳之半導體的製造方法。 、 其次,為求達成第二目的,於LSI晶片上形成前述之金 凸塊,於基板側形成前述之金鍍膜。接合前之濺射促使表 ,潔淨化之方*,係採用部分同時進行真空排氣步驟與氯 乱導入/ ^之步驟’其係因應必要數量依序進行使數個 ⑶晶片搭載於拖盤上進行同時賤射步驟及同㈣射數個 基板步驟之步驟。此外選擇接合溫度係將搭載基板之載台
側设於室溫,僅传附曰μ > A 值便及附日日片之接合頭側昇溫,並施加 波與負載進行接合的方式。首先,於濺射洗淨步驟中 由使真空排氣與氬氣導入一邻八 ^ # 邛刀日守間性重疊,可縮短將蓋 氣壓控制在特定壓力的時間 才间钕早開始放電,藉由在拖舷 上處理晶片可同時搬運及法I ^ 曰…^ 建及冼乎多數個晶片,其係將基板盥 晶片分開洗淨方式,可促#夂 奴^、 净各個所需數量,可大幅缩輛 才冼 ,精由增加將基板與晶“者 匕外 驟的超音波接合,可大幅改盖今面㈣^化之步 、 文善金/金接合性,可在低査| •低溫·短時間接合,由於縮短昇溫定、 助於縮短對準步驟,可大幅 才/、…性l疋’有 ..^ , A ?田、、、值紐倒裝片接合步驟,而据古 生產性。此外,藉由接合性 向钕间 不良,而提高生產良率。“亦有助於大幅減少接合 4::為求達成第三目的’將形成於配線基板上之有機 於遠銅配線上的最表面形成 狀开7成 、 形成LSI日日片電極上 -16 - (10) 1254398 發明說明續頁 之金凸塊與金錢膜到·於, 敕勝釘π伸張力,其金凸塊接合部係以2 μ江 以上之延伸接合電平進行金屬接合,於晶片/基板間之間 隙’以低熱膨脹填充含微細之無機填料的樹脂予以凝固的 構造。此時將金在2μ喊上延伸條件的定義與斷裂例同時 顯示於圖9、圖10、圖11。藉由接合電平,斷裂位置分散 於凸塊/金膜之接合界面近旁 '凸塊内、及凸塊/鋁電極之 接合界面近旁,不過任何情況均將Hb_H(H$為金的延伸。
首先藉由以金/金之金屬接合予以連接的構造,促使連接 4之耐熱J·生與電性大幅提高。其次,藉由金/金接合電平 具有可在接合界面吸收2 μπι以上畸變的性能,在晶片/基 板間填充含無機填料之樹脂,以不造成大畸變的方式凝固 接合部,使基板之配線層高於基板面而實質地擴大晶片/ 基板間隙,減少施加於接合部之熱畸變,可大幅改善溫度 周期可罪性,可以具有延展性之金接合部吸收因吸濕等造 成晶片/基板間隙擴大,因此可大幅提高高溫高濕可靠性。 【發明之實施形態】
以下’使用圖式洋細說明本發明之實施例。 圖1顯示一種本發明之半導體裝置之剖面構造的實施例 。圖中之配線基板以:核心基板12 ;形成於其兩側之組合 層1 7 ’ 2 7,·及晶片用連接端子2 1構成。核心基板丨2由:藉 由钱刻與玻璃環氧絕緣板8接著之銅箔予以圖案化之粗配 線層1 0 ’ 11 ;及連接表與裡之配線間用之貫穿通孔9構成 組合層1 7由:藉由塗敷而形成之薄絕緣層丨3 ;以焊接法 形成於其上之微細配線層14 ;及連接粗配線層與微細配線 -17- 00 1254398 發明說明續頁 層用之連通孔1 5構成。由於組合層中之薄絕緣層係以i 〜 1賦之溫度硬化烘烤液狀樹脂者,因此Tg溫度在15代以 下,、且彈性率亦為低值。晶片用連接端子Μ係由以銅鍵所 形成之微細配線18與其上之鎳鍍膜19、以及其上之金鍍膜 2〇構成。㈣係以摻人磷之無電解鑛形,膜厚為5〜 金链係以替換型無電解鑛所形成者,膜厚為⑴们〜 0.06陶。半導體晶片6具有形成於半導體基板丨中央之電 路形成區2的區域與形成於周邊之疊層絕緣膜3的區域,並 具有覆蓋外部連接用之紹電極焊塾4與其以外區域之保護 膜5。於半導體晶片之鋁電極烊墊上藉由超音波熱壓著之 球形接合法形成有金凸塊。晶片之電極焊塾數為256接腳 ’焊墊間距為80陣’焊塾尺寸為邊,焊塾材質為 鋁-銅或鋁-銅-矽,鋁膜厚為4〇〇nm〜1〇〇〇nm。金凸塊尺 寸為壓著後之凸塊徑為50μηιΦ’台座高度為1〇〜25_, 頭部徑為30〜4〇μιηφ,高度為35〜5〇_,包含至配線之 突起部的整個高度為50〜70 μηι。而倒裝片接合步驟之表 面潔淨化處理’係藉由氬氣以金膜厚相當於1〇〜2〇随邙 分減射姓刻基板側之金凸塊面,以金膜厚相當於5〜1〇咖 部分濺射蝕刻基板側之金凸塊面。表面潔淨化處理後,自 放入空氣中.至進行接合的時間在1G min以Θ,並在周圍相 對濕度為60%以下的環境下進行接合。接合條件其接合負 載模式採超音波施加中使負載增加的變動負載方式,^期 負載為1 g/bump〜5 g/bump,最後負载為1〇 g/bump〜3〇 ' bmnP之範圍’抵接晶片之工具頂端之振動振幅在丨〜斗帅 -18- 1254398 _ (12) 發明說明績頁 ms〜3υυ ms之範 之範圍’超音波施加時間在1 Ο Ο 中選擇最佳條件。具體而言,係以初期負載5 g / bump (1.2 8 kg),最後負載2〇 g/bump (5 _ 12 kg),振動振幅 3 μηι, 超音波施加時間300 ms進行接合。接合溫度於晶片側之工 具加熱溫度為1 5 0 C ’搭載基板之載台溫度為室溫:2 〇。〇 。貝際之接合部的剖面如圖B所示。儘管組合基板之金膜 厚非常薄,金/金接合界面上幾乎未發現缺陷地達成金屬 接。。有機基板之外部連接端子23上經由鎳艘膜形成有無 鉛焊凸塊28。初期金膜熔解於焊料中而未殘留於界面上。 本實施例因可於具有以80 μιη之配線間距所形成之低玻 璃轉移溫度之表面絕緣層的有機配線基板上,將形成微細 之金柱形凸塊之LSI晶片,不產生連接部之位置偏差,且 不產生晶片損傷,亦即不產生鋁電極下之絕緣多層膜之妒 痕地藉由金/金之金屬接合,倒裝片連接全部256^腳,因 此可提供搭載於具有最尖端之超高速LSI晶片之有機基板 上的兩可靠性多晶片模組。料,因LSI晶片上無須施加 特殊的加工,可降低模6且制〇沾# 士 l口的成本,可以短期間(約2個 月)製成之有機基板構成模組,因此具有可於短 組裝客戶所需規格之系統模組的效果。此外,亦 ^ 約°.lmm鄰接晶片的狀態下可搭載於基板上,促進!= 女裝化,可達到模組小型化的效果。另外,因接合=^ 造係以具有延展性之金/金金屬接合連接,且 =片側較大,基板側較小的接合形狀,因 = 片/基板間產生畸變’於晶 Μ吏在曰曰 王Γ7應刀之別,係以基 -19- 1254398 _ (13) 發明說明續頁 板側之金凸塊部及接合界面近旁之塑性變形來吸收畴變, 因此亦具有不產生模組組裝步驟中之晶片損傷及接合部斷 線等組裝不良,可以高良率組裝模組,而降低製品成本的 效果。
此外’由於可倒裝片安裝於金膜厚為0 03〜0 06 μηι之非 常薄的連接端子,因此亦可使基板外部連接端子側的金膜 厚同樣地薄,即使以富含錫的焊料形成焊接凸塊,仍具有 不形成金錫金屬間化合物層,促使焊料連接部高強度化, 可提高與母板之連接可靠性的效果。 圖2顯示本發明之半導體裝置構造的其他實施例
之組合基板係於具有通孔配線32與兩面配線33,34之核 基板3 5之兩側形成有組合層42,49的構造,其係包含:土 塗敷形成之絕緣層36,37,43,44;以鑛形成之微細配矣 38, 45;連通孔配線4〇, 47, 48;及以最表面之金膜厚^ 〇·〇5μΓΠ之鍍形成之連接端子39, 41,牝。組合基板之_ 面’數個LSI晶片51經由藉由球形接合法而形成於鋁電相 52上之金凸塊55,以金/金之金屬接合連續搭載於基板戈 連接端子41上。並以凸塊高度為3〇 gm,配線高度為2〇μΓ 組衣。4LSI晶片/基板間填充有含對晶片側之純化膜辦 =絕緣層.37兩方接著性良好之無機填料的底填樹脂仏 動零件57精由無錯焊58連續搭載於連接端子39上 二:方t組合基板之另—側上,以覆蓋連接端子46之- 凸塊。圖3顯示圖2之半導體裝置之組裝流程的—種實:例 -20- (14) 1254398 發明說明縝頁 。LSI晶片形成金柱形凸塊並實施濺射洗淨,组入 $經^_洗淨者後,於基板上依序超音波倒Η接合特 疋數篁的1^1晶片。金凸塊之濺射厚度在10 nm以上,基板 側之濺射厚度在金膜厚之1/10以上或10nm以上。接合溫 度於晶片側為常溫〜15(TC,基板側為常溫〜6(rc。LSI晶 片接合後,於晶片/基板間灌入底填樹脂,於i2(rc以下$ 度進行初期$共烤。其二欠,於基板之晶片搭載側的被動零件 連接端子上印刷焊接漿液,供給被動零件進行平坦化熱處 理。其次將局部塗敷焊劑之焊接球供給至連接端子,進行 平坦化熱處理。最後洗淨焊劑後,藉由150°c之烘烤使LSI 晶片下的底填完全硬化而完成組裝。 本貫施例基於組裝成LSI晶片/組合基板之間隙擴大至5〇 ,且於其間隙填充樹脂,並藉由加熱烘烤加以硬化,因此 ,藉由樹脂硬化收縮與自烘烤溫度15(rc冷卻,接合部上 始終施加壓縮力,於溫度周期測試及高溫高濕測試中,接 合部上不產生導致剝離的強大力,此外,因微小之剪切畸 變可以柔軟之金凸塊的塑性變形吸收,因此接合部周邊不 產生高應力等因素,可提供LSI晶片之連接可靠性非常高 的半導體裝置。J:匕外,由於以〇 〇5 μιη之非常薄的膜構成 基板之連接端子的金膜厚,因此亦具有可提高焊接連接部 之可靠性的效果。此外,由於LSI晶片之微小連接部係低 電阻之金,並以金屬性且以最短距離連接於基板,因此亦 具有連接部之電阻及阻抗成分非常小,電性優異,可縮短 传號傳送延遲,避免高速系統之性能降低的效果。此外, -21 - (15) 1254398 發明說明續頁 由於金/金倒裝片接合部之耐 後面進行被動零件及LSI零件 尖端之LSI晶片與焊接接合零 ’設計容易的效果。 熱性高,因此亦具有容易自 的焊接搭載,可混合搭載超 件’系統構造的選擇範圍廣 圖4顯示本發明之半導體 σσ 衣置之口丨J面構造的其他實施例 。微細單面配線基板6 5之微 1又、、、田運接端子66係於銅圖案上實 施鎳/金鍍。在LSI晶片60,61之钮雷杌u f二士人 、 丄之紹電極上形成有金柱形凸 塊,並藉由金/金之金屬接合與基板65之連接端子連接。 於基:反與LSI晶片之間填充有含無機填料之低熱膨脹樹脂 ,並藉由加熱予以硬化。其祐A 4 + 土扳6 5接者於母板6 8加以固定, 基板與母板之間以金線70之線接合連線。 本實施例因以無通孔之單面配線基板構成模組,因此具 有可以貼薄銅箔之基板的㈣處理來製造,可藉由降低基 j成本而降低模組成本的效果。此外,因於包含母板搭載 别並無焊接接合部,因此亦具有附加零件之焊接搭載不受
限制,組裝容易,可提高溫度周期可靠性及高溫高濕可靠 性的效果。 圖5顯示本發明之半導體裝置之剖面構造的其他實施例 圖中於兩層配線印刷基板93之一面的一部分,藉由接著 劑86貼附具有通孔85的單面帶基板%,帶基板之通孔電極 85與印刷基板之連接端子90係以金/金之高負載條件的加 熱壓著接合。形成於帶基板之配線連接端子84與1^1晶片 8〇之鋁電極81的金鍍凸塊82係藉由超音波熱壓著進行金/ 金接合。於晶片/帶基板間填充有樹脂87並加以硬化。於 -22- (16) 1254398 發明說明續頁 印刷基板之底面的外部連接端子91上形成有谭接凸塊。 本實施例因採僅於LSI晶片搭載部上形成微細配線區域 的構造’可以麼著以其他步驟製出之微細配線帶基板的方 法製造模組基板,因此可提高基板製造之通量,可降低成 本。此外’亦具有於LSI晶片因收縮等因素而規格變更時 ’僅將帶基板作最小限度的變更即可再製造基板,可縮短 規格變更之開發期間的效果。 圖6顯示本發明之LSI晶片與有機配線基板之接合構造的 一種實施例。圖中於LSI晶片1〇〇之紹電極ι〇ι上,藉由球 接合法形成有金柱形凸塊1G3。柱形凸塊由:金球被毛細 管工具之頂端面壓碎之厚度為心欧基座部、壓入毛細 孔所形成之殼部、與金線經過伸張斷裂而形成之尖塔狀的 頂端部構成,形成僅壓碎頂端部,而於基板之連接端子上 金/金接合的形狀。晶片側之接合部直徑為牦pm,基板側 之接合部直徑為30 μιη。有機配線基板係於核心基板i 15之 兩面形成薄絕緣層1 〇7,;[ 08後,在其上形成微細配線層的 構造。晶片連接端子之構造係於銅圖案上鎳/金或鎳/鈀/金 鍍之構造,金厚度或鈀+金厚度為0.05〜0.1 μιη。 本κ ^例因基板側的接合面積比晶片側之接合面積小達 1 /2以下’凸塊高度係維持初期之柱形凸塊殼部的高度, 因此即使產生接合後之負載釋放時產生之基板的反撓曲, 晶片之铭電極周邊未施加金屈服強度之1 /2以上之力,因 此不致應力性破壞晶片之鋁電極下的絕緣多層膜。因此, 即使基板之平坦精密度低,仍具有組裝良率高的效果。該 -23- 1254398 發明說明繽頁 (17) 應力的問題,於接合中同樣地 狀,因此亦具有減少接合時之晶片損傷的效果。 圖7顯示本發明之LSI晶片與有機配線基板之接合構造的 其他實施例。圖中於LSI晶片120之鋁電極121上,以一部 分覆蓋於鈍化膜122之方式形成有金屬喷鍍膜123,其上藉 由鍍法形成有金凸塊。金凸塊於鍍步驟後施加熱處理,以 維氏硬度Hv在80以下之方式實施軟質化處理。有機配線基 板之晶片連接端子1 3 7之連接端子頂端部的尺寸設計成小 於凸塊底面的尺寸,接合後之端子側的接合面積形成凸塊 底面之面積1/2以下的尺寸。具體而言,凸塊係長4〇μιηχ 咼15 μιη,連接端子之基座部寬3〇 μπι,頂端部寬2〇 , 高20 μιη。連接端子之構造係於銅圖案上鎳-磷/金或鎳-磷/ 鈀/金鍍的構造,金厚度或鈀+金厚度為〇〇5〜〇ipm。 本實施例因採藉由金/金金屬接合將形成金鍍凸塊之 曰曰片搭載於有機配線基板上的構造,鋁電極並未暴露於外 部,即使暴露於高溫高濕環境之腐蝕環境下亦不受其影響 ’因此可提供可靠性非常高的半導體裝置。此外,因凸^ 底面大達龍於聽臈,形成連接端子接觸於凸塊中央的 配置’因此亦具有銘電極周邊不產生應力集中,不對晶片 造成接合損傷’可提高組裝良率的效果。最令人擔心者, 係因金ώ塊變形不易,益法 ”、、凌及收基板回度不均一及鍍凸塊 之局度不均一,而產生未 俏入^ 安口鲕于不過精由以熱處理降 孟凸塊之硬度及縮小連 ,葬以一 運接知子尺寸,容易擠入金鑛凸塊 猎由金凸塊之局部性變形來 水汉队同度不均一即可避免該 -24- 1254398 (18) —--— 發明說明繽頁 問題。 圖8顯示本發明之半導體裝置之剖面構造的其他實施例 。圖中係於LSI晶片140之電路形成面上形成有由厚度為 4 μιη聚醯亞胺之絕緣膜142與附隔離膜之銅配線143構成之 再配線層,其上形成有最表面係金膜之電極端子丨。其 電極端子上藉由球接合法形成有金柱形凸塊145。有機配 線基板係配線間距200 μπι之印刷電路基板,並於連接端子 上貫施鎳/金電鍍。於基板背面之外部連接端子上形成有 焊接凸塊。此外,於晶片/基板間填充有樹脂加以凝固。 本實施例因係使用於微細間距之LSI晶片上藉由再配線 形成擴大層之晶片,以金/金金屬接合連接於有機基板上 ,因此有機配線基板上可使用一般之印刷電路基板,可予 以低成本化。此外,因係經由聚醯亞胺之緩衝將接合時之 應力傳導至晶片的構造,因此完全不產生組裝步驟時之晶 片損傷,可配合對準容易度大幅提高良率。此外, /貧』 Θ曰曰/"! 土板間之連接部的耐熱性與可靠性高,因此亦具有對模組 搭載於母板處理幾乎無限制,處理容易使用性佳的效果: 【發明之功效】 如以上詳述,本發明可提供一種於具有最小配線間距 100 μιη以下之微細配線層,具有低玻璃轉移溫度之表面絕 、、彖層的有機配線板上,將具有最小電極間距在⑽叫以下 ,5〇接腳以上之電極焊墊之LSI晶片,不產生基板/晶片間 1置偏差,且不產生晶片損傷,藉由金/金之金屬接合 確貫地倒裝片連接全部接腳之半導體的製造方法。 -25- (19) 1254398 發明說明繽頁 卜可提供一種可以尚可靠且低阻抗之特性將多接腳· u細間距之LSI晶片搭載於具有微細配線層之有機配線基 板上’組裝良率高且生產性優異之安裝構造及安裝處理。 此外,可提供-種於表面層上具有包含微細配線層與低 :璃轉移溫度之有機絕緣層之組合層之有機配線基板上, 猎由倒裝片連接搭載具有5 0接腳以上之電極焊墊之多接腳 LSI晶片,且倒裝片連接部之耐熱性、電性、冑溫高濕及 /m度周期可靠性優異之半導體裝置。 【圖式之簡單說明】 圖1係本發明之半導體裝置之剖面構造的一種實施例。 圖2係本赉明之半導體裝置之剖面構造的其他實施例。 圖3係本發明之半導體裝置之剖面構造的其他實施例。 圖4係本發明之半導體裝置之剖面構造的其他實施例。 圖5係本發明之半導體裝置之剖面構造的其他實施例。 圖6係本發明之LSI晶片與有機配線基板之接合構造的一 種實施例。 圖7係本發明之LSI晶片與有機配線基板之接合構造的其 他實施例。 圖8係本赉明之半導體裝置之剖面構造的其他實施例。 圖9係接合部伸張斷裂時之金伸展的定義與斷裂例。 圖10係接合部伸張斷裂時之金伸展的定義與斷裂例。 圖11係接合部伸張斷裂時之金伸展的定義與斷裂例。 圖1 2係金凸塊接合部之剖面形狀與斷裂狀況。 圖13係80 μιη間距LSI晶片與組合基板之接合剖面例。 -26- I254398 發明說明續頁 (20) 圖式代表符號說明 …矽基板、2…電路形成區 電極焊墊、5…保護膜、6, 5心"半導體晶片、了,M,^ •••金凸塊、8…玻璃環氧絕緣板、9,85…通孔、,丨卜·· 配線層、i2,35,115···核心基板、13,22,刊,37,^ ’ 44 ’ 107 ’ 108 ’ 126,128…絕緣層、14〜微細配線層、 15,24…連通孔、16,25,59,92,113,135,15〇 …光
阻膜、17,27,42,49···組合層' 18,38,45·••微細配線 、19 ’ 26 ’ 110 ’ 131···鎳鍍膜、20,lu,132···金鍍膜、 21 ’ 39,41,46,66,9〇,91,133,148.··連接端子、23 ,67,112 ’ 134 ’ 149···外部連接端子、28,5〇,94,1H ’ 136 ’ 152···焊接凸塊、31,146·••有機絕緣基板、32, 89,147···通孔配線、33,34,1〇5,1〇6 , 127,129 ••配 線、40,47,48…連通孔配線、51,6〇,61,8〇,1〇〇, 120’140〜1^1晶片、52,62,81,1〇1,121,14卜.鋁電
極、53,63,1〇2,122…鈍化膜、56…底填樹脂、57…被 動零件、58···烊接、64,1()3,145···金柱形凸塊、65···配 線基板、68···母板、69…WB連接端子、7〇…金線、以… 緣▼、84···配線連接端子、86···接著劑、87,151…樹 脂、88…玻璃環氧基板、93…印刷基板、%…帶基板、 104 125···有機絕緣板、1〇9,13〇…銅圖案、123…金屬 喷鍍膜、124···金鍍凸塊、142…絕緣膜、I"…銅配線、 144···電極端子。 -27-
Claims (1)
1254398 拾、申請專利範圍 1. 一種半導體裝置,其且 加\ /、有·夕層配線基板,其係至少一 口F为以有機材料構成;< 寸傅风,形成有電子電路之 及有機樹脂,苴俜埋入前、+、丄 。遐日日片, η 則述半導體晶片與前述多層配線 基板之間;其特徵為··前 Λ 層配線基板上之晶片連接 用立而子下之至少一立β八4装_L、U 邛刀構成構件係以具有15〇〇c以 玻璃轉移溫度的有機材料構 得风日日片連接用端子之最心、 間距在100 μχη以下,晶片i隶技 曰曰月連接用端子之表面金屬係由鎳_ 磷/金或錦_碟/把/金之鑛層構成,且金及趣/金之貴重金 屬部之總厚度為0.005〜〇.3_,半導體晶片之電極端子 上形成有金凸塊,基柄卜夕A、+、人土 ^ 敬上之刚述金連接端子與晶片之前 述金凸塊以金屬接合連接。 2·如申睛專利範圍第!項之半導體裝置,#中前述多層配 線基板包含:核心基板,其係以具有單面或兩面配線圖 案之印刷配線基板構成;及丨層以上之組合層,其係具 有:於前述核心基板上塗敷液狀樹脂使其硬化或貼附膜 狀樹脂而形成之有機絕緣層;於前述有機絕緣層上形成 有比核心基板微細,最小配線間距在丨〇〇 以下之銅配 線之微細配線層;及連接上層微細配線與下層配線之連 通孔連接部。 3·如申請專利範圍第1或2項之半導體裝置,其中形成金凸 塊/金連接端子係藉由呈現金之延展斷裂之金屬接合倒裝 片連接’於晶片/基板間填充有含無機絕緣填料之樹脂, 基板之外部連接端子以焊接凸塊所構成之構造。 1254398 申請專利範圍繽頁 4·如申4專利範圍第2項半 V體衣置,#中丽述核心基 之河述有機絕緣層係以玻璃轉移溫度Tg: 15〇。〇以 下之有機樹脂構成,微細配線銅圖案之至少一部分 由電鍍形成。 ”错 5·如申請^利範圍第2項之半導體裝置,丨中前述核心基 二丽述有機絕緣層與前述微細配線層係接著聚醯亞 妝Τ基板而形成。 6·-種半導體裝置,其具有:多層配線基板,i係至 部分以有機材料構成;形成有電子電路之半導體晶片. :有機樹脂’其係埋入前述半導體晶片與前述多層配線 基板之間;其特徵為··金屬接合前述多層配線基板上之 :連接端子與前述半導體晶片上之金凸塊,金凸塊之結 晶組織形成於晶片側較粗,於基板側向端子面方向1 扁平形狀且微細的組織。 7·一種半導體裝置’其特徵為包含:組合基板,其係於且 有通孔舆兩面配線圖案之有機配線基板的兩面,形成2 有機絕緣層、銅鍍配線、與連通孔構成之}〜4層的組合 層於與半導體晶片連接之端子面上實施金厚度為〇 〜〇.3 μηι之無電解鎳/金或無電解鎳/鈀/金鍍;及 半導體晶片,其係於具有接腳數5〇個以上之裸晶片之 連接電極或設於晶片表面之再配線層上之連接電極上形 成金凸塊; 7 且具有金凸塊與金鍍面以金/金之金屬接合進行倒裝片 連接,基板與晶片間之間係以含無機絕緣填料之樹脂填 -2 - 1254398 申請專利範圍續頁 充,於组合基板之底面之 處理形成有焊接凸塊之構造。子上猎由平坦化熱 •種半導體裝置,其且有·夕 部分以有機材料構成:开二層配線基板’其係至少- 及有機樹脂,其係、埋人晶片與基板之間;日片二 述多層配線基板上之晶片連接端 ::寺:為.别 之鍍層構成,前述半導體曰、、,萄係以金 金屬柱形凸塊,二片=電極端子面上形成貴重 舌人η 述曰曰片連接端子上之金鍍層與前述貴 二金二塊以金屬接合連接,晶片電極/凸塊間之密著面 =與凸塊/基板側連接端子間之㈣面積处之 在1/2以下。 ,半^體裝置’其係半導體晶片以各貴重金屬之固態 ,接合之倒裝片冑接安裝於配線基板上,纟特徵為: 具有配線基板上之半導體晶片之連接端子之表面金屬由 鎳/金或錄/!巴/金之鑛層構成,且金及免/金之貴重金屬部 之總厚度為0.005〜〇.3 μιη,半導體晶片以石夕基板上之電 子電路形成區域與電極焊墊區域構成,其表面夾著厚度 在2 μιη以上之有機絕緣層而形成再配線層,與電極焊墊 電性連線之再配線層之連接焊墊以總厚度在2 pm以上之 銅/隔離金屬/金之多層金屬構造構成,該連接焊墊上形 成金凸塊,金凸塊與金鍍面以金/金之金屬接合倒裝片連 接,且基板與晶片間之間隙以含無機絕緣填料之樹脂填 充,配線基板之底面之外部連接端子上藉由平坦化熱處 理形成有焊接凸塊之構造。 1254398 申請專利範圍繽頁 10.—種半導體裝置,其係半導體晶片以各貴重金屬之固態 金屬接合之倒裝片連接安裝於配線基板上,其特徵為: 有配線基板上之晶片連接端子之表面金屬由鎳/金或鎳 /、鈀/金之鍍層構成,且金及鈀/金之.貴重金屬部之總厚度 為0.005〜0·3 μιη,半導體晶片以矽基板上之鋼配線之電 子電路形成區域與銅電極焊墊區域構成,銅電極焊墊最 表面經由隔離層而實施金或紹金屬喷鐘處理,進一步於 其上形成有金柱形凸塊或金鍍凸塊,金凸塊與金鍍面以 金/金之金屬接合倒裝片連接,且基板與晶片間之間隙以 合無機絕緣填料之樹脂填充,配線基板之底面之外部連 接端子上形成有焊接凸塊之構造。 11·一種半導體裝置之製造方法,其特徵為具有:物理性濺 射蝕刻步驟,其係於配線基板之金鍍連接端子與形成於 晶片上之金凸塊之倒裝片連接中,藉由平行平板電極間 產生之減壓下之氬放電氣體物理性濺射蝕刻配線基板之 金連接端子表面至金膜厚之1/10以上或10nm以上,且僅 金膜厚之1/2以下厚度;與基板側同樣地濺射蝕刻晶片上 之金凸塊表面僅數〜數十nm厚度;對準步驟,其係使基 板與晶片相對;加熱步驟,其係將晶片 至⑽之範圍的溫度:TC,將基板侧加二^ 之玻璃轉移溫度Tg以下之溫度Tb;金/金之金屬接合步 驟,其係以超音波接合方法進行’該超音波接合方法包 含於超音波加振中使施加於晶片之負載增加的步驟;填 充步驟,其係於基板與晶片之間填充樹脂;使填充之樹 1254398 申請專利範圍續頁 月曰加熱硬化步驟;及於基板之外部連接端子上形成焊接 凸塊步驟。 12 13 如申請專利範圍第丨丨項之半導體裝置之製造方法,其中 於濺射蝕刻晶片與配線基板兩者後,,藉由超音波倒裝片 接合前之空氣釋放時間為10分鐘以内。 如申請專利範圍第11項之半導體裝置之製造方法,其中 =超音波接合時之基板溫度設定為室溫,將晶片溫度設 疋為室溫〜1 5 〇 。 如申請專利範圍第11項之半導體裝置之製造方法,其中 將超音波接合時之基板溫度及晶片溫度設定為室溫。 14·
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001393043A JP3891838B2 (ja) | 2001-12-26 | 2001-12-26 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200303588A TW200303588A (en) | 2003-09-01 |
TWI254398B true TWI254398B (en) | 2006-05-01 |
Family
ID=19188742
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW091135033A TWI254398B (en) | 2001-12-26 | 2002-12-03 | Semiconductor device and its manufacturing method |
Country Status (5)
Country | Link |
---|---|
US (1) | US6784554B2 (zh) |
JP (1) | JP3891838B2 (zh) |
KR (1) | KR100531393B1 (zh) |
CN (1) | CN100431142C (zh) |
TW (1) | TWI254398B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI512862B (zh) * | 2013-03-25 | 2015-12-11 | Toshiba Kk | Manufacturing method of semiconductor device |
Families Citing this family (92)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6889429B2 (en) * | 2001-03-26 | 2005-05-10 | Semiconductor Components Industries, L.L.C. | Method of making a lead-free integrated circuit package |
JP3891838B2 (ja) * | 2001-12-26 | 2007-03-14 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
US7505862B2 (en) * | 2003-03-07 | 2009-03-17 | Salmon Technologies, Llc | Apparatus and method for testing electronic systems |
JP4170137B2 (ja) * | 2003-04-24 | 2008-10-22 | 新光電気工業株式会社 | 配線基板及び電子部品実装構造 |
TWI245381B (en) * | 2003-08-14 | 2005-12-11 | Via Tech Inc | Electrical package and process thereof |
US7408258B2 (en) * | 2003-08-20 | 2008-08-05 | Salmon Technologies, Llc | Interconnection circuit and electronic module utilizing same |
US7239023B2 (en) * | 2003-09-24 | 2007-07-03 | Tai-Saw Technology Co., Ltd. | Package assembly for electronic device |
US8216930B2 (en) | 2006-12-14 | 2012-07-10 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
US8129841B2 (en) | 2006-12-14 | 2012-03-06 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
US8574959B2 (en) | 2003-11-10 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
USRE47600E1 (en) | 2003-11-10 | 2019-09-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
US9029196B2 (en) | 2003-11-10 | 2015-05-12 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
KR101237172B1 (ko) | 2003-11-10 | 2013-02-25 | 스태츠 칩팩, 엘티디. | 범프-온-리드 플립 칩 인터커넥션 |
US8026128B2 (en) | 2004-11-10 | 2011-09-27 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
JP4507582B2 (ja) * | 2003-12-12 | 2010-07-21 | パナソニック株式会社 | バンプ付電子部品の実装方法 |
US20050184376A1 (en) * | 2004-02-19 | 2005-08-25 | Salmon Peter C. | System in package |
US20050186690A1 (en) * | 2004-02-25 | 2005-08-25 | Megic Corporation | Method for improving semiconductor wafer test accuracy |
US7064963B2 (en) * | 2004-04-01 | 2006-06-20 | Delphi Technologies, Inc. | Multi-substrate circuit assembly |
WO2005097396A1 (ja) | 2004-04-08 | 2005-10-20 | Matsushita Electric Industrial Co., Ltd. | 接合方法及びその装置 |
US20050255722A1 (en) * | 2004-05-07 | 2005-11-17 | Salmon Peter C | Micro blade assembly |
US7393771B2 (en) * | 2004-06-29 | 2008-07-01 | Hitachi, Ltd. | Method for mounting an electronic part on a substrate using a liquid containing metal particles |
DE102004032706A1 (de) * | 2004-07-06 | 2006-02-02 | Epcos Ag | Verfahren zur Herstellung eines elektrischen Bauelements und das Bauelement |
DE102004040414B4 (de) * | 2004-08-19 | 2006-08-31 | Infineon Technologies Ag | Verfahren zur Herstellung eines Verdrahtungssubstrats eines Halbleiterbauteils mit Außenkontaktanschlussflecken für Außenkontakte |
TWI278090B (en) * | 2004-10-21 | 2007-04-01 | Int Rectifier Corp | Solderable top metal for SiC device |
US7812441B2 (en) | 2004-10-21 | 2010-10-12 | Siliconix Technology C.V. | Schottky diode with improved surge capability |
US7427809B2 (en) * | 2004-12-16 | 2008-09-23 | Salmon Technologies, Llc | Repairable three-dimensional semiconductor subsystem |
US20070007983A1 (en) * | 2005-01-06 | 2007-01-11 | Salmon Peter C | Semiconductor wafer tester |
US9419092B2 (en) | 2005-03-04 | 2016-08-16 | Vishay-Siliconix | Termination for SiC trench devices |
US7834376B2 (en) | 2005-03-04 | 2010-11-16 | Siliconix Technology C. V. | Power semiconductor switch |
WO2006105015A2 (en) | 2005-03-25 | 2006-10-05 | Stats Chippac Ltd. | Flip chip interconnection having narrow interconnection sites on the substrate |
US8841779B2 (en) * | 2005-03-25 | 2014-09-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate |
JP2006278913A (ja) * | 2005-03-30 | 2006-10-12 | Toyota Motor Corp | 回路装置とその製造方法 |
US7538389B2 (en) * | 2005-06-08 | 2009-05-26 | Micron Technology, Inc. | Capacitorless DRAM on bulk silicon |
US20070023923A1 (en) * | 2005-08-01 | 2007-02-01 | Salmon Peter C | Flip chip interface including a mixed array of heat bumps and signal bumps |
US20070023889A1 (en) * | 2005-08-01 | 2007-02-01 | Salmon Peter C | Copper substrate with feedthroughs and interconnection circuits |
US20070023904A1 (en) * | 2005-08-01 | 2007-02-01 | Salmon Peter C | Electro-optic interconnection apparatus and method |
US7586747B2 (en) | 2005-08-01 | 2009-09-08 | Salmon Technologies, Llc. | Scalable subsystem architecture having integrated cooling channels |
US8368165B2 (en) | 2005-10-20 | 2013-02-05 | Siliconix Technology C. V. | Silicon carbide Schottky diode |
TWI311451B (en) * | 2005-11-30 | 2009-06-21 | Murata Manufacturing Co | Ceramic substrate, electronic device, and manufacturing method of ceramic substrate |
JP4638382B2 (ja) * | 2006-06-05 | 2011-02-23 | 田中貴金属工業株式会社 | 接合方法 |
WO2008016619A1 (en) | 2006-07-31 | 2008-02-07 | Vishay-Siliconix | Molybdenum barrier metal for sic schottky diode and process of manufacture |
KR20080042012A (ko) * | 2006-11-08 | 2008-05-14 | 산요덴키가부시키가이샤 | 소자 탑재용 기판, 그 제조 방법, 반도체 모듈 및 휴대기기 |
US7595553B2 (en) * | 2006-11-08 | 2009-09-29 | Sanyo Electric Co., Ltd. | Packaging board and manufacturing method therefor, semiconductor module and mobile apparatus |
US7659192B2 (en) * | 2006-12-29 | 2010-02-09 | Intel Corporation | Methods of forming stepped bumps and structures formed thereby |
US9084377B2 (en) * | 2007-03-30 | 2015-07-14 | Stats Chippac Ltd. | Integrated circuit package system with mounting features for clearance |
SG148056A1 (en) * | 2007-05-17 | 2008-12-31 | Micron Technology Inc | Integrated circuit packages, methods of forming integrated circuit packages, and methods of assembling intgrated circuit packages |
JP5101169B2 (ja) * | 2007-05-30 | 2012-12-19 | 新光電気工業株式会社 | 配線基板とその製造方法 |
JP2009081366A (ja) * | 2007-09-27 | 2009-04-16 | Elpida Memory Inc | バッチ処理装置 |
JP4431606B2 (ja) * | 2007-10-05 | 2010-03-17 | シャープ株式会社 | 半導体装置、半導体装置の実装方法、および半導体装置の実装構造 |
JP2009224492A (ja) * | 2008-03-14 | 2009-10-01 | Oki Semiconductor Co Ltd | 半導体装置及びその製造方法 |
JP5366674B2 (ja) * | 2008-06-27 | 2013-12-11 | パナソニック株式会社 | 実装構造体および実装方法 |
TW201011878A (en) * | 2008-09-03 | 2010-03-16 | Phoenix Prec Technology Corp | Package structure having substrate and fabrication thereof |
JP5101451B2 (ja) | 2008-10-03 | 2012-12-19 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
CN101728289B (zh) * | 2008-10-10 | 2011-12-28 | 哈尔滨工业大学深圳研究生院 | 一种面阵封装电子元件的室温超声波软钎焊方法 |
JP2010171386A (ja) * | 2008-12-26 | 2010-08-05 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP2010161136A (ja) * | 2009-01-07 | 2010-07-22 | Panasonic Corp | 半導体装置及びその製造方法 |
CN102282659B (zh) * | 2009-02-04 | 2013-11-20 | 松下电器产业株式会社 | 半导体基板结构及半导体装置 |
US8410374B2 (en) | 2009-02-27 | 2013-04-02 | Ibiden Co., Ltd. | Printed wiring board |
US8461462B2 (en) * | 2009-09-28 | 2013-06-11 | Kyocera Corporation | Circuit substrate, laminated board and laminated sheet |
US8476757B2 (en) * | 2009-10-02 | 2013-07-02 | Northrop Grumman Systems Corporation | Flip chip interconnect method and design for GaAs MMIC applications |
US20110227216A1 (en) * | 2010-03-16 | 2011-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Under-Bump Metallization Structure for Semiconductor Devices |
JP4823375B1 (ja) * | 2010-05-28 | 2011-11-24 | 株式会社東芝 | 電子機器 |
JP5229296B2 (ja) * | 2010-10-14 | 2013-07-03 | 日本テキサス・インスツルメンツ株式会社 | Icチップ上への電子部品の実装 |
KR20130007124A (ko) | 2011-06-29 | 2013-01-18 | 삼성전자주식회사 | 유기 보호막을 갖는 조인트 구조 |
CN102244061A (zh) * | 2011-07-18 | 2011-11-16 | 江阴长电先进封装有限公司 | Low-k芯片封装结构 |
US20130044448A1 (en) * | 2011-08-18 | 2013-02-21 | Biotronik Se & Co. Kg | Method for Mounting a Component to an Electric Circuit Board, Electric Circuit Board and Electric Circuit Board Arrangement |
JP2013235882A (ja) * | 2012-05-07 | 2013-11-21 | Mitsubishi Electric Corp | 半導体装置 |
JP5832956B2 (ja) | 2012-05-25 | 2015-12-16 | 株式会社東芝 | 半導体発光装置 |
TWI451826B (zh) * | 2012-05-28 | 2014-09-01 | Zhen Ding Technology Co Ltd | 多層電路板及其製作方法 |
JP5869961B2 (ja) | 2012-05-28 | 2016-02-24 | 株式会社東芝 | 半導体発光装置 |
CN103458629B (zh) * | 2012-05-30 | 2016-12-21 | 碁鼎科技秦皇岛有限公司 | 多层电路板及其制作方法 |
US9269681B2 (en) * | 2012-11-16 | 2016-02-23 | Qualcomm Incorporated | Surface finish on trace for a thermal compression flip chip (TCFC) |
KR101284363B1 (ko) * | 2013-01-03 | 2013-07-08 | 덕산하이메탈(주) | 금속코어 솔더볼 및 이를 이용한 반도체 장치의 방열접속구조 |
US8896118B2 (en) * | 2013-03-13 | 2014-11-25 | Texas Instruments Incorporated | Electronic assembly with copper pillar attach substrate |
KR20150002492A (ko) * | 2013-06-28 | 2015-01-07 | 쿄세라 서킷 솔루션즈 가부시키가이샤 | 배선 기판 |
KR101673649B1 (ko) * | 2013-07-16 | 2016-11-08 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US20150097268A1 (en) * | 2013-10-07 | 2015-04-09 | Xintec Inc. | Inductor structure and manufacturing method thereof |
US20150115442A1 (en) * | 2013-10-31 | 2015-04-30 | Infineon Technologies Ag | Redistribution layer and method of forming a redistribution layer |
TWI576869B (zh) * | 2014-01-24 | 2017-04-01 | 精材科技股份有限公司 | 被動元件結構及其製作方法 |
CN104409434A (zh) * | 2014-08-28 | 2015-03-11 | 南通富士通微电子股份有限公司 | 半导体器件封装结构 |
JP6623508B2 (ja) * | 2014-09-30 | 2019-12-25 | 日亜化学工業株式会社 | 光源及びその製造方法、実装方法 |
KR102248876B1 (ko) * | 2014-12-24 | 2021-05-07 | 엘지디스플레이 주식회사 | 표시장치 어레이 기판 및 표시장치 |
KR101518760B1 (ko) * | 2014-12-31 | 2015-05-08 | 주식회사 자이스 | 전도성 접착제를 이용한 칩 접착 방법 |
JP7002134B2 (ja) * | 2016-08-29 | 2022-01-25 | 国立大学法人東北大学 | 磁気トンネル接合素子およびその製造方法 |
US10103095B2 (en) * | 2016-10-06 | 2018-10-16 | Compass Technology Company Limited | Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect |
US10923449B2 (en) | 2016-10-06 | 2021-02-16 | Compass Technology Company Limited | Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect |
US11069606B2 (en) | 2016-10-06 | 2021-07-20 | Compass Technology Company Limited | Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect |
CN106847936B (zh) * | 2016-12-07 | 2019-01-01 | 清华大学 | 基于金属键合的光电器件封装结构及其制造方法 |
JP7012489B2 (ja) * | 2017-09-11 | 2022-01-28 | ローム株式会社 | 半導体装置 |
JP7189672B2 (ja) * | 2018-04-18 | 2022-12-14 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
KR20200116577A (ko) | 2019-04-01 | 2020-10-13 | 삼성디스플레이 주식회사 | 표시 장치 및 그 제조 방법 |
KR20220022302A (ko) | 2020-08-18 | 2022-02-25 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3252745B2 (ja) * | 1997-03-31 | 2002-02-04 | 関西日本電気株式会社 | 半導体装置およびその製造方法 |
US20030001286A1 (en) * | 2000-01-28 | 2003-01-02 | Ryoichi Kajiwara | Semiconductor package and flip chip bonding method therein |
JP3891838B2 (ja) * | 2001-12-26 | 2007-03-14 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
-
2001
- 2001-12-26 JP JP2001393043A patent/JP3891838B2/ja not_active Expired - Fee Related
-
2002
- 2002-12-03 TW TW091135033A patent/TWI254398B/zh not_active IP Right Cessation
- 2002-12-18 US US10/321,567 patent/US6784554B2/en not_active Expired - Fee Related
- 2002-12-24 KR KR10-2002-0083019A patent/KR100531393B1/ko not_active IP Right Cessation
- 2002-12-26 CN CNB021593884A patent/CN100431142C/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI512862B (zh) * | 2013-03-25 | 2015-12-11 | Toshiba Kk | Manufacturing method of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US6784554B2 (en) | 2004-08-31 |
KR100531393B1 (ko) | 2005-11-28 |
KR20030055130A (ko) | 2003-07-02 |
CN1430272A (zh) | 2003-07-16 |
US20030127747A1 (en) | 2003-07-10 |
JP2003197673A (ja) | 2003-07-11 |
CN100431142C (zh) | 2008-11-05 |
TW200303588A (en) | 2003-09-01 |
JP3891838B2 (ja) | 2007-03-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI254398B (en) | Semiconductor device and its manufacturing method | |
JP3227444B2 (ja) | 多層構造のフレキシブル配線板とその製造方法 | |
TW494557B (en) | Flip chip type semiconductor device and method of manufacturing the same | |
TWI311348B (en) | Semiconductor device | |
JP3910493B2 (ja) | 半導体装置及びその製造方法 | |
US20020171152A1 (en) | Flip-chip-type semiconductor device and manufacturing method thereof | |
TWI237310B (en) | Semiconductor device and manufacturing method of the same | |
TW201018347A (en) | Wiring board capable of having built-in functional element and method for manufacturing the same | |
WO2007036994A1 (ja) | 半導体装置およびその製造方法並びにフィルムの製造方法 | |
TW200843064A (en) | Surface structure of a packaging substrate and a fabricating method thereof | |
US7679188B2 (en) | Semiconductor device having a bump formed over an electrode pad | |
US6936927B2 (en) | Circuit device having a multi-layer conductive path | |
JP2000100987A (ja) | 半導体チップモジュール用多層回路基板およびその製造方法 | |
US6883231B2 (en) | Method for fabricating a circuit device | |
JP7497576B2 (ja) | 配線基板及び配線基板の製造方法 | |
TW200808143A (en) | PCB electrical connection terminal structure and manufacturing method thereof | |
TW200837918A (en) | Surface structure of package substrate and method for manufacturing the same | |
JPH10275826A (ja) | 半導体装置およびその製造方法 | |
JP2004080006A (ja) | 半導体装置の製造方法 | |
JPH11145174A (ja) | 半導体装置およびその製造方法 | |
JP4286264B2 (ja) | 半導体装置及びその製造方法 | |
US7197817B2 (en) | Method for forming contact bumps for circuit board | |
JP3505328B2 (ja) | 半導体装置およびその製造方法 | |
JP2001118959A (ja) | 接続端子及びそれを用いた半導体装置 | |
JP2003037210A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |