CN106847936B - 基于金属键合的光电器件封装结构及其制造方法 - Google Patents

基于金属键合的光电器件封装结构及其制造方法 Download PDF

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Publication number
CN106847936B
CN106847936B CN201611120663.2A CN201611120663A CN106847936B CN 106847936 B CN106847936 B CN 106847936B CN 201611120663 A CN201611120663 A CN 201611120663A CN 106847936 B CN106847936 B CN 106847936B
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China
Prior art keywords
electrode
package substrates
photoelectric
photoelectric device
packaging
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CN201611120663.2A
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CN106847936A (zh
Inventor
张文剑
张清军
李元景
陈志强
赵自然
刘以农
刘耀红
邹湘
何会绍
李树伟
白楠
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Tsinghua University
Nuctech Co Ltd
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Tsinghua University
Nuctech Co Ltd
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Priority to CN201611120663.2A priority Critical patent/CN106847936B/zh
Publication of CN106847936A publication Critical patent/CN106847936A/zh
Priority to EP17879501.9A priority patent/EP3553828A4/en
Priority to PCT/CN2017/101361 priority patent/WO2018103397A1/zh
Priority to US15/718,919 priority patent/US10510683B2/en
Priority to JP2017190726A priority patent/JP6445109B2/ja
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Abstract

公开了一种基于金属键合的光电器件封装结构及其制造方法。根据实施例，一种光电器件封装结构可以包括光电芯片和封装基底。光电芯片包括：衬底，具有彼此相对的第一表面和第二表面；在衬底上形成的光电器件；以及在第一表面上形成的用于光电器件的电极。封装基底具有彼此相对的第一表面和第二表面，并包括从第一表面延伸到第二表面的导电通道。光电芯片以其第一表面面向封装基底的方式与封装基底叠置在一起，且光电芯片的第一表面上形成的电极与封装基底中的相应导电通道键合在一起。

Description

基于金属键合的光电器件封装结构及其制造方法
技术领域
本公开涉及光电器件封装，具体地，涉及基于金属键合的光电器件封装结构及其制造方法。
背景技术
在常规的背入式光电器件封装中，通常在裸芯的电极上植锡球，由此焊接到封装印刷电路板(PCB)上。为了增加可靠性，可以在裸芯与封装PCB板之间填充填料。由于常规封装PCB材料和裸芯材料(Si)热膨胀系数相差很大，很容易在温度变化时开裂。
另外，从其后续使用而言，一般需要将封装后的背入式光电器件再次焊接在相应的电路板上。也即，存在二次焊接问题。采用常规焊锡，植球存在二次融化过程。而如采用低温焊锡，对焊接工艺和焊料要求很高，极容易出现焊接问题。
需要提供新的封装技术来至少部分地解决上述问题。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种基于金属键合的光电器件封装结构及其制造方法。
根据本公开的一个方面，提供了一种光电器件封装结构，包括光电芯片和封装基底。光电芯片包括：衬底，具有彼此相对的第一表面和第二表面；在衬底上形成的光电器件；以及在第一表面上形成的用于光电器件的电极。封装基底具有彼此相对的第一表面和第二表面，并包括从第一表面延伸到第二表面的导电通道。光电芯片以其第一表面面向封装基底的方式与封装基底叠置在一起，且光电芯片的第一表面上形成的电极与封装基底中的相应导电通道键合在一起。
根据本公开的另一方面，提供了一种封装光电芯片的方法。光电芯片包括：衬底，具有彼此相对的第一表面和第二表面；在衬底上形成的光电器件；以及在第一表面上形成的用于光电器件的电极。该方法包括：提供封装基底，该封装基底具有彼此相对的第一表面和第二表面，并包括从第一表面延伸到第二表面的导电通道；将光电芯片以其第一表面面向封装基底的方式叠置到封装基底上；以及将光电芯片的第一表面上形成的电极与封装基底中的相应导电通道键合在一起。
根据本公开的实施例，不仅可以降低封装工艺和使用难度，还可以有效提高器件的可靠性和光电转化效率。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1是示出了根据本公开实施例的光电芯片的示意截面图；
图2是示出了根据本公开实施例的封装基底的示意截面图；
图3是示出了根据本公开实施例的对光电芯片和封装基底进行键合的示意图；
图4是示出了根据本公开实施例的光电器件封装结构的示意截面图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
图1是示出了根据本公开实施例的光电芯片的示意截面图。
如图1所示，根据该实施例的光电芯片100例如是在衬底100上制造光电器件之后尚未封装的裸芯。衬底100可以是半导体衬底如硅衬底，并包括彼此相对的第一表面101-1S和第二表面101-2S。第一表面101-1S和第二表面101-2S可以彼此大致平行。例如，可以在硅晶圆上通过半导体工艺制造光电器件，并将硅晶圆切片，切片后的晶圆部分形成衬底100，且衬底100上包括制造的光电器件(以及可能存在的外围部件)。这些光电器件可以包括相应的电极区域103，例如，在光电二极管的情况下，阳极和阴极。这些电极区域103例如可以是衬底101中的掺杂区，如p型掺杂区或n型掺杂区。
在衬底101的第一表面101-1S一侧，可以形成有电极107，用以将光电器件的电极区域103引出到外部，以便进行适当的电连接。根据半导体制造工艺，可以在第一表面101-1S一侧形成金属化叠层(metalization)，电极107可以包括在这种金属化叠层中。例如，金属化叠层可以包括一层或多层层间介质层105，可以在层间介质层105中形成通孔或沟槽，并在其中填充导电材料如金属，从而形成导电通道。这些导电通道可以包括过孔(via)和/或金属互连(interconnect)。例如，可以通过大马士革工艺来形成金属化叠层。这些导电通道可以构成电极107，各电极107可以与相应的电极区域103电连接。根据本公开的实施例，电极107可以包括Au或Ti。
此外，在形成金属化叠层时，可以在各电极107之间保留一些导电材料109(但是与电极107分离，以避免不必要的电连接)。残留的导电材料109可以与电极107在相同的工艺中形成，故而它们的上表面可以大致共面。这些导电材料109在后继键合时有助于保持光电芯片100与封装基底之间的距离，从而有助于增强机械强度。
在该示例中，光电芯片100可以是背入式的，即，入射光可以从第二表面101-2S一侧入射。这样，在第一表面101-1S一侧形成的各种部件如电极等不会影响光的入射。
图2是示出了根据本公开实施例的封装基底的示意截面图。
如图2所示，根据该实施例的封装基底200可以包括绝缘基底，例如玻璃基底、陶瓷基底等。为了保证可靠性，特别是为了应对温度变化，封装基底200的热膨胀系数可以与衬底101的热膨胀系数基本上一致。例如，在衬底101为硅衬底的情况下，封装基底200可以包括硼硅玻璃。这样，可以减小在温度变化时芯片100与封装基底200之间开裂的可能性。
封装基底200可以具有彼此相对的第一表面201-1S和第二表面201-2S。第一表面201-1S和第二表面201-2S可以彼此大致平行。在封装基底200中，可以形成从第一表面201-1S延伸到第二表面201-2S的导电通道203。例如，可以形成从第一表面201-1S延伸到第二表面201-2S贯穿封装基底200的通孔T，并在通孔T中填充导电材料如金属来形成导电通道203。根据本公开的实施例，导电通道203可以包括AuPbTi或AuTi。在图2的示例中，导电材料形成于通孔T的底部和侧壁上。但是，本公开不限于此，例如，导电材料可以填满通孔T。
在本公开的技术中，封装基板200随后将以第二表面201-2S面向光电芯片100的方式叠置到光电芯片100上。因此，第二表面201-2S一侧优选地可以是平坦的。也即，导电通道203的底面可以与封装基板200的第二表面201-2S基本上共面。另外，在第一表面201-1S一侧，导电通道203可以延伸到第一表面201-1S上，以便随后进行电连接，例如焊接到电路板。
封装基底200可以是针对光电芯片100专门设计的专用封装基底。例如，封装基底200上导电通道203的布局可以与光电芯片100上电极107的布局实质上相同。于是，当封装基底200与光电芯片100相叠置时，导电通道203可以与电极107一一对应，且彼此相对。
或者，封装基底200可以是通用封装基底。例如，可以按照一定的间距，在封装基底200上形成导电通道203的阵列。当封装基底200与光电芯片100相叠置时，封装基底200上的至少一部分导电通道203可以与光电芯片100上的电极107相对应，且彼此相对。当然，这种通用的封装基底200也可以用于布局不同于光电芯片100的其他芯片。
图3是示出了根据本公开实施例的对光电芯片和封装基底进行键合的示意图。
如图3所示，在键合机(未示出)中，可以将光电芯片100和封装基底200相叠置。具体地，可以使光电芯片100的第一表面101-1S一侧面向封装基底200的第二表面201-2S一侧。另外，可以调整光电芯片100和/或封装基底200的位置，使得光电芯片100上的电极107可以对准封装基底200上的相应导电通道203。
然后，可以在键合机中施加一定的温度(例如，约400-500℃)和压力(例如，约2000-4000mBar)，使得电极107和导电通道203能够彼此键合在一起(例如，由于金属材料熔融而彼此结合在一起)。
根据本公开的实施例，在键合之后，还可以从光电芯片100的第二表面101-2S一侧，减薄光电芯片。例如，如图4所示，可以减薄衬底101。根据一示例，可以先通过机械方式，使得光电芯片100减薄至约140-200μm；然后，可以通过化学方式或化学机械方式，使得光电芯片100减薄至约50-140μm。这种减薄的厚度有利于光生载流子收集，可以有效提高光电转化效率。
根据本公开实施例的封装结构300可以忍耐更高的温度(可达约400℃以上)，降低了后继焊接难度，且牢固度(键合强度)明显提高，显著改善了器件可靠性。另外，后继无需填充填料。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (11)

1.一种光电器件封装结构，包括：
光电芯片，包括：
衬底，具有彼此相对的第一表面和第二表面；
在衬底上形成的光电器件；
在第一表面上形成的用于光电器件的电极；以及
在第一表面上各电极之间形成的由电极的材料构成的增强层，其中，增强层与电极相分离，且增强层背对第一表面的表面与电极背对第一表面的表面共面；以及
封装基底，具有彼此相对的第一表面和第二表面，并包括从第一表面延伸到第二表面的导电通道，其中，导电通道在封装基底的第二表面一侧的端面与封装基底的第二表面共面，
其中，光电芯片以其第一表面面向封装基底的第二表面的方式与封装基底叠置在一起，且光电芯片的第一表面上形成的电极与封装基底中的相应导电通道键合在一起。
2.根据权利要求1所述的光电器件封装结构，其中，光电芯片的厚度为50-140μm。
3.根据权利要求1所述的光电器件封装结构，其中，电极包括在衬底上形成的金属化叠层中。
4.根据权利要求1或3所述的光电器件封装结构，其中，电极包括Au或Ti。
5.根据权利要求1所述的光电器件封装结构，其中，封装基底的热膨胀系数与衬底的热膨胀系数基本上一致。
6.根据权利要求5所述的光电器件封装结构，其中，衬底包括硅，封装基底包括硼硅玻璃。
7.根据权利要求1所述的光电器件封装结构，其中，导电通道包括AuPbTi或AuTi。
8.一种封装光电芯片的方法，其中，光电芯片包括：衬底，具有彼此相对的第一表面和第二表面；在衬底上形成的光电器件；在第一表面上形成的用于光电器件的电极；以及在第一表面上各电极之间形成的由电极的材料构成的增强层，其中，增强层与电极相分离，且增强层背对第一表面的表面与电极背对第一表面的表面共面，
该方法包括：
提供封装基底，该封装基底具有彼此相对的第一表面和第二表面，并包括从第一表面延伸到第二表面的导电通道，其中，导电通道在封装基底的第二表面一侧的端面与封装基底的第二表面共面；
将光电芯片以其第一表面面向封装基底的第二表面的方式叠置到封装基底上；以及
将光电芯片的第一表面上形成的电极与封装基底中的相应导电通道键合在一起。
9.根据权利要求8所述的方法，其中，通过施加一定的温度和压力，使得电极和导电通道键合在一起。
10.根据权利要求9所述的方法，其中，键合时的温度在400-500℃，压力在2000-4000mBar。
11.根据权利要求8所述的方法，还包括：从光电芯片的第二表面一侧减薄光电芯片。
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JP6445109B2 (ja) 2018-12-26
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