CN111357102A - 用于多芯片模块的非嵌入式硅桥芯片 - Google Patents

用于多芯片模块的非嵌入式硅桥芯片 Download PDF

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Publication number
CN111357102A
CN111357102A CN201880074024.8A CN201880074024A CN111357102A CN 111357102 A CN111357102 A CN 111357102A CN 201880074024 A CN201880074024 A CN 201880074024A CN 111357102 A CN111357102 A CN 111357102A
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substrate structure
chip
semiconductor
bridge chip
solder bumps
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CN201880074024.8A
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E·莱巴顿
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International Business Machines Corp
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International Business Machines Corp
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Abstract

一种方法包括将两个或更多个半导体芯片电连接到硅桥芯片，以及将所述两个或更多个半导体芯片电连接到衬底结构，所述硅桥芯片延伸到所述衬底结构中的凹部中，使得所述硅桥芯片的顶面基本上与所述衬底结构的顶面齐平。

Description

用于多芯片模块的非嵌入式硅桥芯片
背景技术
本发明总体上涉及半导体器件的封装，并且更具体地涉及形成具有非嵌入式硅桥芯片的多芯片模块的方法。
多芯片模块通常是指包括多个集成电路(IC或芯片)的电子组件。某些多芯片模块可能包括多个集成电路，这些集成电路二维地排列在整个衬底上，例如层压衬底(例如PCB)或陶瓷衬底。此类技术在行业中通常称为二维或2D封装。
以二维技术为基础，一些多芯片模块包括在多个集成电路和衬底之间并将其分离的硅中介层。此类技术在行业中通常被称为二维或2.5D封装。2.5D封装由于其巨大的容量和性能而特别具有优势。
最后，其他多芯片模块可以包括芯片堆叠封装，其具有以三维或垂直堆叠的方式排列的多个芯片。3D芯片堆叠封装由于增加了封装密度、减小了占位面积并提高了带宽而特别有利，这是因为使用硅通孔可以实现较短的连接长度。此类技术在行业中通常称为三维或3D封装。
发明内容
在本发明的实施例中，一种方法包括将：两个或更多个半导体芯片电连接到硅桥芯片，并将所述两个或更多个半导体芯片电连接到衬底结构，所述硅桥芯片延伸到所述衬底结构的凹部中，使得所述硅桥芯片的顶面与所述衬底结构的顶面基本上齐平。
在本发明的另一实施例中，一种方法包括提供两个或更多个半导体芯片，其中，第一多个焊料凸块位于两个或更多个半导体芯片的内顶面上，并且第二多个焊料凸块位于所述两个或更多个半导体芯片的外顶面，提供硅桥芯片，提供衬底结构，所述衬底结构包括凹部，利用第一多个焊料凸块将所述两个或更多个半导体芯片电连接到所述硅桥芯片，使用第二多个焊料凸块将所述两个或更多个半导体芯片电连接到所述衬底结构，所述硅桥芯片延伸到所述衬底结构中的凹部中，使得所述硅桥芯片的顶面与所述衬底结构的顶面基本上齐平，将盖子附接到所述衬底结构的顶面和所述两个或更多个半导体芯片的底面，并且在所述衬底结构的底面上形成第三多个焊料凸块。
在本发明的另一实施例中，一种半导体结构包括电连接至衬底结构的两个或更多个半导体芯片；以及电连接所述两个或更多个半导体芯片的硅桥芯片，所述硅桥芯片在所述衬底结构的区域内延伸，使得所述硅桥芯片的顶面与所述衬底结构的顶面基本上齐平。
附图说明
结合附图，将最好地理解以下通过示例的方式给出的详细描述，而不是仅仅将本发明限制于此，在附图中：
图1描绘了根据本发明实施例的多芯片模块的组装中的初始步骤；
图2A描绘了根据本发明实施例的衬底结构的剖视图；
图2B示出了沿剖面线A-A'截取的图2A的俯视图；
图3描绘了根据本发明实施例的硅桥芯片；
图4描绘了将硅桥芯片附接到初始结构；
图5示出了根据本发明的实施例的翻转临时衬底；
图6描绘了从半导体芯片分离所述临时衬底；
图7A描绘了根据本发明实施例的多芯片模块的截面图；
图7B示出了沿剖面线A-A'截取的图7A的俯视图；
图8A描绘了根据本发明实施例的衬底结构的截面图；
图8B示出了沿剖面线A-A'截取的图8A的俯视图；
图9示出了根据本发明的实施例的翻转临时衬底；
图10描绘了从半导体芯片分离所述临时衬底；
图11A描绘了根据本发明的实施例的多芯片模块的剖视图；
图11B描绘了沿截面线A-A'截取的图11A的俯视图；
图12描绘了根据本发明的实施例的替代的多芯片模块的截面图；和
图13描绘了将硅桥芯片结合到所述多芯片模块。
附图不一定按比例绘制。附图仅是示意性表示，并非意图描绘本发明的特定参数。附图仅旨在描绘本发明的典型实施例。在附图中，相同的标号表示相同的元素。
具体实施方式
本文公开了本发明的实施例；然而，可以理解的是，本发明的公开实施例仅是说明可以以各种形式体现的要求保护的结构和方法。然而，本发明可以以许多不同的形式实施，并且不应被解释为限于这里阐述的本发明的示例性实施例。在说明书中，可以省略众所周知的特征和技术的细节，以避免不必要地使本发明的实施例难以理解。
出于下文描述的目的，诸如“上”、“下”、“右”、“左”、“垂直”、“水平”、“上”、“下”及其派生词等术语应涉及如附图所示的本发明涉及公开的结构和方法。诸如“在......上方”、“在上方”、“在顶部”，“在......顶部”，“位于...上”或“位于顶部”之类的术语是指第一元素(例如第一结构)存在于第二元素(例如第二结构)上。其中在第一元件和第二元件之间可以存在中间元件，例如界面结构。术语“直接接触”是指第一元件(例如第一结构)和第二元件(例如第二结构)在两个元件的界面处没有任何中间导电、绝缘或半导体层的情况下被连接。
为了不使本发明的实施例的呈现不清楚，在下面的详细描述中，可以将本领域中已知的一些处理步骤或操作组合在一起以用于呈现和用于说明目的，并且在某些情况下可以不再详细描述。在其他情况下，可能根本不描述本领域中已知的一些处理步骤或操作。应当理解，以下描述相当集中于本发明的各种实施例的独特特征或元件。
当前的半导体技术集中于制造工艺的继续改进，其可以允许制造高密度、高性能和低成本的半导体芯片(也称为“裸芯”)。多芯片模块或封装可能具有以降低的成本提高架构灵活性的潜力，但这样做必须以经济有效的方式提供适当的裸芯到裸芯互连密度。互连密度是半导体封装中的重要考虑因素，主要是因为裸芯连接数量不足可能会限制带宽容量，这会对逻辑-逻辑和/或逻辑-存储器通信产生负面影响。
现代半导体封装技术需要最大数量的裸芯到裸芯互连。针对此限制的典型解决方案可能包括实施2.5D技术，该技术建议使用硅中介层和硅通孔(TSV)以较小的占位面积以硅互连速度连接裸芯。但是，最终的互连布局非常复杂，所需的制造技术可能会延迟流片，并降低良率。最新的方法包括在制造过程中将小的硅桥式芯片嵌入有机衬底中。但是，嵌入小的硅桥芯片的过程非常复杂。
因此，本发明的实施例除其他潜在益处外，可以提供一种形成包括非嵌入式硅桥式裸芯或芯片的多芯片模块的方法。通过实施所提出的方法，本发明的实施例可以消除对通常在其他2.5D方法中使用的大型硅中介层的需要，并且在提高生产率的同时降低了布局复杂性。
本发明总体上涉及半导体器件的封装，并且更具体地涉及形成具有非嵌入式硅桥芯片的多芯片模块的方法。形成具有非嵌入式硅桥芯片的多芯片模块的一种方法可以包括在衬底结构内形成凹部，并使用芯片粘合工艺将硅桥芯片附着到衬底结构上。下面参照图1至图11B详细描述可形成具有非嵌入式硅桥芯片的多芯片模块的本发明的实施例。
现在参考图1，其示出了组装多芯片模块的初始步骤。在该步骤，可以形成或提供包括多个半导体芯片102的初始结构100。仅出于说明的目的，在无限制的情况下，在图1中示出了两个半导体芯片102；但是，根据多芯片设计中所需的芯片数量，可以考虑使用其他半导体芯片。半导体芯片102可以各自包括硅衬底或其他已知的半导体衬底。
在制造过程的该步骤，所述半导体芯片102包括焊料凸块104、106。所述焊料凸块104、106可以形成在所述半导体芯片102的底部上方并与之直接接触。通常，金属化的焊盘被集成到半导体芯片102的表面中，并允许所述半导体芯片102(这里是所述初始结构100)电连接到其他衬底结构或衬底。所述焊料凸块104、106随后用于在所述初始结构100的金属化焊盘与邻接结构的金属化焊盘之间形成电连接，例如，如下所述的层压衬底。可以保留所述焊料凸块104以将所述初始结构100电连接到衬底结构200(图2A)，如下所述，所述焊料凸块106可以被设计用于经由硅桥芯片300(图3)将一个半导体芯片102电连接到另一半导体芯片102。应当注意，形成所述焊料凸块104、106的过程是典型的并且是本领域技术人员众所周知的。所述焊料凸块104可以具有与所述焊料凸块106相同的大小、小于或大于焊料凸块106。在本发明的一个实施例中，使所述焊料凸块104大于所述焊料凸块106对允许所述两个半导体芯片(102)之间的连接关系具有更高的密度是特别有益的。
现在参考图2A-2B，示出了衬底结构200的不同视图，图2A示出了所述衬底结构200的截面图，并且图2B示出了沿截面线A-A'截取的图2A的俯视图。所述衬底结构200可以是例如层压衬底、陶瓷衬底或印刷电路板(PCB)。
衬底结构200可以包括可以形成在层间电介质202中的各种金属互连结构206(以下称为“互连结构”)。所述互连结构206通常可以根据工艺通过层叠多层电介质和金属来形成。在制造层压衬底、陶瓷衬底或PCB方面众所周知。
所述衬底结构200可以进一步包括金属层204、208(也称为“金属化焊盘”)。通常，所述互连结构206在所述金属层204和所述金属层208之间提供必需的电连接。这样，所述金属层204、208提供电焊盘以将所述衬底结构200连接或接合到另一衬底结构，例如，如图1的所述初始结构100的所述金属层204、208通常可以包括通过任何合适的技术形成的富铜材料。
凹部210可以形成在所述衬底结构200中，如图2A-2B所示。最典型地，可以在所述衬底结构200基本完成之后作为最后步骤添加所述凹部210。在这种情况下，将使用激光烧蚀、离子蚀刻或物理钻孔/铣削来蚀刻出所述凹部210，以去除所述层间电介质202的一部分。可替代地，所述凹部210可被结合到所述衬底结构200的设计中并将在制造过程中合并。可以以这样的方式设计所述衬底结构200：使得所述衬底结构200内凹部210的位置不影响所述互连结构206或其它电子设备(未示出)。在本发明的一个实施例中，所述凹部210通常位于所述衬底结构200的中心。在本发明的另一个实施方案中，所述凹部210位于所述衬底结构200上的任何位置，例如，更靠近所述衬底结构200的一个边缘或角落。在所有情况下，所述凹部的位置将与所述硅桥芯片(300)的位置相对应。
在所有情况下，所述凹部的尺寸均合适以容纳以下描述的硅桥芯片。在本发明的各种实施例中，所述凹部210的形状将对应于所述硅桥芯片(300)的总体形状。例如，正方形凹部将用于正方形桥芯片，而矩形凹部将用于矩形硅桥芯片。在本发明的其他实施例中，所述凹部的形状可以不对应于所述硅桥芯片的形状。例如，方形凹部可以用于圆形硅桥芯片。为了适应所述硅桥芯片的尺寸和形状，所述凹部210可以略大于所述硅桥芯片的实际尺寸和形状。在实践中，例如，所述凹部210可以是几平方毫米，深度在大约10μm至大约1mm的范围内以容纳所述桥接芯片。
现在参考图3，示出了硅桥芯片300。所述硅桥芯片300可以与所述半导体芯片102相同的方式形成，并且可以包括类似的布线组件。例如，所述硅桥芯片300可以包括层间电介质302，其中可以形成互连结构(未示出)和其他电子器件(未示出)。所述硅桥芯片300还包括金属层304，包括金属化的焊盘。像其他结构一样，所述金属化的焊盘有助于使用已知的焊料凸块连接技术将所述硅桥芯片300连接到其他衬底结构。在本发明的实施例中，如下面将详细说明的，所述硅桥芯片300随后被附接到所述初始结构100以将两个半导体芯片102电接合到一起。
所述硅桥芯片300可具有可集成到多芯片封装中的任何尺寸。例如，所述硅桥芯片300的宽度可以在大约1mm至大约5mm的范围内，长度可以在大约1mm至大约20mm的范围内，以适应两个芯片102之间的连接。所述硅桥芯片可以足够大以电连接两个以上的芯片102。例如，所述硅桥芯片300可以为大约5毫米至大约20平方毫米，以促进四个芯片102之间的电连接。
现在参考图4，硅桥芯片300可以附接到所述初始结构100。具体地，使用本领域公知的典型芯片附接工艺将所述硅桥芯片300接合至所述半导体芯片102。
首先，将所述半导体芯片102附接到临时衬底400，所述临时衬底400可以支撑所述半导体芯片102以准备附接所述硅桥芯片300。在后续处理中，所述临时衬底400还将在附接所述硅桥芯片300之后的支撑组件。在本发明的替代实施例中，可以将所述硅桥芯片300结合到两个半导体芯片200，然后将所述组件结合到所述临时支撑件400。通常，将使用粘合材料(未示出)来将所述半导体芯片102附接到所述临时衬底400。在一些情况下，所述半导体芯片102将被附接到所述临时衬底400，使得它们可以随后被分离。例如，选择的粘合剂或替代的附接方法将允许随后移除所述临时衬底400。所述临时衬底400可以包括硅晶片或其他结构上足够的材料。在本发明的另一个实施例中，所述临时衬底400可以包括玻璃晶片。
现在参考图5，将所述临时衬底400翻转并放置在所述衬底结构200上方。具体地，将所述临时衬底400翻转过来，以使具有所述焊料凸块104、106的所述半导体芯片102的底面向下。然后可以以这样的方式定位所述临时衬底400，使得所述硅桥芯片300与所述凹部210对准(图2A-2B)，并且所述焊料凸块104与所述衬底结构200中的匹配金属层204对准。
在制造过程的这一点上，可以使用本领域公知的过程来附接焊料凸块104以将半导体芯片102接合到金属层204。接下来，在大多数情况下，根据本领域公知的工艺，使用底部填充材料来填充半导体芯片102和衬底结构200之间的空隙，并在物理上彼此固定。另外，可以将粘性材料502放置在硅桥芯片300和衬底结构200的顶面之间(位于图2A-2B的凹部210的底部)。粘性材料502将物理地将硅桥芯片300接合到衬底结构200，从而为组件提供附加的结构支撑。粘性材料502可以包括任何已知的合适的粘合剂，例如已知的填充材料。
现在参考图6，可以将临时衬底400与半导体芯片102分离。在将硅桥芯片300和半导体芯片102附接到衬底结构200之后，可以释放和移除临时衬底400。应当注意，在释放临时衬底400之后，可以暴露半导体芯片102的顶部。
现在参照图7A-7B，可以形成盖702和焊料凸块704。图7A描绘了多芯片模块的截面图，图7B描绘了沿截面线A-A'截取的图7A的俯视图。
所述盖702可以对下方组件(例如，半导体芯片102)提供机械刚度和物理保护。所述盖702可以固定到所述衬底结构200的顶面和所述半导体芯片102的底面。所述盖702可以使用能够提供机械刚度和抗翘曲性的任何已知的环氧树脂固定到所述衬底结构200。用任何已知的粘合材料将其粘贴到所述半导体芯片102上。所述盖702可包括通常可位于中心处或附近的凹部(未示出)，以容纳所述半导体芯片102在所述衬底结构200上方的高度。所述盖702可以包括为下方组件提供机械刚度和物理保护的任何材料，例如镀镍的铜、阳极氧化铝、陶瓷或任何其他合适的材料。另外，根据本领域公知的方法，也可以在盖702与半导体芯片102之间使用导热膏或导热界面材料。
类似于所述焊料凸块104、106，可以形成所述焊料凸块704以将由半导体芯片102、硅桥芯片300和衬底结构200形成的多芯片结构连接到诸如母板或其他印刷电路板的其他结构或衬底。
现在参照图8A-8B，示出了包括凹部802的衬底结构800。图8A描绘了所述衬底结构800的截面图，图8B描绘了沿截面线A-A'截取的图8A的俯视图。
应当注意，所述衬底结构800类似于图2A和图2B的所述衬底结构200。而且，可以以与图2的所述凹部210相同的方式形成所述凹部802。然而，在这里，如图8A所示，所述凹部802延伸穿过所述衬底结构800的整个厚度。在形成所述凹部800之后，可以通过翻转所述临时衬底400来继续如将在下面详细描述的芯片接合工艺。
现在参考图9，可以将所述临时衬底400翻转并放置在所述衬底结构800上方。如上所述，将所述临时衬底400翻转过来，使得所述临时衬底400的顶侧包括所述半导体芯片102和面朝下的硅桥芯片300。然后可以对准所述临时衬底400，使得所述硅桥芯片300与所述凹部802对准，并且所述焊料凸块104与所述衬底结构800中的匹配金属层204对准。在制造过程中，焊料凸块104可以是附着以将半导体芯片102连接到金属层204。
现在参考图10，可以将所述硅桥芯片300附着到所述衬底结构800，并且可以将所述临时衬底400与所述半导体芯片102分离。具体地，在将所述硅桥芯片300和半导体芯片102附着到衬底结构800，可以释放所述临时衬底400。应当注意，在释放所述临时衬底400之后可以暴露半导体芯片102。
现在参照图11A-11B，可以形成盖702、焊料凸块704和塞子802。图11A描绘了所述多芯片模块的截面图，图11B描绘了沿截面线A-A'截取的图11A的俯视图。
如上所述，盖702可以形成为面向下的组件(例如，半导体芯片102)提供机械刚度和物理保护，而焊料凸块704可以形成为连接由半导体芯片102、硅桥芯片300和衬底结构800形成的多芯片结构到其他衬底结构或衬底。所述塞子804可以形成为机械地保持所述硅桥芯片300。所述塞子804可以由具有与所述衬底结构800相同的热特性的任何材料形成，例如相同的陶瓷或层压材料。
所述塞子804可以完全填充所述硅桥芯片300下方的所述凹部802(图10)的一部分，并且可以与所述衬底结构800的底面基本齐平或共面。
下面通过参考图12-13详细描述本发明的另一个实施例，通过该实施例可以形成具有非嵌入式硅桥芯片的多芯片模块。
现在参考图12-13，其中示出了本发明的替代实施例，其中硅桥芯片300直接附接到多芯片模块。
这里，已经形成了包括半导体芯片102、盖702、衬底结构200和焊料凸块702的多芯片模块(图12)。应当注意，尚未附着位于半导体芯片102的顶面上的焊料凸块106。如图13所示，这可以允许将所述硅桥芯片300直接附接到所述半导体芯片102。可以随后形成所述塞子804以如上所述地机械地保持所述硅桥芯片300。
因此，本发明的实施例提供了一种形成具有非嵌入式硅桥芯片的多芯片模块的方法，该方法可以消除对硅中介层的需求，从而在提高成品率的同时降低了布局复杂度。在所提出的方法中，所述硅桥芯片(300)未嵌入在所述衬底结构(200、800)内。此外，所述硅桥芯片(300)不是所述衬底结构制造过程的一部分，所述所述硅桥芯片(300)在其制造之后被装配在所述衬底结构(200、800)中的凹部内。
已经出于说明的目的给出了本发明的各种实施例的描述，但是这些描述并不旨在是穷举性的或限于所公开的实施例。在不脱离本发明范围的情况下，许多修改和变化对本领域普通技术人员将是显而易见的。选择这里使用的术语是为了最好地解释本发明的原理，对市场上发现的技术的实际应用或技术上的改进，或者使本领域的其他普通技术人员能够理解这里公开的本发明的实施例。

Claims (15)

1.一种方法，包括：
将两个或更多个半导体芯片电连接到硅桥芯片；以及
将所述半导体芯片电连接到衬底结构，其中，所述桥接芯片延伸到所述衬底结构中的凹部中，使得所述桥接芯片的顶面与所述衬底结构的顶面基本上齐平。
2.根据权利要求1所述的方法，还包括：
在所述衬底结构的顶面和两个或更多个的半导体芯片的底面安装盖；以及
在所述衬底结构的底面上形成多个焊料凸块。
3.根据权利要求1所述的方法，还包括：
在所述桥接芯片的底面和位于所述凹部的底部的所述衬底结构的表面之间放置粘性材料，其中所述粘性材料将所述桥接芯片物理地连接到所述衬底结构。
4.根据权利要求1所述的方法，其中，所述衬底结构中的所述凹部延伸穿过所述衬底结构的整个厚度。
5.根据权利要求3所述的方法，还包括：
形成与所述桥接芯片的底面直接接触的塞子，以使得所述塞子基本上填充位于所述桥接芯片下面的所述凹部的一部分，所述塞子机械地保持所述桥接芯片，其中所述塞子的底面基本上与所述衬底结构的底面齐平。
6.根据权利要求3所述的方法，还包括：
将所述半导体芯片电连接到所述衬底结构，使得所述凹部直接在所述两个或更多个半导体芯片的一部分的下方；
将所述桥接芯片电连接到所述半导体芯片，使得所述桥接芯片的顶面与所述衬底结构的顶面基本上齐平；以及
形成与所述桥接芯片的底面直接接触的塞子，使得所述塞子基本上填满所述桥接芯片下面的所述凹部的一部分，所述塞子机械地保持所述桥接芯片，其中所述塞子的底面基本上与所述衬底结构的底面齐平。
7.根据权利要求1所述的方法，其中，每个所述半导体芯片包括硅衬底，并且所述衬底结构包括层压衬底、陶瓷衬底或印刷电路板。
8.根据权利要求1所述的方法，包括：
在所述半导体芯片的内顶面上放置第一多个焊料凸块，并且在所述半导体芯片的外顶面上放置第二多个焊料凸块；
其中，将所述半导体芯片电连接至所述桥接芯片包括：使用所述第一多个焊料凸块将所述半导体芯片电连接至所述桥接芯片；
其中，将所述半导体芯片电连接到所述衬底结构包括：使用所述第二多个焊料凸块将所述半导体芯片电连接到所述衬底结构；以及，
其中，所述方法包括将盖子附接到所述衬底结构的所述顶面和所述半导体芯片的底面；以及
在所述衬底结构的底面上形成第三多个焊料凸块。
9.根据权利要求7所述的方法，其中，所述第二多个焊料凸块中的焊料凸块大于所述第一多个焊料凸块中的焊料凸块。
10.一种半导体结构，包括：
两个或多个电连接到衬底结构的半导体芯片；以及
电连接所述两个或更多半导体芯片的硅桥芯片，其中所述硅桥芯片在所述衬底结构的区域内延伸，使得所述硅桥芯片的顶面与所述衬底结构的顶面基本上平齐。
11.根据权利要求10所述的半导体结构，还包括：
盖，其安装到所述衬底结构的所述顶面和所述两个或更多个半导体芯片的底面；以及
在所述衬底结构的底面上的多个焊料凸块。
12.根据权利要求10所述的半导体结构，还包括：
在所述硅桥芯片的底面和位于所述硅桥芯片正下方的所述衬底结构的顶面之间的粘性材料，其中所述粘性材料将所述硅桥芯片物理地接合到衬底结构。
13.根据权利要求10所述的半导体结构，还包括：
与所述硅桥芯片的底面直接接触的塞子，使得所述塞子基本上填充位于所述硅桥芯片下方的所述衬底结构的一部分，所述塞子机械地保持所述硅桥芯片，其中所述塞子的底面是基本上与所述衬底结构的底面齐平。
14.根据权利要求10所述的半导体结构，还包括：
位于所述两个或更多半导体芯片的内顶面上的第一多个焊料凸块；以及
位于所述两个或更多个半导体芯片的外顶面上的第二多个焊料凸块，其中所述第二多个焊料凸块中的焊料凸块大于所述第一多个焊料凸块中的焊料凸块。
15.根据权利要求10所述的半导体结构，其中，所述两个或更多个半导体芯片中的每一个包括硅衬底，并且所述衬底结构包括层压衬底、陶瓷衬底或印刷电路板。
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CN104051420A (zh) * 2013-03-14 2014-09-17 英特尔公司 用于嵌入式互连桥封装的直接外部互连
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CN112490182A (zh) * 2020-11-25 2021-03-12 通富微电子股份有限公司 多芯片封装方法
WO2022198675A1 (zh) * 2021-03-26 2022-09-29 华为技术有限公司 多芯片模组及具有该多芯片模组的电子设备
WO2022249077A1 (en) * 2021-05-27 2022-12-01 International Business Machines Corporation Bonding of bridge to multiple semiconductor chips
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CN113643986A (zh) * 2021-08-10 2021-11-12 中国科学院微电子研究所 提高嵌入式硅桥与芯片间互联精度的结构的制作方法
CN113643986B (zh) * 2021-08-10 2024-04-09 中国科学院微电子研究所 提高嵌入式硅桥与芯片间互联精度的结构的制作方法
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US10483156B2 (en) 2019-11-19

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