JP5984912B2 - 積層型半導体の製造方法 - Google Patents

積層型半導体の製造方法 Download PDF

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JP5984912B2
JP5984912B2 JP2014506159A JP2014506159A JP5984912B2 JP 5984912 B2 JP5984912 B2 JP 5984912B2 JP 2014506159 A JP2014506159 A JP 2014506159A JP 2014506159 A JP2014506159 A JP 2014506159A JP 5984912 B2 JP5984912 B2 JP 5984912B2
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substrate
wall portion
electrode
electrodes
semiconductor device
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JPWO2013141091A1 (ja
Inventor
良章 竹本
良章 竹本
直裕 高澤
直裕 高澤
菊地　広
広 菊地
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Olympus Corp
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Olympus Corp
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Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Dicing (AREA)

Description

本発明は、積層型半導体の製造方法に関する。
半導体装置においては、その集積度を上げる技術が日夜進歩しており、これまで、主として回路パターンの微細化の促進により集積度が高められてきた。しかしながら、微細化そのものが限界を迎え、それ以上集積度を上げるために、従来の２次元構造から、構成を立体的にした３次元構造へ展開することが一つの解決策として期待されている。
３Ｄ−ＬＳＩを大きく分類すると、ＫＧＤ（Ｋｎｏｗｎ−Ｇｏｏｄ−Ｄｉｅ）のみを低精度のダイボンダで積層しワイヤボンドで半導体チップ間を接続する「簡易Ｃｈｉｐ積層」、バーンイン・テストを行った良品パッケージを積層する「パッケージ型積層」、そして、シリコン製のウェハ（基板）上に素子間の貫通電極やマイクロバンプを設け、ウェハもしくは半導体チップ同士を直接接続して形成する「貫通電極型積層（以下、ＴＳＶ：Ｔｈｒｏｕｇｈ Ｓｉ Ｖｉａ積層と称する）」に分類できる。
前２者は既に実用化の域にあり、ＴＳＶ積層が最終的な形態として期待されている。これは、例えばＤＲＡＭの場合、高度な微細化を待たずにメモリセルアレイウェハの単純な積層により、チップサイズや設計線幅の変更なく容量を増大できるためである。
さて、ＴＳＶ積層を以下の３つの方法に分類する。
（１）Ｃｈｉｐ−ｔｏ−Ｃｈｉｐ（Ｃ２Ｃ）：ＫＧＤ（Ｋｎｏｗｎ−Ｇｏｏｄ−Ｄｉｅ）同士を積層する簡便な手法である。
（２）Ｃｈｉｐ−ｔｏ−Ｗａｆｅｒ（Ｃ２Ｗ）：ウェハ上にＫＧＤを搭載するもので（１）と類似の系といえる。
（３）Ｗａｆｅｒ−ｔｏ−Ｗａｆｅｒ（Ｗ２Ｗ）：高歩留まりウェハを前提とし、ウェハ同士を直接貼り合わせる方式であり最終的な積層形態といえる。
本発明は、Ｗ２Ｗ方式の接合技術に関する。その場合のウェハとウェハを接合するウェハ接合装置の概要を図１１および図１２に示す。なお、ウェハ接合装置全体の概要は、例えば特許文献１に記載されており、公知のものである。このため、図示と説明を省略し、本発明に関係のある部分のみを図示し説明する。
２枚のウェハ１５１、１５２には、接続電極（電極）１５３が形成された電極領域１５４が設けられている。電極領域１５４の周囲は、ウェハ１５１、１５２以外には何も設けられないブランク領域となっている。電極領域１５４には、ウェハ１５１、１５２上にそれぞれ接続電極１５３が形成されており、ウェハ１５１、１５２上に形成された接続電極１５３同士を接合することによりウェハ１５１、１５２間での電気的接合を図っている。なお、接続電極１５３の中には、電気的導通には寄与せず、接合の強度を保つためのダミーも含まれている場合がある。
Ｗ２Ｗ方式においては、ウェハ１５１、１５２同士の対応する接続電極１５３同士が接するようにウェハ１５１、１５２を重ね合わせて接合する。
具体的には、ウェハ１５１、１５２の接続電極１５３が互いに接する様にして加圧板１５５、１５６の間に挟み、図示しないプレス装置によって、上下から加圧板１５５、１５６を加圧する。ウェハ１５１、１５２の接合には、接続電極１５３を加熱し、加圧して接合する加熱加圧接合が一般的に使用される。
このようなＷ２Ｗ方式の接合方式において、特許文献２では、前述の特許文献１とは異なる接合方法が開示されている。すなわち、特許文献２の接合方法は、図１１に示すように複数の接続電極１５３から形成される電極領域１５４を外周接続部（壁部）１５７で囲んだ電極構造とすることで、前記外周接続部１５７に囲まれた領域を任意の雰囲気とし、仮接合と本接合工程を有した製造工程を用いることによって、接続信頼性を高めている。
なお、ウェハ１５１、１５２を接合することで、複数の積層型半導体装置が形成される。
特開２００５−２５１９７２号公報 特開２００９−２２０１５１号公報
しかしながら、特許文献１および２の方法で製造された積層型半導体装置は、積層型半導体装置を個片化する工程、所謂ダイシング工程を実施する必要がある。ダイシング工程には、ブレードを用いた方式やレーザーを用いた方式が成されているが、いかなる方式においても、積層型半導体装置に少なからず物理的衝撃が生じる。その衝撃によって、前述の外周接続部１５７や接続電極１５３がダメージを受けることで、接続信頼性が低下することが懸念される。
なお、外周接続部１５７の領域を大きくすることによって接続電極１５３に与える衝撃を緩和する手段も考えられるが、その場合には接続しなければならない電極部が増加することによってウェハ全面で接続電極１５３を接合することが困難となる。
本発明はこのような事情に鑑みてなされたもので、個片化した際にも基板の電極同士の接続信頼性を確保することができる積層型半導体の製造方法を提供することを目的とする。
本発明の積層型半導体装置の製造方法は、一方の面に複数の第一の電極、およびそれぞれの前記第一の電極を囲うように立設した複数の第一の壁部が設けられた第一の基板と、第一の面に複数の第二の電極、およびそれぞれの前記第二の電極を囲うように立設した複数の第二の壁部が設けられた第二の基板とを、前記一方の面と前記第一の面とを対向させ、それぞれの前記第一の電極と前記第二の電極とを接続させるとともに、それぞれの前記第一の壁部のうち前記第一の壁部が立設する先端部とそれぞれの前記第二の壁部のうち前記第二の壁部が立設する先端部とを前記第一の壁部の全周にわたり接続することで互いに接続する接続工程と、前記第一の基板と前記第二の基板との間であってそれぞれの前記第一の壁部および前記第二の壁部の外側に封止部材を充填する封止工程と、前記第一の基板、前記第二の基板、および前記封止部材を、前記第一の基板の厚さ方向に見たときの隣り合う前記第一の壁部の中間部で切断する切断工程と、を備えることを特徴としている。
本発明の積層型半導体の製造方法によれば、個片化した際にも基板の電極同士の接続信頼性を確保することができる。
本発明の第１実施形態の積層型半導体装置の側面の断面図である。 図１中の切断線Ａ１−Ａ１の断面図である。 分割される前の両基板を対向配置した状態の側面の断面図である。 分割される前の第一の基板の要部の底面図である。 本実施形態の積層型半導体装置の製造方法の接続工程終了時の状態を説明する側面の断面図である。 図５中の切断線Ａ２−Ａ２の断面図である。 本発明の第２実施形態の積層型半導体装置の側面の断面図である。 分割される前の両基板を対向配置した状態の側面の断面図である。 本実施形態の積層型半導体装置の製造方法の接続工程終了時の状態を説明する側面の断面図である。 本発明の変形例の実施形態の積層型半導体装置における要部の断面図である。 従来のウェハ接合装置に用いられるウェハの平面図である。 同ウェハ接合装置でウェハを接合している状態を示す模式図である。
（第１実施形態）
以下、本発明に係る積層型半導体装置（以下、「半導体装置」と略称する。）の第１実施形態を、図１から図６を参照しながら説明する。
図１および図２に示すように、本半導体装置１は、一方の面１０ａに複数の第一の電極１１、およびこれら複数の第一の電極１１を囲うように立設した壁部１２が設けられた第一の基板１０と、第一の面２０ａに複数の第二の電極２１が設けられた第二の基板２０とを備えている。
なお、後述する素子１４、２４、および配線１５、２５は、説明の便宜上、図１および後述する図７のみに示している。
第一の基板１０は、シリコンなどの材料で、第一の基板１０の厚さ方向Ｘに見たときに矩形となる平板状に形成されている。第一の基板１０には、トランジスタなどの素子１４が内蔵されている。素子１４に設けられた不図示の接点は、ビアなどの配線１５を介して第一の電極１１に接続されている。
複数の第一の電極１１は、一方の面１０ａにおいて格子状に配置され、複数の第一の電極１１が全体として第一の電極領域Ｒ１１を構成している。厚さ方向Ｘに見た平面視において、例えば、それぞれの第一の電極１１は直径が数μｍ程度に形成され、第一の電極領域Ｒ１１は数ｍｍ角程度に形成されている。
壁部１２は、厚さ方向Ｘに見て、第一の電極領域Ｒ１１の外形を外側に拡大するとともに、第一の基板１０を内側に縮小した矩形状（矩形の輪郭状）に形成されている。壁部１２が一方の面１０ａから立設する立設方向は、厚さ方向Ｘの一方側Ｘ１となる。厚さ方向Ｘの長さは、第一の電極１１および第二の電極２１の和と、壁部１２とがほぼ等しくなるように設定されている。
この例では、壁部１２は、第一の電極１１と同一の金属、例えば銅や金などで形成されている。
第二の基板２０は、シリコンなどの材料で、厚さ方向Ｘに見たときに第一の基板１０と同一の形状となる平板状に形成されている。第二の基板２０には、素子１４と同様の素子２４が内蔵されている。素子２４に設けられた不図示の接点は、配線２５を介して第二の電極２１に接続されている。
複数の第二の電極２１は、第一の面２０ａにおいて、複数の第一の電極１１と同様の格子状に配置され、複数の第二の電極２１が全体として第二の電極領域Ｒ１２を構成している。
第一の基板１０と第二の基板２０とは、一方の面１０ａと第一の面２０ａとを対向させ、対応する第一の電極１１と第二の電極２１とを接続させるとともに、壁部１２のうち一方側Ｘ１の先端部を第一の面２０ａに全周にわたり接続した状態に配置されている。第一の電極１１と第二の電極２１とは、両電極１１、２１を加熱した状態で押圧することで電気的に接続されている。第二の基板２０と壁部１２とも、同様に接続されている。
第一の基板１０と第二の基板２０との間であって壁部１２の外側には、壁部１２の全周にわたりエポキシ樹脂（封止部材）３０が充填されている。第二の基板２０と壁部１２とを接続することと、エポキシ樹脂３０を充填することで、第一の基板１０と第二の基板２０との間であって壁部１２の内側となる内部空間Ｒ２０は、外部から気密に封止されている。
この例では、内部空間Ｒ２０は真空となるように減圧されている。ここで言う真空とは、大気圧よりも低い圧力のことを意味し、絶対圧力で、０Ｐａ以上１Ｐａ以下であることが好ましい。これにより、電極１１、２１の周囲は、真空雰囲気となっている。
第一の電極領域Ｒ１１と第二の電極領域Ｒ１２とで、電極領域Ｒ１０が構成される。以下では、各図において電極領域Ｒ１０に同一のハッチングを付して示すことにする。
半導体装置１は、配線１５、２５、および電極１１、２１を介して電気的に接続された素子１４、２４が、互いに信号を送受信しながら所定の処理を行うように構成されている。
次に、以上のように構成された半導体装置１を製造する、本実施形態の半導体装置１の製造方法について説明する。
本製造方法は、第一の基板１０と第二の基板２０とを接続する接続工程と、第一の基板１０と第二の基板２０との間にエポキシ樹脂３０を充填する封止工程と、基板１０、２０を切断する切断工程とを備えている。
本製造方法には、図３および図４に示すように、厚さ方向Ｘに見たときに略円形となる基板１０、２０が用いられる。そして、後述するように切断工程で基板１０、２０をスクライブライン（分割線）Ｓで切断して平面視で矩形状の個片領域Ｔに分割することで、個々の半導体装置１に分割（個片化）する。
このように、略円形となる基板１０、２０において、個片領域Ｔは略格子状に複数配置されている。
予め、第一の基板１０の個片領域Ｔごとに、素子１４および配線１５を形成するとともに、第一の基板１０の一方の面１０ａにそれぞれの配線１５に接続された第一の電極１１を設け、第一の電極領域Ｒ１１を構成しておく。そして、個片領域Ｔごとに第一の電極領域Ｒ１１を囲うように壁部１２を形成する。なお、この例では、第一の電極１１および壁部１２を一方の面１０ａに金属で形成しているため、第一の電極１１および壁部１２を同一の半導体製造プロセスで形成することができる。
同様に、第二の基板２０の個片領域Ｔごとに、素子２４および配線２５を形成するとともに、第二の基板２０の第一の面２０ａにそれぞれの配線２５に接続された第二の電極２１を設け、第二の電極領域Ｒ１２を構成しておく。
まず、接続工程において、不図示の真空チャンパ内で以下の工程を行う。図５および図６に示すように、第一の基板１０と第二の基板２０とを、一方の面１０ａと第一の面２０ａとを対向させ、第一の電極領域Ｒ１１の第一の電極１１と第二の電極領域Ｒ１２の第二の電極２１とを接続させるとともに、それぞれの壁部１２のうち一方側Ｘ１の先端部を第一の面２０ａに全周にわたり接続する。これにより、第一の基板１０と第二の基板２０とを互いに接続する。
具体的には、図示はしないが、公知の加圧装置の一対の加圧板の間に基板１０、２０を配置し、互いに接触させた第一の電極１１と第二の電極２１、壁部１２と第二の基板２０を不図示の加熱装置によりそれぞれ加熱した状態で一対の加圧板により基板１０、２０を厚さ方向Ｘに押圧することで、第一の電極１１と第二の電極２１、壁部１２と第二の基板２０をそれぞれ接合する。
次に、封止工程において、互いに接続された第一の基板１０と第二の基板２０との間であってそれぞれの壁部１２の外側に、加熱して流動性を高めたエポキシ樹脂３０を流し込む。壁部１２と第二の基板２０とは全周にわたり接続されているため、内部空間Ｒ２０内にエポキシ樹脂３０が流れ込むことはない。また、真空雰囲気においてエポキシ樹脂３０を流し込むため、エポキシ樹脂３０内に気体が混入するのを抑制し、基板１０、２０間にエポキシ樹脂３０を容易に充填させることができる。
この後で、加熱したエポキシ樹脂３０を冷却して、固化させる。
続いて、切断工程において、第一の基板１０、第二の基板２０、およびエポキシ樹脂３０を、図５および図６に示すスクライブラインＳでダイシングなどにより切断する。このスクライブラインＳは、厚さ方向Ｘに見たときの隣り合う壁部１２の中間部に設定される。すなわち、第一の基板１０の切断面と第二の基板２０の切断面との間に、全周にわたりエポキシ樹脂３０が配されるように切断する。
第一の基板１０と第二の基板２０との間はエポキシ樹脂３０が充填されているため、基板１０、２０を切断するときに作用する荷重をエポキシ樹脂３０で支持することができ、第一の電極１１と第二の電極２１との接合部、壁部１２と第二の基板２０との接合部に過大な荷重（衝撃）が作用するのが防止される。
スクライブラインＳで切断することで個片化され、半導体装置１が得られる。
これまで説明した接続工程から切断工程までの工程により、半導体装置１が製造される。
以上説明したように、本実施形態の半導体装置１、および半導体装置１の製造方法によれば、第二の基板２０と壁部１２とを壁部１２の全周にわたり接続させることと、エポキシ樹脂３０を充填させることで、壁部１２の内側となる内部空間Ｒ２０を気密に保持し、両電極１１、２１の接続状態を安定させることができる。
第一の基板１０と第二の基板２０との間であって壁部１２の外側にはエポキシ樹脂３０が充填されているため、基板１０、２０を切断するときに作用する荷重をエポキシ樹脂３０が支持する。したがって、基板１０、２０を個片化して半導体装置１を製造する際に、壁部１２と第二の基板２０との接続部に過大な荷重が作用するのが防止され、電極１１、２１同士の接続を確保することができる。
内部空間Ｒ２０は真空となるように減圧されているため、電極１１、２１が雰囲気により酸化などの影響を受けるのを抑制し、電極１１、２１同士の接続信頼性を確保することができる。
加熱して流動性を高めたときのエポキシ樹脂３０の粘度は、他の樹脂の粘度に比べて比較的低いため、第一の基板１０と第二の基板２０との間に容易にエポキシ樹脂３０を充填させることができる。
（第２実施形態）
次に、本発明の第２実施形態について図７から図９を参照しながら説明するが、前記実施形態と同一の部位には同一の符号を付してその説明は省略し、異なる点についてのみ説明する。
第１実施形態の半導体装置１は、壁部を第一の基板１０の一方の面１０ａのみに形成したが、図７に示す本実施形態の半導体装置２は、この壁部を第一の基板１０の一方の面１０ａおよび第二の基板２０の第一の面２０ａのそれぞれに形成したものとなっている。すなわち、本半導体装置２は、半導体装置１の壁部１２に代えて、第一の基板１０の一方の面１０ａに複数の第一の電極１１を囲うように立設した第一の壁部１７が設けられるとともに、第二の基板２０の第一の面２０ａに複数の第二の電極２１を囲うように立設した第二の壁部２７が設けられている。
第一の壁部１７は、第１実施形態の壁部１２とは厚さ（厚さ方向Ｘの長さ。）のみが異なるものである。第一の壁部１７の厚さは、各第一の電極１１の厚さに等しい。また、第一の壁部１７は、第一の電極１１と同一の金属で形成されている。このように構成することで、各第一の電極１１と第一の壁部１７とを、同一の半導体製造プロセスでより容易に形成することができる。
同様に、第二の壁部２７の厚さは各第二の電極２１の厚さに等しい。第一の壁部１７と第二の壁部２７とは、厚さ方向Ｘに見たときに重なるように（同一の形状に）形成されている。
第一の基板１０と第二の基板２０とは、一方の面１０ａと第一の面２０ａとを対向させ、対応する第一の電極１１と第二の電極２１とを接続させるとともに、第一の壁部１７のうち第一の壁部１７が立設する先端部と第二の壁部２７のうち第二の壁部２７が立設する先端部とを第一の壁部１７の全周にわたり接続した状態に配置されている。第一の壁部１７と第二の壁部２７とは、両壁部１７、２７を加熱した状態で押圧することで接続されている。
この例では、前述のエポキシ樹脂３０は、第一の基板１０と第二の基板２０との間であって第一の壁部１７および第二の壁部２７の外側に、第一の壁部１７の全周にわたり充填されている。
次に、以上のように構成された半導体装置２を製造する、本実施形態の半導体装置２の製造方法について説明する。
本実施形態の製造方法も、第１実施形態の製造方法と同様に接続工程、封止工程および切断工程を備えている。
予め、図８に示すように、第一の基板１０の個片領域Ｔごとに、複数の第一の電極１１からなる第一の電極領域Ｒ１１、および第一の電極領域Ｒ１１を囲うように第一の壁部１７を形成する。複数の第一の電極１１および第一の壁部１７の厚さおよび材質が前述のようになっているため、複数の第一の電極１１と第一の壁部１７とを、同一の半導体製造プロセスでより容易に形成することができる。
同様に、第二の基板２０の個片領域Ｔごとに、複数の第二の電極２１からなる第二の電極領域Ｒ１２、および第二の電極領域Ｒ１２を囲うように第二の壁部２７を形成する。
まず、接続工程において、図９に示すように、第一の基板１０と第二の基板２０とを、一方の面１０ａと第一の面２０ａとを対向させ、第一の電極領域Ｒ１１の第一の電極１１と第二の電極領域Ｒ１２の第二の電極２１とを接続させるとともに、それぞれの第一の壁部１７のうち第一の壁部１７が立設する先端部とそれぞれの第二の壁部２７のうち第二の壁部２７が立設する先端部とを第一の壁部１７の全周にわたり接続する。これにより、第一の基板１０と第二の基板２０とを互いに接続する。
次に、封止工程において、第一の基板１０と第二の基板１０との間であってそれぞれの第一の壁部１７および第二の壁部２７の外側にエポキシ樹脂３０を充填する。
続いて、切断工程において、第一の基板１０、第二の基板２０、およびエポキシ樹脂３０を、図９に示すスクライブラインＳで切断する。このスクライブラインＳは、厚さ方向Ｘに見たときの隣り合う第一の壁部１７の中間部に設定される。
これまで説明した接続工程から切断工程までの工程により、半導体装置２が製造される。
以上説明したように、本実施形態の半導体装置２、および半導体装置２の製造方法によれば、個片化した際にも基板１０、２０の電極１１、２１同士の接続信頼性を確保することができる。
本実施形態では、第一の壁部１７の厚さが各第一の電極１１の厚さに等しくなく、かつ、第二の壁部２７の厚さが各第二の電極２１の厚さに等しくないように構成してもよい。第一の壁部１７の厚さと第二の壁部２７の厚さとの和と、第一の電極１１の厚さと第二の電極２１の厚さとの和がほぼ等しければ、第一の基板１０と第二の基板２０とを良好に接続できるからである。
以上、本発明の第１実施形態および第２実施形態について図面を参照して詳述したが、具体的な構成はこの実施形態に限られるものではなく、本発明の要旨を逸脱しない範囲の構成の変更なども含まれる。
たとえば、前記第１実施形態および第２実施形態では、封止部材としてエポキシ樹脂を用いたが、封止部材はこれに限定されず、他にも熱可塑性樹脂や熱硬化性樹脂、有機材料などを適宜選択して用いることができる。ただし、封止部材は、加熱して流動性を有したときに粘度が低くなるものが好ましい。第一の基板１０と第二の基板２０との間に、隙間なく封止部材を充填できるからである。
壁部１２、１７、２７は、厚さ方向Ｘに見て矩形状に形成されているとした。しかし、壁部の形状はこれに限定されることなく、図１０に示す半導体装置３のように、壁部４２は、６角形などの矩形以外の多角形状に形成されていてもよいし、円形や楕円形に形成されていてもよい。
複数の第一の電極１１により構成される第一の電極領域Ｒ１１の形状も、円形や楕円形に形成されていてもよいし、多角形状に形成されていてもよい。第二の電極領域Ｒ１２についても同様である。
前記第１実施形態および第２実施形態では、内部空間Ｒ２０は、真空となるように減圧されているとしたが、窒素ガスまたは希ガスが充填されているように構成してもよい。ここで言う希ガスとは、ヘリウムガス、ネオンガス、アルゴンガス、クリプトンガス、キセノンガス、およびラドンガスのことを意味する。このように構成することでも、電極１１、２１が雰囲気により酸化などの影響を受けるのを抑制し、電極１１、２１同士の接続信頼性を確保することができる。
壁部１２、１７、２７は第一の電極１１と同一の金属で形成されているとしたが、壁部１２、１７、２７は樹脂などで形成されていてもよい。
また、複数の第一の電極１１を囲うように壁部１２を形成したが、壁部１２が囲う第一の電極１１の数に制限は無く、１つ以上であればいくつでもよい。壁部１７、２７についても同様である。
１、２、３ 半導体装置（積層型半導体装置）
１０ 第一の基板
１０ａ 一方の面
１１ 第一の電極
１２、４２ 壁部
１７ 第一の壁部
２０ 第二の基板
２０ａ 第一の面
２１ 第二の電極
２７ 第二の壁部
３０ エポキシ樹脂（封止部材）
Ｘ 厚さ方向

Claims (1)

  1. 一方の面に複数の第一の電極、およびそれぞれの前記第一の電極を囲うように立設した複数の第一の壁部が設けられた第一の基板と、第一の面に複数の第二の電極、およびそれぞれの前記第二の電極を囲うように立設した複数の第二の壁部が設けられた第二の基板とを、前記一方の面と前記第一の面とを対向させ、それぞれの前記第一の電極と前記第二の電極とを接続させるとともに、それぞれの前記第一の壁部のうち前記第一の壁部が立設する先端部とそれぞれの前記第二の壁部のうち前記第二の壁部が立設する先端部とを前記第一の壁部の全周にわたり接続することで互いに接続する接続工程と、
    前記第一の基板と前記第二の基板との間であってそれぞれの前記第一の壁部および前記第二の壁部の外側に封止部材を充填する封止工程と、
    前記第一の基板、前記第二の基板、および前記封止部材を、前記第一の基板の厚さ方向に見たときの隣り合う前記第一の壁部の中間部で切断する切断工程と、
    を備えることを特徴とする積層型半導体装置の製造方法。
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