JPWO2013141091A1 - 積層型半導体装置およびその製造方法 - Google Patents
積層型半導体装置およびその製造方法 Download PDFInfo
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- JPWO2013141091A1 JPWO2013141091A1 JP2014506159A JP2014506159A JPWO2013141091A1 JP WO2013141091 A1 JPWO2013141091 A1 JP WO2013141091A1 JP 2014506159 A JP2014506159 A JP 2014506159A JP 2014506159 A JP2014506159 A JP 2014506159A JP WO2013141091 A1 JPWO2013141091 A1 JP WO2013141091A1
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Abstract
Description
さて、TSV積層を以下の3つの方法に分類する。
(1)Chip−to−Chip(C2C):KGD(Known−Good−Die)同士を積層する簡便な手法である。
(2)Chip−to−Wafer(C2W):ウェハ上にKGDを搭載するもので(1)と類似の系といえる。
(3)Wafer−to−Wafer(W2W):高歩留まりウェハを前提とし、ウェハ同士を直接貼り合わせる方式であり最終的な積層形態といえる。
2枚のウェハ151、152には、接続電極(電極)153が形成された電極領域154が設けられている。電極領域154の周囲は、ウェハ151、152以外には何も設けられないブランク領域となっている。電極領域154には、ウェハ151、152上にそれぞれ接続電極153が形成されており、ウェハ151、152上に形成された接続電極153同士を接合することによりウェハ151、152間での電気的接合を図っている。なお、接続電極153の中には、電気的導通には寄与せず、接合の強度を保つためのダミーも含まれている場合がある。
W2W方式においては、ウェハ151、152同士の対応する接続電極153同士が接するようにウェハ151、152を重ね合わせて接合する。
具体的には、ウェハ151、152の接続電極153が互いに接する様にして加圧板155、156の間に挟み、図示しないプレス装置によって、上下から加圧板155、156を加圧する。ウェハ151、152の接合には、接続電極153を加熱し、加圧して接合する加熱加圧接合が一般的に使用される。
なお、ウェハ151、152を接合することで、複数の積層型半導体装置が形成される。
なお、外周接続部157の領域を大きくすることによって接続電極153に与える衝撃を緩和する手段も考えられるが、その場合には接続しなければならない電極部が増加することによってウェハ全面で接続電極153を接合することが困難となる。
本発明の積層型半導体装置は、一方の面に第一の電極、および前記第一の電極を囲うように立設した第一の壁部が設けられた第一の基板と、第一の面に第二の電極、および前記第二の電極を囲うように立設した第二の壁部が設けられた第二の基板と、を備え、前記第一の基板と前記第二の基板とは、前記一方の面と前記第一の面とを対向させ、前記第一の電極と前記第二の電極とを接続させるとともに、前記第一の壁部のうち前記第一の壁部が立設する先端部と前記第二の壁部のうち前記第二の壁部が立設する先端部とを前記第一の壁部の全周にわたり接続した状態に配置され、前記第一の基板と前記第二の基板との間であって前記第一の壁部および前記第二の壁部の外側には、前記第一の壁部の全周にわたり封止部材が充填されていることを特徴としている。
また、上記の積層型半導体装置において、前記封止部材は、エポキシ樹脂であることがより好ましい。
以下、本発明に係る積層型半導体装置(以下、「半導体装置」と略称する。)の第1実施形態を、図1から図6を参照しながら説明する。
図1および図2に示すように、本半導体装置1は、一方の面10aに複数の第一の電極11、およびこれら複数の第一の電極11を囲うように立設した壁部12が設けられた第一の基板10と、第一の面20aに複数の第二の電極21が設けられた第二の基板20とを備えている。
なお、後述する素子14、24、および配線15、25は、説明の便宜上、図1および後述する図7のみに示している。
複数の第一の電極11は、一方の面10aにおいて格子状に配置され、複数の第一の電極11が全体として第一の電極領域R11を構成している。厚さ方向Xに見た平面視において、例えば、それぞれの第一の電極11は直径が数μm程度に形成され、第一の電極領域R11は数mm角程度に形成されている。
壁部12は、厚さ方向Xに見て、第一の電極領域R11の外形を外側に拡大するとともに、第一の基板10を内側に縮小した矩形状(矩形の輪郭状)に形成されている。壁部12が一方の面10aから立設する立設方向は、厚さ方向Xの一方側X1となる。厚さ方向Xの長さは、第一の電極11および第二の電極21の和と、壁部12とがほぼ等しくなるように設定されている。
この例では、壁部12は、第一の電極11と同一の金属、例えば銅や金などで形成されている。
複数の第二の電極21は、第一の面20aにおいて、複数の第一の電極11と同様の格子状に配置され、複数の第二の電極21が全体として第二の電極領域R12を構成している。
この例では、内部空間R20は真空となるように減圧されている。ここで言う真空とは、大気圧よりも低い圧力のことを意味し、絶対圧力で、0Pa以上1Pa以下であることが好ましい。これにより、電極11、21の周囲は、真空雰囲気となっている。
半導体装置1は、配線15、25、および電極11、21を介して電気的に接続された素子14、24が、互いに信号を送受信しながら所定の処理を行うように構成されている。
本製造方法は、第一の基板10と第二の基板20とを接続する接続工程と、第一の基板10と第二の基板20との間にエポキシ樹脂30を充填する封止工程と、基板10、20を切断する切断工程とを備えている。
このように、略円形となる基板10、20において、個片領域Tは略格子状に複数配置されている。
同様に、第二の基板20の個片領域Tごとに、素子24および配線25を形成するとともに、第二の基板20の第一の面20aにそれぞれの配線25に接続された第二の電極21を設け、第二の電極領域R12を構成しておく。
具体的には、図示はしないが、公知の加圧装置の一対の加圧板の間に基板10、20を配置し、互いに接触させた第一の電極11と第二の電極21、壁部12と第二の基板20を不図示の加熱装置によりそれぞれ加熱した状態で一対の加圧板により基板10、20を厚さ方向Xに押圧することで、第一の電極11と第二の電極21、壁部12と第二の基板20をそれぞれ接合する。
この後で、加熱したエポキシ樹脂30を冷却して、固化させる。
第一の基板10と第二の基板20との間はエポキシ樹脂30が充填されているため、基板10、20を切断するときに作用する荷重をエポキシ樹脂30で支持することができ、第一の電極11と第二の電極21との接合部、壁部12と第二の基板20との接合部に過大な荷重(衝撃)が作用するのが防止される。
スクライブラインSで切断することで個片化され、半導体装置1が得られる。
これまで説明した接続工程から切断工程までの工程により、半導体装置1が製造される。
第一の基板10と第二の基板20との間であって壁部12の外側にはエポキシ樹脂30が充填されているため、基板10、20を切断するときに作用する荷重をエポキシ樹脂30が支持する。したがって、基板10、20を個片化して半導体装置1を製造する際に、壁部12と第二の基板20との接続部に過大な荷重が作用するのが防止され、電極11、21同士の接続を確保することができる。
加熱して流動性を高めたときのエポキシ樹脂30の粘度は、他の樹脂の粘度に比べて比較的低いため、第一の基板10と第二の基板20との間に容易にエポキシ樹脂30を充填させることができる。
次に、本発明の第2実施形態について図7から図9を参照しながら説明するが、前記実施形態と同一の部位には同一の符号を付してその説明は省略し、異なる点についてのみ説明する。
第1実施形態の半導体装置1は、壁部を第一の基板10の一方の面10aのみに形成したが、図7に示す本実施形態の半導体装置2は、この壁部を第一の基板10の一方の面10aおよび第二の基板20の第一の面20aのそれぞれに形成したものとなっている。すなわち、本半導体装置2は、半導体装置1の壁部12に代えて、第一の基板10の一方の面10aに複数の第一の電極11を囲うように立設した第一の壁部17が設けられるとともに、第二の基板20の第一の面20aに複数の第二の電極21を囲うように立設した第二の壁部27が設けられている。
同様に、第二の壁部27の厚さは各第二の電極21の厚さに等しい。第一の壁部17と第二の壁部27とは、厚さ方向Xに見たときに重なるように(同一の形状に)形成されている。
この例では、前述のエポキシ樹脂30は、第一の基板10と第二の基板20との間であって第一の壁部17および第二の壁部27の外側に、第一の壁部17の全周にわたり充填されている。
本実施形態の製造方法も、第1実施形態の製造方法と同様に接続工程、封止工程および切断工程を備えている。
同様に、第二の基板20の個片領域Tごとに、複数の第二の電極21からなる第二の電極領域R12、および第二の電極領域R12を囲うように第二の壁部27を形成する。
続いて、切断工程において、第一の基板10、第二の基板20、およびエポキシ樹脂30を、図9に示すスクライブラインSで切断する。このスクライブラインSは、厚さ方向Xに見たときの隣り合う第一の壁部17の中間部に設定される。
これまで説明した接続工程から切断工程までの工程により、半導体装置2が製造される。
本実施形態では、第一の壁部17の厚さが各第一の電極11の厚さに等しくなく、かつ、第二の壁部27の厚さが各第二の電極21の厚さに等しくないように構成してもよい。第一の壁部17の厚さと第二の壁部27の厚さとの和と、第一の電極11の厚さと第二の電極21の厚さとの和がほぼ等しければ、第一の基板10と第二の基板20とを良好に接続できるからである。
たとえば、前記第1実施形態および第2実施形態では、封止部材としてエポキシ樹脂を用いたが、封止部材はこれに限定されず、他にも熱可塑性樹脂や熱硬化性樹脂、有機材料などを適宜選択して用いることができる。ただし、封止部材は、加熱して流動性を有したときに粘度が低くなるものが好ましい。第一の基板10と第二の基板20との間に、隙間なく封止部材を充填できるからである。
複数の第一の電極11により構成される第一の電極領域R11の形状も、円形や楕円形に形成されていてもよいし、多角形状に形成されていてもよい。第二の電極領域R12についても同様である。
壁部12、17、27は第一の電極11と同一の金属で形成されているとしたが、壁部12、17、27は樹脂などで形成されていてもよい。
また、複数の第一の電極11を囲うように壁部12を形成したが、壁部12が囲う第一の電極11の数に制限は無く、1つ以上であればいくつでもよい。壁部17、27についても同様である。
10 第一の基板
10a 一方の面
11 第一の電極
12、42 壁部
17 第一の壁部
20 第二の基板
20a 第一の面
21 第二の電極
27 第二の壁部
30 エポキシ樹脂(封止部材)
X 厚さ方向
Claims (5)
- 一方の面に第一の電極、および前記第一の電極を囲うように立設した第一の壁部が設けられた第一の基板と、
第一の面に第二の電極、および前記第二の電極を囲うように立設した第二の壁部が設けられた第二の基板と、
を備え、
前記第一の基板と前記第二の基板とは、前記一方の面と前記第一の面とを対向させ、前記第一の電極と前記第二の電極とを接続させるとともに、前記第一の壁部のうち前記第一の壁部が立設する先端部と前記第二の壁部のうち前記第二の壁部が立設する先端部とを前記第一の壁部の全周にわたり接続した状態に配置され、
前記第一の基板と前記第二の基板との間であって前記第一の壁部および前記第二の壁部の外側には、前記第一の壁部の全周にわたり封止部材が充填されていることを特徴とする積層型半導体装置。 - 前記第一の基板と前記第二の基板との間であって前記第一の壁部および前記第二の壁部の内側は、窒素ガスまたは希ガスが充填されているか、真空となるように減圧されていることを特徴とする請求項1に記載の積層型半導体装置。
- 前記封止部材は、エポキシ樹脂であることを特徴とする請求項1に記載の積層型半導体装置。
- 一方の面に第一の電極、および前記第一の電極を囲うように立設した壁部が設けられた第一の基板と、
第一の面に第二の電極が設けられた第二の基板と、
を備え、
前記第一の基板と前記第二の基板とは、前記一方の面と前記第一の面とを対向させ、前記第一の電極と前記第二の電極とを接続させるとともに、前記壁部のうち前記壁部が立設する先端部を前記第一の面に全周にわたり接続した状態に配置され、
前記第一の基板と前記第二の基板との間であって前記壁部の外側には、前記壁部の全周にわたり封止部材が充填されていることを特徴とする積層型半導体装置。 - 一方の面に複数の第一の電極、およびそれぞれの前記第一の電極を囲うように立設した複数の第一の壁部が設けられた第一の基板と、第一の面に複数の第二の電極、およびそれぞれの前記第二の電極を囲うように立設した複数の第二の壁部が設けられた第二の基板とを、前記一方の面と前記第一の面とを対向させ、それぞれの前記第一の電極と前記第二の電極とを接続させるとともに、それぞれの前記第一の壁部のうち前記第一の壁部が立設する先端部とそれぞれの前記第二の壁部のうち前記第二の壁部が立設する先端部とを前記第一の壁部の全周にわたり接続することで互いに接続する接続工程と、
前記第一の基板と前記第二の基板との間であってそれぞれの前記第一の壁部および前記第二の壁部の外側に封止部材を充填する封止工程と、
前記第一の基板、前記第二の基板、および前記封止部材を、前記第一の基板の厚さ方向に見たときの隣り合う前記第一の壁部の中間部で切断する切断工程と、
を備えることを特徴とする積層型半導体装置の製造方法。
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JP2007512707A (ja) * | 2003-11-26 | 2007-05-17 | アバゴ・テクノロジーズ・ジェネラル・アイピー(シンガポール)プライベート・リミテッド | 基板間においてプレスされるコンプライアント素子を有するデバイス |
JP2006186091A (ja) * | 2004-12-27 | 2006-07-13 | Mitsubishi Heavy Ind Ltd | 半導体装置及びその製造方法 |
JP2011114054A (ja) * | 2009-11-25 | 2011-06-09 | Dainippon Printing Co Ltd | センサーユニットおよびその製造方法 |
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