CN100431142C - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN100431142C
CN100431142C CNB021593884A CN02159388A CN100431142C CN 100431142 C CN100431142 C CN 100431142C CN B021593884 A CNB021593884 A CN B021593884A CN 02159388 A CN02159388 A CN 02159388A CN 100431142 C CN100431142 C CN 100431142C
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chip
substrate
projection
circuit board
mentioned
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CN1430272A (zh
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梶原良一
小泉正博
筱田政佳
成泽明彦
西村朝雄
守田俊章
高桥和弥
伊藤和利
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Hitachi Ltd
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Hitachi Ltd
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Abstract

对于在有机基板上直接搭载具有小于100微米间距大于50管脚的电极的LSI芯片的半导体装置，提供半导体装置的耐焊锡回流性、温度循环可靠性、高温高湿可靠性好的安装结构及制造方法。构成为通过Au/Au金属接合直接倒装片接合芯片的电极Au凸起和基板连接端子最表面的Au膜，并接合构成为Au凸起的接合部延伸大于2微米。得到该接合结构的方法为从溅射清洁开始在10分钟内超声波接合两接合面的工序，选择接合条件为基板侧：常温，芯片侧：常温-150度，接合负荷：1/2S*100MPa-S*180MPa(S：凸起/芯片间的接触面积)，负荷模式：接合中增加，超声波时间：50-500ms，可实现上述结构。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种通过贵金属凸起面朝下地在布线基板上安装Si芯片的半导体装置和安装方法，尤其是涉及可降低安装时的芯片损伤、大大改善连接部的耐热性、温度循环寿命和高温高湿及高温保持可靠性的芯片/基板间的接合结构及接合端子的金属化结构和金属接合方法。
背景技术
在现有的使用Au凸起的半导体芯片的倒装片安装法中，有1)Au/Au直接接合、2)通过绝缘树脂的芯片粘接，Au/Au接触连接、3)通过各向异性导电性树脂的芯片粘接，Au/Ag粒子/Au接触连接、4)Au/Sn的熔化接合。2)、3)的树脂粘接的接触连接方式在曝露于高湿度环境后的各种可靠性试验中恶化显著，缺乏可靠性，4)的使用低熔点金属的熔化接合方式中，在接合界面上形成脆的金属间化合物，在接合后的冷却工序和温度循环试验时，存在容易发生裂纹、强度可靠性低的问题。在现状下，可靠性最好的安装法是Au/Au直接接合方式。
作为Au/Au接合方式的背景技术，在特开平10-107078号或电子通信学会技术报告书(1995年7月)中作为现有技术公开了在布线基板的Au垫上增加超声波并面朝下地金属接合搭载形成Au凸起的表面波装置。在这些现有技术中，为了使Au凸起/Au垫间确实金属接合，设Au垫的膜厚大于0.5微米，作为适当的接合条件，设接合负荷为75gf/bump-300gf/bump，接合温度为150-250度，超声波施加时间为500-800ms。作为在该条件下的Au凸起接合部的剪断强度，得到40gf/bump-100gf/bump。因为表面波装置的电介质基板是复合氧化物系列的电介质材料，所以强度非常强，在接合负荷为300gf/bump以前，没有接合产生的损伤。作为接合条件下限值的接合负荷75gf/bump、接合温度150、超声波施加时间300ms是若下降到其上则在接合强度下降的同时，接合变得不稳定，产生未接合品或未接合凸起，导致合格率下降或连接可靠性降低，制品的组装困难的条件。另外，仅就陶瓷基板描述布线基板。
另一方面，特开平10-275826号中作为现有技术公开了在包含有机材料的布线基板上面朝下地经金属接合搭载形成Au凸起的半导体芯片的安装方法。在现有技术中，通过在接合前，在真空中，照射离子或原子来清洁布线基板上覆盖硬质金属：Ni(3-5微米)/Au(0.03-0.05微米)的接合垫部，在形成凸起后，在非氧化性气氛中保管芯片，保持清洁，进行彼此接合。接合是将这些布线基板和芯片在大气中加热和加压后保持规定时间，在硬质金属与Au凸起之间形成合金后进行金属接合。此时的适当接合条件为接合温度在芯片侧为150-300度，在基板侧为60-120度，接合负荷为20gf/bump-30gf/bump，接合时间为10-150秒。作为在照射离子或原子并清洁后的垫表面上仅剩余Au的程度，通过在上述条件下进行接合，在硬质金属Ni与Au凸起之间形成合金，在对接合部进行破坏试验的情况下，在挖去部分Ni层后附着在凸起电极前端的状态下，越是断裂，越可牢固接合。若提供超声波，则可实现接合温度的低温化和接合时间的短时间化，但未详细公开。
我们在开发搭载微型计算机、图像处理装置或存储器等最新的LSI芯片的高速、高功能的多芯片模块的同时，研究评价了现有的Au/Au接合方式。模块基板中，为了符号LSI芯片的电极间距，最小布线间距必须为90-40微米的间距。一般的印刷布线基板通过贴上Cu箔后进行蚀刻并布图的方法来制造，但在细微间距化方面，100微米间距的程度为界限。可对应于在此以上的细微间距的布线基板中，在芯板上形成薄的绝缘层后，通过电镀方法形成图案的依次层叠方式的组合基板在生产性和可靠性及成本方面最有力。但是，该组合基板的依次层叠形成的有机绝缘层的玻璃转变温度为较低温度(100-150度)，弹性率低，电镀处理限定于无电解电镀，所以形成厚的电镀膜在成本上困难，由于形状、尺寸的制约，细微布线的刚性低，所以存在现有的Au/Au金属接合的倒装片安装困难的问题。具体研究实例如下所示。
经上述超声波接合技术，通过Au/Au接合将最新的LSI芯片倒装片安装在上述组合基板上。结果，在接合负荷为75gf/bump、接合温度为150-250度、接合时间为300ms的条件下，在形成Au凸起的芯片的Al电极下绝缘层中产生微小的裂纹，判断芯片损伤是该安装法的大问题。另外，加热组合基板时，细微布线因为施加在细微布线部上的接合负荷和超声波振动而变形大，电镀形成在表面的Ni层中产生裂纹，判断产生布线剥离。为了避免这些问题，若降低接合负荷，则得不到充分的接合，在大于50管脚的LSI芯片中，基于接合故障而产生初始导通故障，判断难以实现100％接合率。另外，在接合温度为150度时，由于有机基板的热膨胀率17ppm与LSI芯片的热膨胀率3ppm的差，在10mm的芯片中，最大产生约20微米的初始错位，在超声波接合时的Au凸起变形工序中，该错位扩大，判断容易产生与相邻端子短路的故障。另外，在芯片接合成粗的图案的情况下，虽然不产生错位和短路故障，但在接合后的冷却工序中，在芯片/基板间产生大的热变形，芯片上的Al膜厚薄，基础弱，判断在LSI中产生芯片损伤(基础绝缘层的裂纹)。
另一方面，在清洁基板表面并热压的现有的上述Au/Au接合法中，在Ni(5微米)/Au(0.05微米)规格的组合基板上倒装片安装最新的LSI芯片，在芯片温度为150度/基板温度为60度、接合时间为10-150s、接合负荷为20-30gf/bump的条件下，由大气中的热压接合来实现充分的金属接合。通过将接合样品在NaOH水溶液中腐蚀Al电极去除芯片，检查Au凸起向基板侧的转录率的方法来评价接合状态，判断有无金属接合。检查得到Au凸起转录率100％的接合条件的结果，在芯片温度为300度/基板温度为120度的接合温度、接合负荷为20-30gf/bump、接合时间大于150s的条件下确认转录率100％。但是，因为在上述任一条件下接合时间都长至10-150s，所以判断组合基板的温度上升，依次层叠的绝缘层的弹性率下降，由该现象可知在基底中芯板具有Cu图案布线的区域的细微布线部和无Cu图案布线的区域的细微布线部的变形大小不同。因此，判断Au凸起的变形率产生差异，变形率大的凸起得到充分的金属接合，而变形率小的Au凸起接合不充分。这是在由玻璃转变温度和弹性率高的材料构成的现有印刷布线板中未产生的问题。若接合温度上升，则接合水平整体提高，所以即使在变形率小的Au凸起中也实现金属接合，但由于伴随基板热膨胀的凸起/细微布线间的错位增大及细微布线部变形大并导致错位增加这两个原因，难以安装不足100微米的细微间距LSI。另外，在生产率方面，也存在接合时间长导致制造成本上升的问题。
另外，制作由现有的Au/Au接合法将模拟LSI的TEG芯片倒装片安装在各种布线基板上，在基板/芯片之间填充热膨胀率约为30ppm的无机绝缘填料树脂的安装样品，进行-50/150度的温度循环试验后进行评价，在Au凸起向基板侧的转录率为100％条件的样品中，Au凸起的变形大，芯片/基板间的间隙小，在芯片的Al电极与Au凸起间产生裂纹，判断1000循环水平下产生断路。在抑制Au凸起变形的条件的样品中，Au凸起的转录率不是100％，初期确认导通，但在数百循环的试验中，判断Au凸起与Au连接端子的接合界面开口，在短时间内达到断路。
发明内容
本发明的目的在于提供一种半导体的制造方法，按照本发明的一种半导体装置的制造方法，具有：在布线基板的Au电镀连接端子和芯片上形成的Au凸起的倒装片连接中，通过平行平板电极间产生的减压下的Ar放电气体物理溅射蚀刻布线基板的Au连接端子表面大于Au膜厚的1/10或大于10nm、小于Au膜厚的1/2的厚度的工序；与基板侧一样溅射蚀刻芯片上的Au凸起表面数-数十nm的厚度的工序；使基板与芯片面对并对位的工序；将芯片侧加热到室温至150度范围的温度：Tc、将基板侧加热到室温-低于基板的玻璃转变温度Tg的温度Tb的工序；通过包含在超声波加振中增加施加在芯片上的负荷的工序的超声波接合方法来进行Au/Au的金属接合的工序；在基板与芯片之间填充树脂的工序；加热硬化填充的树脂的工序；和在基板的外部连接端子中形成焊锡凸起的工序，其特征在于：上述布线基板上的芯片连接用端子下的至少一部分的构成部件由具有小于150度的玻璃转变温度的有机材料构成，芯片连接用端子的最小间距为小于100微米的间距。
因此，在具有最小布线间距小于100微米的细微布线层且具有低的玻璃转变温度的表面绝缘层的有机布线板中，在最小电极间距小于100微米具有多于50管脚的电极垫的LSI芯片中，不产生基板/芯片间的错位，并不产生芯片损伤，经Au/Au金属接合来可靠倒装片连接所有管脚。
本发明的另一目的在于提供一种安装结构和安装工序，可将多管脚、细微间距的LSI芯片搭载在高可靠性低阻抗特性并具有细微布线层的有机布线基板上，提高组装合格率，生产性好。
本发明的再一目的在于提供一种半导体装置，具备：至少一部分由有机材料构成的多层布线基板；形成电路的半导体芯片；和埋置在上述半导体芯片与上述多层布线基板之间的有机树脂，其特征在于：上述多层布线基板上的芯片连接用端子下的至少一部分的构成部件由具有小于150度的玻璃转变温度的有机材料构成，芯片连接用端子的最小间距为小于100微米的间距，芯片连接用端子的表面金属由Ni-P/Au或Ni-P/Pd/Au的电镀层构成，并且Au或Pd/Au的贵金属部的总厚度为0.005-0.3微米，在半导体芯片的电极端子上形成Au凸起，通过金属接合连接基板上的上述Au连接端子和芯片的上述Au凸起。
本发明还提供一种半导体装置，包含：组合基板，在具有通孔和双面布线图案的有机布线基板的两个面上形成由有机绝缘层、Cu电镀布线和辅助孔构成的1-4层组合层，在与半导体芯片连接的端子面上实施Au厚度为0.005-0.3微米的无电解Ni/Au或无电解Ni/Pd/Au电镀；和半导体芯片，在具有多于50个管脚的裸芯片的连接电极或设置在芯片表面上的再布线层上的连接电极上形成Au凸起，其特征在于：上述布线基板上的芯片连接用端子下的至少一部分的构成部件由具有小于150度的玻璃转变温度的有机材料构成，芯片连接用端子的最小间距为小于100微米的间距，通过Au/Au的金属接合来倒装片连接Au凸起与Au电镀面，在基板与芯片之间的间隙中填充包含无机绝缘填料的树脂，在组合基板里面的外部连接端子上，经回流形成焊锡凸起。
本发明还提供一种半导体装置，具备：至少一部分由有机材料构成的多层布线基板；形成电路的半导体芯片；和埋置在芯片与基板之间的有机树脂，其特征在于：上述多层布线基板上的芯片连接用端子下的至少一部分的构成部件由具有小于150度的玻璃转变温度的有机材料构成，芯片连接用端子的最小间距为小于100微米的间距，由Au电镀层构成上述多层布线基板上的芯片连接端子的最表面金属，在上述半导体芯片的电极端子面上形成贵金属柱形凸起，通过金属接合连接上述芯片连接端子上的Au电镀层和上述贵金属凸起，芯片电极/凸起间的紧贴面积Sc与凸起/基板侧连接端子间的紧贴面积Sk之比Sk/Sc小于1/2。
本发明还提供一种半导体装置，通过贵金属彼此的固态金属接合的倒装片连接将半导体芯片安装在布线基板上，其特征在于：上述布线基板上的芯片连接用端子下的至少一部分的构成部件由具有小于150度的玻璃转变温度的有机材料构成，芯片连接用端子的最小间距为小于100微米的间距，布线基板上的半导体芯片连接端子的表面金属由Ni/Au或Ni/Pd/Au的电镀层构成，并且Au或Pd/Au的贵金属部的总厚度为0.005-0.3微米，半导体芯片由Si基板上的电路形成区域和电极垫区域构成，在其表面上夹杂厚度大于2微米的有机绝缘层来形成再布线层，与电极垫电连接的再布线层的连接垫由总厚度大于2微米的Cu/势垒金属/Au的多层金属结构构成，在该连接垫上形成Au凸起，通过Au/Au的金属接合倒装片连接Au凸起与Au电镀面，并用包含无机绝缘填料的树脂填充基板与芯片间的间隙，在布线基板里面的外部连接端子上，由回流形成焊锡凸起。
本发明还提供一种半导体装置，通过贵金属彼此的固态金属接合的倒装片连接将半导体芯片安装在布线基板上，其特征在于：上述布线基板上的芯片连接用端子下的至少一部分的构成部件由具有小于150度的玻璃转变温度的有机材料构成，芯片连接用端子的最小间距为小于100微米的间距，布线基板上的芯片连接端子的表面金属由Ni/Au或Ni/Pd/Au的电镀层构成，并且Au或Pd/Au的贵金属部的总厚度为0.005-0.3微米，半导体芯片由Si基板上的Cu布线的电路形成区域和Cu电极垫区域构成，经势垒层在Cu电极垫最表面实施Au或Al金属化处理，并在其上形成Au柱形凸起或Au电镀凸起，由Au/Au金属接合倒装片连接Au凸起和Au电镀面，并用包含无机绝缘填料的树脂填充基板与芯片间的间隙，在布线基板里面的外部连接端子上形成焊锡凸起。
因此，通过倒装片连接将具有多于50管脚的电极垫的多管脚LSI芯片搭载在在表面层中具有由细微布线层和低玻璃转变温度的有机绝缘层构成的组合层的有机布线基板上，倒装片芯片连接部的耐热性、电特性、高温高湿及温度循环可靠性好。
在本发明中，为了实现上述第一目的，在LSI芯片的电极上形成Au凸起，底座部的直径或矩形的一边大小为电极尺寸的60-100％或最小电极间距的50-90％、高度为5-40微米，在其上部为小于底座部直径的70％，前端部更小，从底面到前端的整体高度大于30微米。另一方面，在具有细微布线层的有机布线基板侧的Cu布线的连接端子最表面形成Au电镀膜。在倒装片接合两者之前，在大气压或0.1-数Pa的减压Ar气氛下，经Ar离子溅射物理蚀刻Au凸起表面，使膜厚大于5nm，经Ar离子溅射物理蚀刻连接端了侧的Au电镀表面至大于5nm或Au膜厚的1/10-1/2左右。在减压下物理蚀刻两者的情况下，在氮气或去除水分的干空气中升压，并将其分别取出到大气中。将有机布线基板搭载在接合装置的台上，使LSI芯片反转吸附在超声波接合头的接合工具面上，使两者对位后，下降接合头，使之重合。此时，将台或接合工具保持在规定温度，在对位工序中使有机布线基板和LSI芯片温度达到规定温度。重合后，从芯片里面施加压力和超声波振动，金属接合Au凸起和Au电镀膜。此时的接合条件中，从1/2S1(m2)*120(Mpa)≤P(N)≤S1(m2)*180(Mpa)(公式1)的范围内选择每1bump增加的负荷P(其中，S1：Au凸起/电极间的接触面积)。在比该条件高的负荷下，因为在Au凸起/芯片电极的接触部中伴随Au凸起的变形产生芯片损伤，所以在低负荷下，接合面积相比凸起尺寸明显变小，在芯片/基板间产生热变形的情况下，凸起主体不变形，变形集中在接合界面上，知路的概率增大。
作为其它接合条件，设接合气氛的温度小于60度，接合温度在搭载基板的台侧为室温-60度，在接合头侧为室温-150度的范围，设接合时间为50-500ms的范围，设振动振幅为芯片的振幅，在50kHz的情况下为0.3-2.0微米，因此，工具振幅在接合工具/芯片间的振动传递效率为1/2的情况下为0.6-4.0微米的范围，组合工件选择适当条件。另外，施加负荷方法为在施加超声波中从低负荷向高负荷上升的方式，从表面清洁化到接合的接合工件曝露在大气中的时间小于10分钟。通过设定该接合条件范围，仅在前端部分附近残留Au凸起变形，不产生基板/芯片间的错位，且不对芯片产生损伤，确认可达到全部管脚的Au/Au金属接合。其研究结果一例如图12和图13所示。图12表示Ar溅射有机基板侧和芯片侧两个面，使Au厚度为20nm左右，在工具振幅为3微米下超声波接合情况下的接合部截面与拉长断面的扫描型电子显微镜像。接合负荷小，将基板侧的接合面积与芯片侧的接合面积相比小于1/5左右，确认在拉长断截面中部分凸起附着在基板侧，可知实现金属接合。这里，所谓金属接合的定义是指在接合界面处因位力而断裂的情况下，在Au/Au接合部实现伴随局部延伸呈现延展性断裂的接合，确认在凸起侧与电镀膜侧的断截面中观察到Au突起。图13表示凸起尺寸为50微米ф时将电极间距为80微米的芯片接合在组合基板上的截面照片。因为基板侧的接合温度为室温，所以无热变形，从低倍的截面像可知Au凸起高精度地接合在连接端子的其中中央处。另外，从中高倍率的像可知，Au凸起的组织仅在基板侧变扁平并金属接合的状况。虽然在该条件的接合样品中检查芯片损伤，但没有发生损伤。根据这些研究结果确认可提供一种半导体的制造方法，即使最小电极间距小于100微米并具有大于50管脚的电极垫的LSI芯片中也不产生基板/芯片间的错位，并不产生芯片损伤，经Au/Au的金属接合来确实倒装片连接全部管脚。
接着，为了实现第二目的，在LSI芯片上形成上述Au凸起，在基板侧形成上述Au电镀膜。作为接合前的溅射表面清洁方法，有局部同时进行真空排气工序和Ar气体导入工序的工序，组合必要个数并依次进行将多个LSI芯片载在托盘上一起溅射的工序和一起溅射多个基板的工序的工序。另外，选择设接合温度中搭载基板的台侧为室温，仅升温吸附芯片的接合头侧，施加超声波和负荷进行接合的方式。首先，在溅射工序中，在部分时间中重叠真空排气和Ar气体导入，缩短将A r气压控制到规定气压的时间，可迅速开始放电，通过托盘承载芯片，可同时搬运清洁多个芯片，将基板与芯片分开后进行清洁的方式下，通过最佳化各清洁条件和设定各必要个数可定时清洁，大幅度缩短工件清洁所需的时间。另外，通过增加清洁基板与芯片两者接合表面的工序的超声波接合，可大幅度改善Au/Au接合性，可在低负荷、低温、短时间内进行接合，因为没有升温时间缩短和热的动摇，所以可缩短对位工序，大幅度缩短倒装片接合工序，提高生产性。另外，由于提高接合性，接合故障大大减少，提高了生产合格率。
下面，为了实现第三目的，将布线基板上形成的有机绝缘层上的Cu细微布线图案形成为从绝缘层上突出的形状，在该Cu布线上的最表面形成Au膜，LSI芯片电极上的Au凸起和Au电镀膜以Au凸起接合部相对拉力拉伸2微米以上的接合水平金属接合，在芯片/基板间的间隙中填充低热膨胀、包含细微无机填料的树脂。这里，图9、图10、图11根据拉断实例来表示Au拉伸2微米以上的条件的定义。根据接合水平，拉断位置除了凸起/Au膜的接合界面附近、凸起内、凸起/Al电极的接合界面附近外，即使任一种情况下，Hb-H0作为Au的延伸。首先，通过Au/Au的金属接合连接的结构，可实现连接部的耐热性与电特性的大幅度提高。接着，通过Au/Au接合水平具有可在接合界面处吸收大于2微米的变形的性能、在芯片/基板间填充无机填料树脂、不向接合部增加大的变形、基板的布线层比基板面、扩大实质的芯片/基板间隙并减小加到接合部上的热变形，可大幅度改善温度循环可靠性，由延展性的某个Au接合部吸收吸湿等引起的芯片/基板间隙的扩大，从而可大幅度提高高温高湿可靠性。
附图说明
图1是本发明半导体装置的截面结构的一实施例。
图2是本发明半导体装置的截面结构的另一实施例。
图3是本发明半导体装置的截面结构的再一实施例。
图4是本发明半导体装置的截面结构的又一实施例。
图5是本发明半导体装置的截面结构的又一实施例。
图6是本发明的LSI芯片与有机布线基板的接合结构的一实施例。
图7是本发明的LSI芯片与有机布线基板的接合结构的另一实施例。
图8是本发明半导体装置的截面结构的又一实施例。
图9是接合部拉伸拉断时的Au延伸的定义和拉断实例。
图10是接合部拉伸拉断时的Au延伸的定义和拉断实例。
图11是接合部拉伸拉断时的Au延伸的定义和拉断实例。
图12是Au凸起接合部的截面形状和拉断状况。
图13是80微米间距LSI芯片与组合基板的接合截面图。
具体实施方式
下面，使用附图来详细说明本发明的实施例。
图1表示本发明半导体装置的截面结构的一实施例。图中，布线基板由芯板12、形成于其两侧上的组合层17、27和芯片连接用端子21构成。芯板12由玻璃环氧树脂绝缘板8、通过蚀刻布图粘接的Cu箔的粗布线层10、11和连接表里布线间的贯通孔9构成，组合层17由涂布形成的薄绝缘层13、在其上通过电镀法形成的细微布线层14和连接粗布线层和细微布线层的辅助孔15构成。组合层中的薄绝缘层在150-180度的温度下硬化焙烤液态树脂，所以Tg温度小于150度，弹性率也低。芯片有连接端子21由Cu电镀形成的细微布线18、其上的Ni电镀膜19、以及还在其上的Au电镀膜20构成。Ni电镀由导入P的无电解电镀形成，膜厚为5-10微米，Au电镀由置换型无电解电镀形成，膜厚为0.03-0.06微米。半导体芯片6具有形成于半导体基板1中央的电路形成区域2的区域和形成于周边的积层绝缘膜3的区域，并具有外部连接用Al电极垫4和覆盖其外区域的保护膜5。在半导体芯片的Al电极垫上，由超声波热压的球形焊接法形成Au凸起。芯片的电极垫数为256管脚，垫间距为80微米，垫尺寸为65微米四方形，垫材料为Al-Cu或Al-Cu-Si，Al膜厚为400-1000nm。Au凸起尺寸为压后的凸起直径为50微米ф，台座高度为10-25微米，头部的直径为30-40微米ф，高度为35-50微米，包含至导线突起部的整体高度为50-70微米。另外，倒装片接合工序中的表面清洁处理通过Ar气体溅射蚀刻芯片侧的Au凸起面至Au膜厚相当于10-20nm，溅射蚀刻基板侧的Au垫面至Au膜厚相当于5-10nm。在表面清洁处理后从取出到大气中到进行接合为止的时间为10min以内，在周围的相对湿度小于60％的气氛下进行接合。作为接合条件，接合负荷模式是在超声波施加中使负荷增加的变动负荷方式，初期负荷在1g/bump-5g/bump的范围内，最终负荷在10g/bump-30g/bump的范围内，压在芯片上的工具前端的振动振幅在1-4微米范围内，超声波施加时间在100ms-500ms的范围内，并从其中选择最佳条件。具体而言，在初期负荷为5g/bump(1.28kg)，最终负荷为20g/bump(5.12kg)，振动振幅为3微米，超声波施加时间为300ms下进行接合。接合温度为芯片侧的工具加热温度为150度，搭载基板的台温度为室温：20度。实际的接合部截面如图B所示。尽管组合基板的Au膜厚非常薄，也认为Au/Au接合界面中几乎无缺陷，实现金属接合。在有机基板的外部连接端于23中，通过Ni电镀膜形成无铅的焊锡凸起28。初期的Au膜溶解在焊锡中，没残留在界面中。
根据本实施例，提供一种高可靠的多芯片模块，在以80微米的布线间距形成的具有低玻璃转变温度的表面绝缘层的有机布线基板上形成细微Au柱形凸起的LSI芯片中，不产生连接部的错位，并且不产生芯片损伤、即Al电极下的绝缘多层膜的裂纹，可由Au/Au金属接合倒装片连接所有256管脚，所以可将最先端的超高速LSI芯片搭载在有机基板上。因为此时不必对LSI芯片进行特殊加工，所以可实现模块制品的低成本，由可在短时间(两个月左右)制造的有机基板构成模块，可在短时间内开发组装符合顾客规格的系统的模块。另外，可在相邻0.1mm左右的状态下将芯片搭载到基板上，实现高密度安装，可使模块小型化。另一方面，因为由延展性的Au/Au金属接合连接作为接合部的结构，其形状为芯片侧大、基板侧小的接合形状，所以即使在芯片/基板间产生变形的情况下，在芯片侧产生高的应力之前，通过基板侧的Au凸起部和接合界面附近的弹性变形来吸收变形，所以不会发生模块组装工序中的芯片损伤和接合部的断路等组装故障，可高合格率地进行模块组装，降低制品成本。
另外，由于可在Au膜厚为0.03-0.06微米、非常薄有连接端子上进行倒装片安装，所以基板的外部连接端子侧的Au膜厚也同样薄，即使由包含很多Sn的焊锡形成焊锡凸起，也不形成AuSn金属间化合物层，实现焊锡连接部的高强度化，提高与母板的连接可靠性。
图2表示本发明半导体装置的截面结构的另一实施例。图中，组合基板在具有通孔布线32和双面布线33、34的芯板35的两侧形成由涂布形成的绝缘层36、37、43、44、电镀形成的细微布线38、45、辅助孔布线40、47、48和最表面的Au膜厚为0.05微米的电镀形成的连接端子39、41、46构成的组合层42、49。在组合基板的单面中，多个LSI芯片51通过由球形焊接法形成于Al电极52上的Au凸起55由Au/Au金属接合连接搭载在基板的连接端子41上。以凸起高度为30微米、布线高度为20微米进行组装。在LSI芯片/基板间，填充对芯片侧的钝化膜53和基板的绝缘层37两者粘接性好的无机填料的未充满树脂56。另外，被动部件57由无铅焊锡58连接搭载在连接端子39上。另一方面，在组合基板的相对侧覆盖部分连接端子46地形成抗蚀刻膜59，在连接端子中形成无铅的焊锡凸起。图3表示图2的半导体装置组装流程的一实施例。从准备LSI芯片形成Au柱形凸起后进行溅射、并溅射组合基板开始，在基板上顺序超声波倒装片接合规定个数的LSI芯片。Au凸起的柱形厚度大于10nm，基板侧的柱形厚度大于Au膜厚的1/10或大于10nm。接合温度在芯片侧为常温-150度，在基板侧为常温-60度。LSI芯片接合后，在芯片/基板间流入未充满树脂，在120度以下进行伪烘烤。接着，在基板的芯片搭载侧的被动部件连接端子上印刷焊锡胶，提供被动部件进行回流。之后，将部分涂布焊剂的焊锡球提供给连接端子，进行回流。最后，洗净焊剂后，通过150度的烘烤完成硬化LSI芯片下的未充满部分，完成组装。
根据本实施例，基于LSI芯片/组合基板的间隙大到50微米进行组装，在其间隙中填充树脂后经加热烘烤进行硬化，经树脂的硬化收缩和从烘烤温度150的冷却，总向接合部施加压缩力，在温度循环试验和高温高湿试验中，在接合部中不产生剥离方向的大的力，另外，微小的剪断方向的变形小，可由Au凸起的弹性变化吸收，所以在接合部周边不发生高的应力的理由，可提高LSI芯片的连接可靠性非常高的半导体装置。另外，因为由基板连接端子的Au膜厚为0.05微米非常薄的膜构成，所以可提高焊锡连接部的可靠性。另外，LSI芯片的微小连接部由低电阻的Au金属且最短距离地连接到基板上，所以连接部的电阻和阻抗分量非常小，电特性好，可减小信号传送延迟，不降低高速系统的性能。另外，因为Au/Au倒装片接合部的耐热性高，所以此后容易进行被动部件和LSI部件的焊锡搭载，可混载超先端的LSI芯片和焊锡接合部件，系统结构的选择范围变宽，设计容易。
图4表示本发明半导体装置的截面结构的又一实施例。细微单面布线基板65的细微连接端子66对Cu图案实施Ni/Au电镀。在LSI芯片60、61的Al电极上形成Au柱形凸起，通过Au/Au的金属接合与基板65的连接端子连接。在基板与LSI芯片之间填充无机填料的低热膨胀树脂，经加热后硬化。将基板65粘接固定在母板68上，在基板与母板之间用Au线70的丝焊进行连接。
根据本实施例，因为在无通孔的单面布线基板中构成模块，所以可由贴有薄Cu箔的基板蚀刻工序来制造，通过降低基板的成本，可稳定模块成本。另外，因为包含至母板搭载都没有焊锡接合部，所以不制约后加部件的焊锡搭载，组装容易，可提高温度循环可靠性和高温高湿可靠性。
图5表示本发明半导体装置的截面结构的又一实施例。图中，在双层布线印刷基板93的单面的一部分上通过粘接剂粘贴具有通孔85的单面带形基板95，通过Au/Au的高负荷条件的热压来接合带形基板的通孔电极85和印刷基板的连接端子90。通过超声波热压来Au/Au接合带形基板的布线连接端子84和形成于LSI芯片80的Al电极81上的Au电镀凸起82。在芯片/带形基板间填充硬化树脂87。在印刷基板里面的外部连接端子91上形成焊锡凸起。
根据本实施例，作为仅在LSI芯片搭载部中形成细微布线区域的结构，因为通过压接在其它工序中制造的细微布线带形基板的方法可制造模块基板，所以可提高基板制造的产量，可低成本化。另外，在由于芯片收缩等变更LSI芯片规格的情况下，仅通过带形基板的最小限度变更就可再制作基板，可缩短规格变更的开发周期。
图6表示本发明的LSI芯片与有机布线基板的接合结构的一实施例。图中，在LSI芯片100的Al电极101上通过球形焊接法形成Au柱形凸起103。柱形凸起由在毛细工具前端面压Au球的厚度为20微米的台部和压入毛细孔中形成的主体部及拉伸断裂AU导线形成的尖塔形前端部构成。形成仅在前端部压碎后Au/Au接合在基板连接端子上的形状。芯片侧的接合部直径为45微米，基板侧的接合部直径为30微米。有机布线基板在芯板115的两个面上形成薄的绝缘层107、108，并在其上形成细微布线层。芯片连接端子的结构是在Cu图案上进行Ni/Au或Ni/Pd/Au的结构，Au厚度或Pd+Au厚度为0.05-0.1微米。
根据本实施例，基板侧的接合面积比芯片侧的接合面积小1/2，凸起高度维持初期柱形凸起主体部的高度并且高，即使在接合后的负荷开放时产生的基板翘曲时，也不会向芯片Al电极周边施加大于Au屈服强度1/2的力，所以不会应力破坏芯片Al电极下的绝缘多层膜。因此，即使基板的平坦精度低，组装合格率也高。该应力的问题在接合中也一样，通过对实施例的凸起形状进行控制，可降低接合时的芯片损伤。
图7表示本发明的LSI芯片与有机布线基板的接合结构的另一实施例。图中，在LSI芯片120的Al电极121上部分覆盖钝化膜122地形成金属化膜123，在其上通过电镀法形成Au凸起。Au凸起在电镀工序后施加热处理，实施软化处理，使维氏硬底Hv小于80。有机布线基板的芯片连接端子137的连接端子前端部的尺寸设计得相对凸起的底面尺寸小，接合后的端子侧接合面积小于凸起底面面积的1/2。具体而言，凸起为40微米四方形*15微米高度，连接端子台部宽30微米，前端部宽20微米，高为20微米。连接端子的结构为在Cu图案上进行Ni-P/Au或Ni-P/Pd/Au的结构，Au厚度或Pd+Au厚度为0.05-0.1微米。
根据本实施例，提供一种可靠性非常高的半导体装置，因为构成为在有机布线基板上通过Au/Au金属接合搭载形成Au电镀凸起的LSI芯片，所以Al电极不曝露在外部，即使曝露在高温高湿气氛的腐蚀环境下也不会受到影响。另外，凸起的底面覆盖在钝化膜上，在凸起中央接触连接端子来配置，所以不会在Al电极周边产生应力集中，不会对芯片产生接合损伤，可提高组装合格率。最担心的是因为Au凸起变形，基板的高度差异或电镀凸起的高度差异不被吸收，产生未接合端子，但通过热处理降低Au凸起硬度及减小连接端子尺寸，容易侵入Au电镀凸起，可通过Au凸起的局部变形来吸收高度差异，避免该问题。
图8表示本发明半导体装置的截面结构的又一实施例。图中，在LSI芯片140的电路形成面中形成由厚度为2-4微米聚酰亚胺绝缘膜142和带垫垒膜的Cu布线143构成的再布线膜，在其上形成最表面为Au膜的电极端子144。在该电极端子中通过球形焊接法形成AU柱形凸起145。有机布线基板为布线间距为200微米的印刷电路基板，对连接端子实施Ni/Au电镀。在基板相对侧的外部连接端子上形成焊锡凸起，另外，在芯片/基板间填充树脂进行固定。
根据本实施例，使用在细微间距的LSI芯片中形成再布线扩大层的芯片，通过Au/Au金属接合连接在有机基板上，所以可在有机布线基板中使用一般的印刷电路基板，可低成本化。另外，因为是通过聚酰亚胺垫传递接合时应力的结构，所以完全不会产生组装工序中的芯片损伤，对位容易，可大幅度提高合格率。另外，因为芯片/基板间的连接部耐热性和可靠性高，所以基本上没有对模块向母板的搭载工序的制约，容易处理，使用方便。
如上所述，根据本发明，提供一种半导体的制造方法，在具有最小布线间距小于100微米的细微布线层且具有低的玻璃转变温度的表面绝缘层的有机布线板中，在最小电极间距小于100微米具有多于50管脚的电极垫的LSI芯片中，不产生基板/芯片间的错位，并不产生芯片损伤，经Au/Au金属接合来确实倒装片连接所有管脚。
另外，提供一种安装结构和安装工序，可将多管脚、细微间距的LSI芯片搭载在高可靠性低阻抗特性并具有细微布线层的有机布线基板上，提高组装合格率，生产性好。
另外，提供一种半导体装置，通过倒装片连接将具有多于50管脚的电极垫的多管脚LSI芯片搭载在在表面层中具有由细微布线层和低玻璃转变温度的有机绝缘层构成的组合层的有机布线基板上，倒装片芯片连接部的耐热性、电特性、高温高湿及温度循环可靠性好。

Claims (13)

1、一种半导体装置，具备：至少一部分由有机材料构成的多层布线基板；形成电路的半导体芯片；和埋置在上述半导体芯片与上述多层布线基板之间的有机树脂，其特征在于：上述多层布线基板上的芯片连接用端子下的至少一部分的构成部件由具有小于150度的玻璃转变温度的有机材料构成，芯片连接用端子的最小间距为小于100微米的间距，芯片连接用端子的表面金属由Ni-P/Au或Ni-P/Pd/Au的电镀层构成，并且Au或Pd/Au的贵金属部的总厚度为0.005-0.3微米，在半导体芯片的电极端子上形成Au凸起，通过金属接合连接基板上的上述Au连接端子和芯片的上述Au凸起。
2、根据权利要求1所述的半导体装置，其特征在于：上述多层布线基板是由如下各部分构成的多层布线基板：单面或双面具有布线图案的印刷布线基板构成的芯板；具有在上述芯板上涂布液态树脂并使之硬化或贴附膜形树脂而形成的有机绝缘层、在上述有机绝缘层上形成比芯板细微的最小布线间距小于100微米的Cu布线的细微布线层、和连接上层细微布线和下层细微布线的辅助孔连接部的多于一层的组合层。
3、根据权利要求1或2所述的半导体装置，其特征在于：由呈现Au延性断裂的金属接合来倒装片连接Au凸起/Au连接端子，在芯片/基板间填充包含无机绝缘填料的树脂，基板的外部连接端子由焊锡凸起构成。
4、根据权利要求2所述的半导体装置，其特征在于：上述芯板上的上述有机绝缘层由玻璃转变温度Tg：150以下的有机树脂构成，细微布线Cu图案的至少一部分由电镀形成。
5、根据权利要求2所述的半导体装置，其特征在于：粘接聚酰亚胺带形基板来形成上述芯板上的上述有机绝缘层和上述细微布线层。
6、一种半导体装置，包含：组合基板，在具有通孔和双面布线图案的有机布线基板的两个面上形成由有机绝缘层、Cu电镀布线和辅助孔构成的1-4层组合层，在与半导体芯片连接的端子面上实施Au厚度为0.005-0.3微米的无电解Ni/Au或无电解Ni/Pd/Au电镀；和半导体芯片，在具有多于50个管脚的裸芯片的连接电极或设置在芯片表面上的再布线层上的连接电极上形成Au凸起，
其特征在于：上述布线基板上的芯片连接用端子下的至少一部分的构成部件由具有小于150度的玻璃转变温度的有机材料构成，芯片连接用端子的最小间距为小于100微米的间距，通过Au/Au的金属接合来倒装片连接Au凸起与Au电镀面，在基板与芯片之间的间隙中填充包含无机绝缘填料的树脂，在组合基板里面的外部连接端子上，经回流形成焊锡凸起。
7、一种半导体装置，具备：至少一部分由有机材料构成的多层布线基板；形成电路的半导体芯片；和埋置在芯片与基板之间的有机树脂，其特征在于：上述多层布线基板上的芯片连接用端子下的至少一部分的构成部件由具有小于150度的玻璃转变温度的有机材料构成，芯片连接用端子的最小间距为小于100微米的间距，由Au电镀层构成上述多层布线基板上的芯片连接端子的最表面金属，在上述半导体芯片的电极端子面上形成贵金属柱形凸起，通过金属接合连接上述芯片连接端子上的Au电镀层和上述贵金属凸起，芯片电极/凸起间的紧贴面积Sc与凸起/基板侧连接端子间的紧贴面积Sk之比Sk/Sc小于1/2。
8、一种半导体装置，通过贵金属彼此的固态金属接合的倒装片连接将半导体芯片安装在布线基板上，其特征在于：上述布线基板上的芯片连接用端子下的至少一部分的构成部件由具有小于150度的玻璃转变温度的有机材料构成，芯片连接用端子的最小间距为小于100微米的间距，布线基板上的半导体芯片连接端子的表面金属由Ni/Au或Ni/Pd/Au的电镀层构成，并且Au或Pd/Au的贵金属部的总厚度为0.005-0.3微米，半导体芯片由Si基板上的电路形成区域和电极垫区域构成，在其表面上夹杂厚度大于2微米的有机绝缘层来形成再布线层，与电极垫电连接的再布线层的连接垫由总厚度大于2微米的Cu/势垒金属/Au的多层金属结构构成，在该连接垫上形成Au凸起，通过Au/Au的金属接合倒装片连接Au凸起与Au电镀面，并用包含无机绝缘填料的树脂填充基板与芯片间的间隙，在布线基板里面的外部连接端子上，由回流形成焊锡凸起。
9、一种半导体装置，通过贵金属彼此的固态金属接合的倒装片连接将半导体芯片安装在布线基板上，其特征在于：上述布线基板上的芯片连接用端子下的至少一部分的构成部件由具有小于150度的玻璃转变温度的有机材料构成，芯片连接用端子的最小间距为小于100微米的间距，布线基板上的芯片连接端子的表面金属由Ni/Au或Ni/Pd/Au的电镀层构成，并且Au或Pd/Au的贵金属部的总厚度为0.005-0.3微米，半导体芯片由Si基板上的Cu布线的电路形成区域和Cu电极垫区域构成，经势垒层在Cu电极垫最表面实施Au或Al金属化处理，并在其上形成Au柱形凸起或Au电镀凸起，由Au/Au金属接合倒装片连接Au凸起和Au电镀面，并用包含无机绝缘填料的树脂填充基板与芯片间的间隙，在布线基板里面的外部连接端子上形成焊锡凸起。
10、一种半导体装置的制造方法，具有：在布线基板的Au电镀连接端子和芯片上形成的Au凸起的倒装片连接中，通过平行平板电极间产生的减压下的Ar放电气体物理溅射蚀刻布线基板的Au连接端子表面大于Au膜厚的1/10或大于10nm、小于Au膜厚的1/2的厚度的工序；与基板侧一样溅射蚀刻芯片上的Au凸起表面数-数十nm的厚度的工序；使基板与芯片面对并对位的工序；将芯片侧加热到室温至150度范围的温度：Tc、将基板侧加热到室温-低于基板的玻璃转变温度Tg的温度Tb的工序；通过包含在超声波加振中增加施加在芯片上的负荷的工序的超声波接合方法来进行Au/Au的金属接合的工序；在基板与芯片之间填充树脂的工序；加热硬化填充的树脂的工序；和在基板的外部连接端子中形成焊锡凸起的工序，
其特征在于：上述布线基板上的芯片连接用端子下的至少一部分的构成部件由具有小于150度的玻璃转变温度的有机材料构成，芯片连接用端子的最小间距为小于100微米的间距。
11、根据权利要求10所述的半导体装置的制造方法，其特征在于：设在溅射蚀刻芯片和布线基板两者后到由超声波倒装片接合之前的大气开放时间为10分钟以内。
12、根据权利要求10所述的半导体装置的制造方法，其特征在于：设超声波接合时的基板温度为室温，设芯片温度为室温到150度。
13、根据权利要求10所述的半导体装置的制造方法，其特征在于：设超声波接合时的基板温度和芯片温度为室温。
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