TW473870B - Integrated low K dielectrics and etch stops - Google Patents
Integrated low K dielectrics and etch stops Download PDFInfo
- Publication number
- TW473870B TW473870B TW089109877A TW89109877A TW473870B TW 473870 B TW473870 B TW 473870B TW 089109877 A TW089109877 A TW 089109877A TW 89109877 A TW89109877 A TW 89109877A TW 473870 B TW473870 B TW 473870B
- Authority
- TW
- Taiwan
- Prior art keywords
- dielectric layer
- carbon
- layer
- dielectric
- oxygen
- Prior art date
Links
- 239000003989 dielectric material Substances 0.000 title description 12
- 238000005530 etching Methods 0.000 claims abstract description 141
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 125
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 123
- 239000007789 gas Substances 0.000 claims abstract description 119
- 238000000034 method Methods 0.000 claims abstract description 77
- 239000001257 hydrogen Substances 0.000 claims abstract description 67
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 67
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 58
- 238000000151 deposition Methods 0.000 claims abstract description 50
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910002091 carbon monoxide Inorganic materials 0.000 claims abstract description 10
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 380
- 239000001301 oxygen Substances 0.000 claims description 43
- 229910052760 oxygen Inorganic materials 0.000 claims description 43
- 238000011049 filling Methods 0.000 claims description 39
- 238000012545 processing Methods 0.000 claims description 39
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 36
- 239000000203 mixture Substances 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 25
- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical compound [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052786 argon Inorganic materials 0.000 claims description 18
- 150000002927 oxygen compounds Chemical class 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- 230000001590 oxidative effect Effects 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 150000001875 compounds Chemical class 0.000 claims description 14
- 150000003377 silicon compounds Chemical class 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 150000002431 hydrogen Chemical class 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 150000003961 organosilicon compounds Chemical class 0.000 claims description 7
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 claims description 5
- 238000013467 fragmentation Methods 0.000 claims description 4
- 238000006062 fragmentation reaction Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 8
- 229920000742 Cotton Polymers 0.000 claims 1
- PRPAGESBURMWTI-UHFFFAOYSA-N [C].[F] Chemical class [C].[F] PRPAGESBURMWTI-UHFFFAOYSA-N 0.000 claims 1
- 150000002222 fluorine compounds Chemical class 0.000 claims 1
- 239000011229 interlayer Substances 0.000 claims 1
- 150000002894 organic compounds Chemical class 0.000 claims 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 abstract description 60
- 230000008021 deposition Effects 0.000 abstract description 31
- 229910001882 dioxygen Inorganic materials 0.000 abstract description 25
- 230000015572 biosynthetic process Effects 0.000 abstract description 11
- 230000009977 dual effect Effects 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 description 47
- 229920002120 photoresistant polymer Polymers 0.000 description 45
- 230000008569 process Effects 0.000 description 40
- 230000004888 barrier function Effects 0.000 description 36
- 238000002161 passivation Methods 0.000 description 19
- 230000002079 cooperative effect Effects 0.000 description 18
- 239000004020 conductor Substances 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 13
- 239000010949 copper Substances 0.000 description 13
- 229910052802 copper Inorganic materials 0.000 description 13
- 241000894007 species Species 0.000 description 12
- 238000009826 distribution Methods 0.000 description 11
- 238000013461 design Methods 0.000 description 10
- 238000011068 loading method Methods 0.000 description 10
- 238000011282 treatment Methods 0.000 description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 9
- 229910010271 silicon carbide Inorganic materials 0.000 description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 8
- 230000008859 change Effects 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 8
- 239000011261 inert gas Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 6
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 229910052731 fluorine Inorganic materials 0.000 description 6
- 239000011737 fluorine Substances 0.000 description 6
- 239000001307 helium Substances 0.000 description 6
- 229910052734 helium Inorganic materials 0.000 description 6
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 6
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 6
- 238000002156 mixing Methods 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000012546 transfer Methods 0.000 description 6
- 229910003828 SiH3 Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000004090 dissolution Methods 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 4
- 229910000831 Steel Inorganic materials 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 4
- 238000001816 cooling Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000009434 installation Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- -1 methylsilyl Chemical group 0.000 description 4
- 239000010959 steel Substances 0.000 description 4
- 150000001335 aliphatic alkanes Chemical class 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 230000005284 excitation Effects 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- CSJDCSCTVDEHRN-UHFFFAOYSA-N methane;molecular oxygen Chemical compound C.O=O CSJDCSCTVDEHRN-UHFFFAOYSA-N 0.000 description 3
- NCWQJOGVLLNWEO-UHFFFAOYSA-N methylsilicon Chemical compound [Si]C NCWQJOGVLLNWEO-UHFFFAOYSA-N 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 150000001282 organosilanes Chemical class 0.000 description 3
- 125000005375 organosiloxane group Chemical group 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 239000012495 reaction gas Substances 0.000 description 3
- 150000004756 silanes Chemical class 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 238000004804 winding Methods 0.000 description 3
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 2
- YZCKVEUIGOORGS-NJFSPNSNSA-N Tritium Chemical compound [3H] YZCKVEUIGOORGS-NJFSPNSNSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- BGTFCAQCKWKTRL-YDEUACAXSA-N chembl1095986 Chemical compound C1[C@@H](N)[C@@H](O)[C@H](C)O[C@H]1O[C@@H]([C@H]1C(N[C@H](C2=CC(O)=CC(O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O)=C2C=2C(O)=CC=C(C=2)[C@@H](NC(=O)[C@@H]2NC(=O)[C@@H]3C=4C=C(C(=C(O)C=4)C)OC=4C(O)=CC=C(C=4)[C@@H](N)C(=O)N[C@@H](C(=O)N3)[C@H](O)C=3C=CC(O4)=CC=3)C(=O)N1)C(O)=O)=O)C(C=C1)=CC=C1OC1=C(O[C@@H]3[C@H]([C@H](O)[C@@H](O)[C@H](CO[C@@H]5[C@H]([C@@H](O)[C@H](O)[C@@H](C)O5)O)O3)O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O[C@@H]3[C@H]([C@H](O)[C@@H](CO)O3)O)C4=CC2=C1 BGTFCAQCKWKTRL-YDEUACAXSA-N 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000839 emulsion Substances 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- HCOKJWUULRTBRS-UHFFFAOYSA-N propan-2-yloxysilane Chemical compound CC(C)O[SiH3] HCOKJWUULRTBRS-UHFFFAOYSA-N 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000001878 scanning electron micrograph Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- 229910052722 tritium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 description 1
- 241000238876 Acari Species 0.000 description 1
- 240000008564 Boehmeria nivea Species 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 241000196324 Embryophyta Species 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 241000282376 Panthera tigris Species 0.000 description 1
- 241001494479 Pecora Species 0.000 description 1
- XBDQKXXYIPTUBI-UHFFFAOYSA-M Propionate Chemical compound CCC([O-])=O XBDQKXXYIPTUBI-UHFFFAOYSA-M 0.000 description 1
- BKHJHGONWLDYCV-UHFFFAOYSA-N [C]=O.[C] Chemical compound [C]=O.[C] BKHJHGONWLDYCV-UHFFFAOYSA-N 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000002826 coolant Substances 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 125000000118 dimethyl group Chemical group [H]C([H])([H])* 0.000 description 1
- UBHZUDXTHNMNLD-UHFFFAOYSA-N dimethylsilane Chemical compound C[SiH2]C UBHZUDXTHNMNLD-UHFFFAOYSA-N 0.000 description 1
- XCLIHDJZGPCUBT-UHFFFAOYSA-N dimethylsilanediol Chemical compound C[Si](C)(O)O XCLIHDJZGPCUBT-UHFFFAOYSA-N 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical compound [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 150000002430 hydrocarbons Chemical group 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 1
- 235000012054 meals Nutrition 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- CBXZGERYGLVXSG-UHFFFAOYSA-N methyl(2-methylsilylethyl)silane Chemical compound C[SiH2]CC[SiH2]C CBXZGERYGLVXSG-UHFFFAOYSA-N 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000008267 milk Substances 0.000 description 1
- 210000004080 milk Anatomy 0.000 description 1
- 235000013336 milk Nutrition 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 125000000962 organic group Chemical group 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 239000001294 propane Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 238000007142 ring opening reaction Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000003307 slaughter Methods 0.000 description 1
- 239000010802 sludge Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000006276 transfer reaction Methods 0.000 description 1
- 125000002023 trifluoromethyl group Chemical group FC(F)(F)* 0.000 description 1
- 150000004901 trioxanes Chemical class 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/312—Organic layers, e.g. photoresist
- H01L21/3121—Layers comprising organo-silicon compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
- H01L21/31612—Deposition of SiO2 on a silicon body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31633—Deposition of carbon doped silicon oxide, e.g. SiOC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Organic Chemistry (AREA)
- Metallurgy (AREA)
- Mechanical Engineering (AREA)
- Materials Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Description
473SV0 A7 B7 經濟部智慧財產局員工消费合作社印製 五、發明說明() 發明領域: 本發明關係於積體電路之製造。更明確地說,本發明 關係於用以沉積及蝕刻於基材上之介電層之製程與設備。 發明背景: 半導體裝置幾何於大小上已經劇烈地降低,因為這些 裝置已經形成了有幾十年。從那時起,積體電路已經大致 依循兩年/一半大小原則(經常稱為莫耳定律)進行,這表示 於一晶片上之裝置數量每兩年增加一倍。今日之製造廠係 經常地生產具有0.35微米甚至是0.18微米特性大小之裝 置,及明日之工廠將很快能生產具有更小幾何之裝置。 為了進一步減少於積體電路上之裝置大小,必須使用 具有低電阻率之導電材料及具有低介電常數(k$ 4.0)之絕 緣體,以降低於相鄰金屬線間之電容耦合。想要之導電材 料為銅,其可以藉由電化學沉積法沉積於次微米特性中β 想要介電材料係為含碳之矽氧化物。氧化矽材料及銅之組 合已經造就了用於備製垂直及水平内連線之新的沉積方 法,因為銅並不容易以形成金屬線。此等方法包含沉積垂 直及水平内連線之鑲嵌法或雙層鑲嵌法,其中,一或多數 介電材料被沉積及蝕刻以形成垂直及水平内連線’其被填 以導電材料。 介電層可以於多數步驟中,沉積,蝕刻及填充以金 屬,諸步辣係典型需要經常地傳送基材於指定給特定步驟 第2頁 本紙張尺度剌t s S家縣(CNS)A4祕(210 X撕公釐) ' (請先閱讀背面之注意事項再填寫本頁) · I 1 I ! I 訂·! •梦 473870
經濟部智慧財產局員工消费合作社印製 之處:室之間。用以沉積介電層之較佳方法包含兩主要雙 層鑲嵌法,其中^ 薄渠係同時被填以介層/接點。於一, 相對孔,•設計中,一連串介電層係沉積於-基材上,如同 於本案之各實施例中所詳述者。然後,垂直内連線,例如 介層/接點係银刻貫穿所有層及水m線線… 係姓刻穿過頂層。於另一實施例中,線/溝渠係#姓刻於: 層中,然後,介層/接點係被蚀刻穿過底廣。電材料然 後沉積於垂直及水平内連線中。 用以創造雙層鑲嵌結構之另一主要設計被稱為,i行 碧―屬"(SAC)設計。SAC設計係類似於相對孔設計,除 了 一蝕刻阻層係沉積於一底介電層並被蝕刻,以於另一介 電層沉積於蝕刻阻層上前,定義介層/接點。垂直及水平内 連線然後於單一步驟中被蝕刻,及導電材料然後沉積於垂 直及水平内連線中。 0 若上介電層可以使用於上層蝕刻率至少三倍大於下 層之相對蝕刻率之狀況(即丝割選擇性為至衣 對孔設計於介電層間並不需要一蝕刻阻層。但是,用於傳 統低k介電層之蝕刻處理之選擇性典型係少於3 : !,以 及,用以提供想要蝕刻選擇性之蝕刻阻層係經常地用於低 k值介電層間。蝕刻阻層^供於整個基材表面之水平内連 線沉積方向之均勻性。蚀ΐ阻層更進一步降低微溝渠之形 成’使彳于矣:邊^渠之底部於外侧緣處係較平而不是較深。 蚀刻阻層更進一步降低於蝕刻水平内連線時,先前蝕刻垂 直内連線之斜面或圍起’其中於水平内連線之底部及垂直 第3頁
一 ^ Μ--------^---------^ (請先閱讀背面之注意事項再填寫本頁W 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 473870
經濟部智慧財產局員工消費合作社印製 内連線之側壁間之邊緣係尖銳而不是圓滑(即斜面)或突起 (圍高)’這是取決於垂直内連線之侧壁是否外露至蝕刻氣 體或與蝕刻氣體相隔而定。 傳統蝕刻阻層提供前述鑲嵌應用之優點,但典型具有 遠大於4之介電常數。例如,氮化矽具有約7之介電常數, 沉積此一蝕刻阻層於低k值介電層上造成對組合層之介電 常數的大量增加。吾人已經發現即使在低k介電材料使用 作為主要絕緣體之情形下,氮化矽可以大量增加於内連線 間之零H…這造成奉音及/或電阻電容(RC)延遲,而降 低了裝置之整個效能。 理想上’低k值介電層將被指出及蚀刻製程將被定義 為’用於例如雙層鑲嵌製程之選擇性蝕刻製程中,其中用 於介電層之蝕刻選擇性至少約3 : 1 ^較佳地,提供想要蝕 刻選擇性之低k值介電層可以沉積於同一室中。 i明目的及概诫: I 本發明提供一種(4刻多有小於或等於4.0(低k值)之 j介電常數之一或多數介電層之方法,其中,於介電質成份 i之„美择供了矣…之3: 1之蝕刻選擇性。本發明包含蝕刻含 ί i珍’氧,碳及氫之介電層的蝕刻,其中於成份間之差異於 沒有例如一氧化碳之碳:氧氣體時,提供大於3 :丨之餘 性。將碳··氧氣體加入至一或多數氟碳氣體中,於 較低蚀刻選擇性中提供了較快蝕刻率,這可以使用於不需 要高選擇性時β至少一介電層係較佳具有高碳含量(約1 第4頁 本紙張尺度適用中國國家標準(CNS)A4規格(21G X 297公爱) ' — ----------I!,裝--------訂· (請先閱讀背面之注意事項再填寫本頁) 473SV0 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明() 原子量。/〇)或高氫含量(約0]原子量%)。例如,當形成水 平内連線時,想要選擇性蝕刻相鄰介電層時,碳:氧氣體 被引入或由蝕刻氣體中省略。 2)本發明更提供一^方法’用以?Lf及蝕刻相獻低k 上立農並料,同時,於室之間具有笔^材傳送,及 於相鄰介電材料間之蝕刻選擇性至少3 : 1 ^高蝕刻選擇性 提供具有均勻深度及大致正方形角落之水平内連線,而不 刻里層。至少一介電層含有矽,氧,碳及氫。其 他介電層可以是任一具有介電常數少於4之介電層,其係 例如藉由旋塗沉積法或化學氣相沉積法所產生者。所有介 電層較佳係藉由化學沉積一或多數有機矽化合物,使用功 率位準,流量,及成份之變化,以控制蝕刻選擇性,藉由 控制沉積材料之碎,氧,碳及氫之含量。 於第一較佳之雙層鑲嵌實施例中,一第一低值介電 層及一第二隻k值介電層係沉積於一基材上,藉由氧化一 或多數有機矽化合物,例如甲基矽烷,CH3SiH3 ,或三甲 基矽烷,(CH3)3-Si-〇-Si-(CH3)3 ,用以兔^續蝕刻垂直及水 平内連線。第一介電層為一:義刻阻層,其包含矽,氧,碳, 及氫,較佳依約5原子量%氫,及約丨原子量%氫。第二 介電層較佳包含少於三分之二之碳或五分之一之氫含於 第二介電層中,最好是少於一半之碳或少於十分之一之 氮。垂直及水平内連線係然後使用氟碳氣體被蝕 值介電層中。一例如一氧化碳之碳:氧化合物係於蚀刻垂 直内連線時,加入氟碳氣體中,並於蝕刻水平内連線時, 第5頁 ---------1---- --------^---------麥 , ~ (請先閱讀背面之注意事項再填寫本頁) 本紐尺度適时關家標準(CNS)A4規格⑽χ挪公楚》 4733'
第约作呢7號專利案%年修芷 經濟部智慧財產局員工消費合作社印製 五、發明說明( 未被使用’以取得至少3 : 1之蝕刻選擇性。然後,水平 及垂直内連線可以被填以一例如銅之導電材料。 於第二較佳之雙層鑲嵌實施例中,一第一低k值介電 層,一第二低k值介電層,及一第三低k值介電層係藉由 氧化一或多數有機矽化合物,例如甲基矽燒,CH3SiH3 , 或二甲基硬燒,(CH3)3-Si-〇-Si-(CH3)3,而沉積於一基材 上’用以後續蝕刻垂直及水平内連線。第二介電層係為一 蚀刻阻層並含碎,氧,碳,及較佳5原子量%碳,及約1 原子量°/〇氫第一及第三介電層較佳包含低於三分之二之 碳及於第二介電層中含少於五分之一之氫,最好是少於一 半之碳及少於十分之一之氫。垂直及水平内連線然後使用 氟碳氣體被蝕刻入低k值介電層。一例如一氧化碳之碳: 氧化合物於蝕刻垂直内連線時被加入氟碳氣體中,及較佳 於蝕刻水平内連線時未使用,以取得至少3 ·· 1之蚀刻選 擇性。水平及垂直内連線可以然後被填以一例如銅之導電 材料。 本發明之上述特性,優點及目的係可以取得並可以詳 細了解,本發明之一更詳細說明可以參考如附圖所示之實 施例加以總結如上,該實施例係示於附圖中。 然而,應注意的是,附圖為本發明之典型實施例,並 不應被認為限制其範圍,因為本發明可以應用至其他等效 實施例中β 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 29/公釐)
It n ί ϋ n n n ϋ n n n » . n n n l I i n^OJ· n ! n n d I n I (請先閱讀背面之注意事項再填寫本頁) 473S70 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明() 圖式簡箪說明Z 第1A-1H圖為本發明之第一實施例之雙層鑲嵌沉積法程 序之剖面圖; 第2A-2H圖為本發明之第二實施例之雙層鑲嵌沉積法程 序之剖面圖; 第3圖為用於依據本發明之例示CVD電漿反應器之剖面 圃, 第4圖為於四個低k值介電化合物中之碳及氫之相對量, 該化合物包含矽,氧,碳及氫;及 第5圖為實施本發明之蝕刻處理之蝕刻處理室之垂直剖面 圖。 為了更了解本發明,請參考以下之詳細說明。 圖號#照說明: 10 介電層 12 介電層 14 阻障層 16 導電材料 18 介電層 20 光阻層 22 水平内連線 24 光阻層 26 垂直内連線 28 阻障層 30 導電材料 40 蝕刻阻擋層 42 介電層 44 介電層 46 阻障層 48 導電材料 50 介電層 52 硬罩層 54 垂直内連線 55 阻擋層 第7頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------户 473S70 A7 B7 五、發明說明() 經濟部智慧財產局員工消費合作社印製 56 水平内連線 58 阻障層 110 化學氣相沉積反應器 111 氣體分配歧管 112 晶座 113 支撐柄 114 抬舉馬達 115 高真空區 117 絕緣器 118 氣體管線 119 混合系統 124 歧管 125 RF電源 128 微波施加器 132 真空泵 134 系統控制器 136 控制管線 138 記憶體 140 處理室 142 螺線管線圈 144 繞組 146 對稱軸 150 圓柱側壁 152 天花板 154 托架 156 基材 158 環形通道 160 環帶 162 可棄環 164 氣體饋送件 166 外殼 168 RF電源 170 偏壓電源 172 加熱器 173 導熱材料 174 冷卻板 175 環面 176 熱耦器 177 輻射加熱器 178 窗 179 溫度感應益· 180 電漿侷限磁鐵 182 電漿侷限磁鐵 184 晶圓狹隙 190 外線圈 192 繞組 194 線圈 196 分離器 第8頁 -------------^ -裝--------訂---------,r (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) CO 3 7 4 經濟部智慧財產局員工消費合作社印製 A7 ------------』7___ _ 五、發明說明() 發明詳細說明: 本發明提供一種用以蝕刻低k值介電層(即k值小於 等於4,較佳小於3)之方法。本發明包含蝕刻一或多數介 電層,其中於介電質化合物中之差異提供至少3: t之蝕 刻選擇性。該方法理想上係適用以選擇性蝕刻處理,例如 鑲嵌設計中,其沉積例如鋼之導電材料於形成於低k值介 電層之内連線中。於較佳實施例中,本發明包含樣級蘇: 各氣脱與氟碳飯刻範體之組合,以控制含氫及碳之低k值 介電層之姓刻§ U生。本發明更提供於相鄰介電層之碳及 氫含量控制,以取得低介電常數及有利於一介電層之至少 3 : .1—ϋ刻锋擇性。因此,低k值介電層提供足夠蝕刻選 擇性’以排除具有高介電常數之傳統蝕刻阻,擋:抹榦,例如 氮化碎沉積及姓刻處理,例如讓嵌設計中。相較於其他使 用相同蝕刻條件之介電層,具有低介電常數及低蝕刻率之 介電層可以替代或消除於很多處理中之蝕刻阻擋層。本發 明之整合沉積及蝕刻法同時可以降低基材於反應室間之 傳送量,藉以允許所有、介電層於蝕刻前被沉積於單一室 〆 ....... 中 〇 本發明之方法提供一整合雙層鑲嵌處理,其包含浼積 一第一低k值介電層,其包含有梦,碳’氧及氫。一沉積 於第一低k值介電層上之第二低k值介電層較佳包含少於 三分之二之碳及少於五分之一之氫於第一介電層中,最好 是少於一半之碳及少於十分之一之氫。該兩介電層均可以 被例如以氟碳化合物及碳··氧化合物,例如一氧化碳之混 第9頁 本紙張尺度適用_國國家標準(CNS)A4規格(210 X 297公釐) •丨!丨!霧— I、裝!! —訂--— — —於 f請先閱讀背面之注意事項再填寫本頁) 473370 A7 B7 五、發明說明() 合物來蚀刻,以形成具有陡峭側壁及尖角落之垂直内連 線。具有低碳或氫含量之介電層係選擇性蝕刻,例如,減 少或消除碳··氧氣體流,以提供至少3 ·· 1之選擇性,而 有利於具有低碳或氫含量之介電層。 一含至少約1原子量%碳及〇·1原子量%氫之氧化發 係藉由旋塗或化學氣相沉積一或多數有機矽化合物而產 生,化學氣相沉積係使用功率位準,流率及成份改變,以 控制所沉積材料之碳含量及氫含量^具有變化碳或氫含量 之低k值介電層可以沉積於單一室中,以於雙層鑲嵌法 中,提供所有介電層。所沉積介電層然後以氣體加以蝕 刻,諸氣體可控制於蝕刻特性表面上之鈍化沉積物,以提 供於相鄰介電層間之至少3 ·· 1之蚀刻選擇性,諸介電層 具有少於4,最好是少於3之介電常數。 本發明廣泛地包含蚀刻相鄰低k值介電層。本發明以 下所主張之範圍係由以下用以蝕刻或沉積含碳或氫之介 電層之較佳實施例說明所支撐。 第一較佳雙層鑲嵌製程 一示於第1A-1H圖之較佳雙層鑲嵌製程包含蝕刻兩 相鄰低k值介電層1 0,1 2,其中,於兩層間之蝕刻選擇性 係至少3 : 1,當蝕刻氣體含氟碳氣體及大致沒有碳:氧化 合物時。換句話說,相鄰低k值介電層具有不南成份,及 第二層12具有一蝕刻率,其係至少三倍大於第一層10之 蝕刻率,於蝕刻氣體包含氟碳氣體,而大致沒有碳:氧氣 第10頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) ----I---訂-------—- 經濟部智慧財產局員工消费合作社印製 473S70 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明( 體量時。第-介電層10於蝕刻第二介電層㈣,作為一 钱刻阻擋層。例如一氧化碳之藏:氧化合物之加入至姓刻 氣體中,改變了介電層10,12之姓刻速率,使得兩層可 以被蝕刻,而不會實質改變蝕刻氣體成份。 參考第1A圖,一包含有矽,氧,碳,及氫之第一低 k值介電層ίο,例如旋塗低k值(摻雜)或藉由氧化一含c_h 鍵及c-si鍵之有機矽化合物而沉積之CVD層係沉積於一 阻障層14之上。第一低k值介電層1〇較佳含至少約$原 子量%碳,或至少約1原子量%氫。一例如旋塗低k值介 電質(摻雜或未摻雜)或由氧化有機矽化合物所沉積之CVD 層之第二低k值介電層12包含較含於第一介電層1〇中之 碳少於約二分之二及氳少於約五分之一,其較佳為少於一 半之碳及少於十分之一之氫。介電層10,12典型係沉積 於一阻障層14上,例如氮化矽或碳化矽上,以防止介電 層被例如銅之導電材料1 6所擴散,該銅係填充於前一介 電層18中之特性。於第一介電層1〇及阻障層14間之蚀 刻選擇性係至少2 : 1。一光阻層20或一硬罩層係沉積於 介電層10’ 12之堆疊上,以轉移一圖案,該圖案係被蝕 刻入介電層者。第一介電層10包含足夠碳或氫,以令蝕 刻率係至少三倍低於第二介電層之蝕刻率,當以一或 多數氟碳氣體及大致上沒有碳··氧氣體蝕刻時。 用以沉積第一及第二介電層1 0,1 2,以取禅變化碳及 氫含量之方法係如以下所詳述。沉積具有低碳含量(少於 約1原子量。/。碳)及低氫含量(少於約0.1原子量%氫)之低k 第11頁 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 x 297公釐) — I— I---:--- ----I--- ---------^ <請先閲讀背面之注意事項再填寫本頁) 473370 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明() 值介電層可以使用傳統用以沉積氧化矽之製程加以執 行’例如被稱為四乙氧甲矽烷之原矽酸四乙酯之氧化。 第一介電層10較佳係沉積至約5000至約10000埃之 厚度。第二介電層12係然後沉積至約5000至約10000埃。 介電層10,12可以使用相同反應劑,例如甲基矽烷或三 甲基碎氧燒加以沉積於同一室中,藉由如以下例子所述改 變流速或功率位準。當阻障層14為一碳化矽層時,阻障 層可以使用相同有機矽化合物被沉積於同一室中。 雖然,第一介電層可以於沉積第二介電層前被蝕刻, 但較佳是於以組合氟碳氣體及碳:氧氣體蝕刻前,沉積該 兩介電層。 參考第1B圖,一光阻或硬罩20係被作出圖案,以定 義予以蝕刻於第二介電層1 2中之水平内連線22。如於以 下實施例所示,一定義垂直内連線之圖案可以首先被使 用。一典型用於氧化矽之光阻係由杜邦化學公司所製造之 "RISTON、光阻係曝露於UV光下,以定義圖案然後光阻 之部份係被剝離。一例如含碳或氫之氧化矽層的硬罩可以 用於光阻下,並被蝕刻如以下所述,於圖案被顯影於光阻 後。光阻或硬罩然後提供圖案,其係被轉移至下層。, 參考第1C圖,水平内連線22然後使用組合一或多數 氟碳物,而大致沒有碳:氧氣體之氣體,以蚀刻入第二介 電層1 2之中。介電層之蝕刻以形成水平内連&較佳係使 用包含氬及一或多數由CF4, C2F6及C4F8選出之氣體的混 合’來加以執行。用以作出水平内連線22圖案之光阻或 第12頁 本紙張尺度適財國國家標準(CNS)A4規格(210 X 297公爱) ------1---^----裝--------訂---------梦 (請先閲讀背面之注意事項再填寫本頁) 473370 A7 —_ B7 _ 五、發明說明() 其他材料較佳係使用一氧/氫去灰處理,例如藉由氧及氨氣 之組合或藉由另一適當處理加以剥離。 (請先閱讀背面之注意事項再填寫本頁) 參考第1D圖,一第二光阻層24或硬罩係沉積於水平 内連線22上及一平坦面係提供作為定義垂直内連線26用 之圖案之轉移。光阻係曝露至UV光,以定義圖案,然後 光阻之部份係被去除,以定義垂直内連線26。光阻24及 硬罩提供圖案,其係於後續蝕刻中被轉移至下層。若垂直 内連線係首先被蝕刻如於下一實施例所述,則第二光阻戈 硬罩層將被用以定義水平内連線。 參考第1 E圖,第一介電層1 〇及阻障層24然後使用 組合一或多數氟碳物及碳:氧氣體的氣體所蝕刻,以完成 垂直内連線26。介電層之蝕刻,以形成垂直内連線較佳係 以包含氬,C0及一或多數由CF4,Cd6及C4F8選出之氣 體的混合加以執行。參考第1F圖,用以對垂直内連線Μ 作出圖案之光阻或其他材料較佳使用一氧/氫去灰處理加 以剝離,例如,藉由組合氧及氨氣或藉由另一適當處理進 行。 經濟部智慧財產局員工消费合作社印製 參考第1 G圖,一例如氮化鈕之適當阻障層2 8係首先 以保角方式,沉積於水平及垂直内連線22,26中,以防 止金屬遷移入周圍矽及/或介電材料。參考第圖,水平 及垂直内連線22,26係然後被填以一例如鋁,鋼,鎮, 或其組合之導電材料3〇。較佳地,由於銅之低電阻率 (1.7mW-cm相較於鋁之3.1mW-cm),趨勢係使用鋼以形成 較小特性。銅係使用化學氣相沉積,物理氣相沉積,電鍵 第13頁
經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 值 473S70
五、發明說明( 或/、、’且口加以/儿積,以形成導電結構。一旦結構被填以銅 或其他金屬’表面係使用化學機械研磨加以平坦化,如於 第1Η圖所示。 於另一實施例中,於第1Α-1Η圖中之第一介電層1〇 可以沉積於一啟始氧化矽層(未示出)上,其係例如藉由氧 化TEOS取得’當於第一介電層1〇及阻障層14間之蝕刻 選擇性係少於2 : 1時,例如當阻障層丨4為氮化矽及介電 層含大於5原子量%銅或大於丨原子量%氫時。啟始介電 層係被選擇以具有至少相對於阻障層丨4具有2 :丨之蝕刻 選擇性,使得垂直内連線26可以於阻障層被完全由垂直 内連線去除前被完全蝕刻。啟始氧化物層較佳具有由約 1000埃至約300埃之厚度,以提供垂直内連線完成至阻障 層之時間。 第二較佳雙層鑲嵌處理 示於第2A-2Η圖之另一較佳雙層鑲嵌處理替換一以 低k值介電層作為於兩低k值介電層42,44間之蚀刻阻 層40之傳統蝕刻阻擋層。當蝕刻氣體含有氟碳氣體及實 質上無碳:氧化合物時,介電層42,44具有一蚀刻率, 其係至少三倍大於蝕刻阻擋層40之蝕刻率之三倍。較佳 地,介電層及蝕刻阻擋層具有類似成份,除了蝕刻阻擋層 具有較高數量之碳或氧之外^ 參考第2A圖,一第一低k值介電層42及一第三低k 介電層44含有低量碳及氫,例如旋塗低k值(摻雜)或藉 第η頁 . ^— i- Μ--------1---------^ (請先閱讀背面之注意事項再填寫本頁) 473370 A7 B7 五、發明說明( 由氧化一有機碎化合物而沉積之pi 買又CVD層。一第二低k值 介電層40,蝕刻阻擋層,含有相备^ ’相㊣向量之碳或氫,例如旋 (請先閱讀背面之注意事項再填寫本頁) 塗低k值介電質(掺雜)或藉由氧化 〜具C-H鍵及C-Si鍵之 有機矽化合物而沉積一 CVD層。笛 ^ 第二低k值介電層40較 佳含至少約5原子量%碳,或至•丨 4主少約1原子量%氫。第一 及第三低k值介電層42, 44包本耘a - 匕。較含於第二介電層40中 之碳少於約三分之二及氫少於約五八 甘^ ^| ^ 立刀 <一,其較佳為少於 一半之碳及少於十分之一之氫〇各兩β 乳介電層40,42,44典型 係沉料-阻障層46 ±,例如氮切或碳化梦上,以防 止在下介電層50被例如飼之導電材料48所擴散,該銅係 填充於在下介電層50中之特性。笛 A ^ ^ W 第一介電層42及阻障層 46間之蝕刻選擇性係至少2 : 1。 光阻層或硬罩層52係沉積於介電層4〇 , 42 , 44 之堆疊上,以轉移一圖案,該圖案係被蚀刻入介電層者。 触刻阻擔層40較佳第一介電層1〇包含足夠碳或氫以令 蝕刻率係至少三倍低於第一及第三介電層42,料之蝕刻 率,當蝕刻氣體大致上沒有碳:氧氣體時。具有變化碳及 氫含量之介電層之沉積係細述如下。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 第一及第三介電層42,22較佳係沉積至約5〇〇〇盖約 10000埃之厚度。蝕刻阻擋層4〇係然後沉積至約5〇〇〇至 約10000埃。第一及第三介電層42,44及蝕刻阻擋層4〇 可以使用相同反應劑於同一室中加以沉積,藉由變化如以 下例子所述改變流速及或功率位準。當阻障脣46為一碳 化梦層時,阻障層可以如同介電層般被沉積於同一室中。 第15頁 473S70 A7 -------— B7 五、發明說明() 參考第2B ®,光p且52或硬罩係被作出圖案,以定義 丁以蝕刻於第一及第二低k值介電層42,“中之垂直内 連線54:如於以上第一實施例所示,一定義水平内連線之 圖案可以首先被使用。一典型用於氧化夺之光阻係由杜邦 =學公司㈣造之”RIST㈣。光阻係曝露於㈣光下,以 疋義圖案然後光阻之部份係被剥離。一例如含碳或氫之氧 化矽層的硬罩可以用於光阻下,並被蝕刻如以下所述,於 圖案被顯影於光阻後。光阻或硬罩然後提供圖案,其係被 轉移至下層。 參考第2C圖,垂直内連線54然後使用組合氟碳物及 碳·氧氣體的氣體,以蝕刻入第一及第二⑯“直介電層 42 ’ 44 ’低k值蝕刻阻擋層4〇及阻障層46之中。介電層 足蝕刻以形成垂直内連線較佳係使用包含氬,c〇及一或 多數由CF4,(:2匕及CUFs選出之氣體的混合,來加以執行。 用以作出垂直内連線54圖案之光阻或其他材料較佳係使 用一氧/氫去灰處理,例如藉由氧及氨氣之組合或有必要 時,藉由另一適當處理加以剥離。 參考第2D圖,一第二光阻層55或硬罩係沉積並作出 圖案以定義水平内連線56。光阻係曝露至UV光,以定義 圖案,然後光阻之部份係被去除,以定義水平内連線56。 若水平内連線係首先被蝕刻,則第二光阻或硬罩層將被用 以定義垂直内連線,如於第一實施例所述者。若想要以降 低下層48之蝕刻的話,光阻可以留於垂直内連線54之底 部。 (請先閲讀背面之注意事項再填寫本頁) 裝 ----訂---------聲. 經濟部智慧財產局員工消費合作社印製 第16頁
473S70 A7 B7 經 濟 部 智 慧 財 產 局 員 X 消 費 合 作 社 印 製 五、發明說明( 參考第2E圖,第三介電層44然後使用組合一或多數 氟碳物及碳:氧氣體而實質沒有碳:氧氣體的氣體所蝕 刻,以完成水平内連線56。介電層之蝕刻,以形成水平内 連線56較佳係以包含氬,及一或多數由CF4, C2F6及C4F8 選出之氣體的混合加以執行,以提供相對於蝕刻阻擋層40 至少3 : 1之選擇性。碳:氧氣體被降低省略,以提供用 於蝕刻阻擋層40之較低蝕刻率。參考第2F圖,用以對水 平内連線56作出圖案之光阻或其他材料較佳於填充水平 及垂直内連線56,54前被剥離。光阻係較佳使用一氧/氫 去灰處理加以剥離,例如,藉由組合氧及氨氣或藉由另一 適當處理進行。 參考第2G圖,一例如氮化鈕之適當阻障層58係首先 以保角方式,沉積於水平及垂直内連線56 , 54中,以防 止金屬遷移入周圍矽及/或介電材料中。參考第2H圖,水 平及垂直内連線56,54係然後被填以一例如鋁,銅,鎢, 或其組合之導電材料60,如於第一實施例所述。 取決於蚀刻處理之選擇性,水平或垂直内連線可以於 /儿積每一介電層後被蝕刻。或者,蝕刻阻擋層可以於沉積 第三介電層前被蝕刻。然而,於室間之基材之傳送係必須 的,以於介電層沉積及蝕刻間作變換。 於另實施例中,不於第2A-2H圖中之蝕刻阻擋層 40可以是沉積於傳絲+啻麻j, ^ 、得轭介電層42上之氮化矽或碳化矽,具 $大於〇之,丨電常數。因此,低k值介電屠44將加強 水平内連線56之隔離’同時傳統介電層η適當地隔離垂 第17頁 a張尺度適用中國國家標準 -------—^—、裝--------訂---------梦 <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 473S70 Α7 Β7 五、發明說明() 直内連線5 4。 低k值介電層之沉積 本發明於適用以於介電層中形成水平内連線之蚀刻 條件下,提供一具有低介電常數(k小於等於約4·〇)並具 有蝕刻率3倍低於相鄰低k值介電層之蝕刻率。此低k值 介電層可以藉由旋塗或CVD方法加以產生,其中形成有 含碳及氫之碳化矽或氧化矽層。具有變化蝕刻率之低k值 層可以產生於同一室中,藉由改變如以下所述之處理氣體 之數量。 較佳低k值介電層係藉由氧化有機矽化合物加以生 產’該有機梦化合物包含C-H鍵及C-Si鍵,例如甲基梦 烷,CH3SiH3,二甲基矽烷,(CH3)2SiH2 ,三甲基碎燒, (Ch3)3SiH,1,1,3,3-四甲基雙矽氧矽,(CH3)2-SnsiH_ (CH3)2,或三甲基矽氧烷,(CH3)3-Si-〇-Si-(CH3)3。氧化碎 層係被於低溫及於高溫固化,以穩定諸特性。沉積介電層 之碳及氫含量係被藉由變化處理條件加以控制,例如改變 另一有機矽化合物,藉由以例如氧,臭氧,氧氧化物及水 之氧化氣體加以氧化,藉由於沉積時改變功率位準, 及改變處理氣體之流速。 留於氧化碎或碳化梦層中之碳或氫造就低介電常 數’良妤阻障特性及降低之蚀刻率。氧化矽或竣化碎屠係 由矽化合物產生’該梦化合物包含於有機群中之碳,其係 不能於處理條件下’迅速藉由氧化加以去除。較佳地,包 第18頁 i紙張尺度適用中國國家標準(CNS>A4規格(210 X 297公釐)-------- - -----;--'裝--------訂 -------梦 (請先閱讀背面之注意事項再填寫本頁) 473870 A7 B7 五、發明說明( 含有C-H键’例如烷族或芳族。適當有機族可以包含烷及 環乙婦基族及官能衍生物。有機矽化合物含碳對矽之變化 比例並包含: 甲基矽烷 二甲基矽烷 三甲基矽烷 四甲基矽烷 二甲取甲矽烷二醇 乙基矽烷 苯基矽烷 二苯基矽烷二醇 甲基苯基矽烷 乙矽烷基甲基 雙(甲基甲矽烷基)甲烷 1.2 -二矽烷基乙烷 CH3-SiH3 (CH3)2-SiH2 (CH3)3-SiH (CH3)4-Si(CH3)2-Si-(OH)2 CH3-CH2-S1H3 C6H5-SiH3 (C6H5)2-Si-(OH)3 C6H5-SiH2-CH3 SiH3-CH2-SiH3 CH3-SiH2-CH2-SiH2-CH3 SiH3-CH2-CH2-SiH3 1,2-雙(甲基甲矽烷基)乙烷 CH3-SiH2-CH2-CH2-SiH2-CH3 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 2.2- 二甲碎淀基丙垸 1,3,5-三伸矽烷-三伸甲基 1.3- 二甲基乙矽醚 1,1,3,3-四甲基乙矽醚 三甲基矽氧烷 1,3-雙(矽烷伸甲)連矽醚 雙(1-甲基乙矽醚)甲烷
SiH3-C(CH3)2-SiH3 -(-SiH2CH2-)3-(環) CH3-SiH2-0-SiH2-CH3 (CH3)2-SiH-0-SiH-(CH3)2 (CH3)3-Si-0-Si-(CH3)3 (SiH3-CH2.SiH2-)〇 (CH3-SiH2-0-SiH2-)2-CH2 ,,2-雙(1-甲基乙矽醚)丙烷((^3-81112-0-81112-)2-€((:113)2 第19頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 473S70 A7 _ B7 經濟部智慧財產局員工消費合作社印製 五、發明說明() 2,4,6,8-四甲基環四矽氧烷 -(-SiHCH3-0-)4-(環) 八甲基環四矽氧烷 -(-Si(CH3)2-〇-)4-(環)2,4,6,8,10-五甲基環五矽氧烷-(-3旧(^3-〇-)5-(環) 1,3,5,7-四矽烷基-2,6·二氧-4,8-二伸甲基 .(-SiH2-CH2.SiH2-0-)2-(環) 2,4,6-三矽烷代四氫派喃 -SiH2-CH2-SiH2-CH2-SiH2-〇-(環) 2,5-二矽烷代四氫夫喃 -SiH2-CH2-CH2-SiH2-〇-Q:|) 及其衍生物。 有機碎化合物係較佳於與氧(〇2)或例如氧化氮 (N2〇),臭氧(〇3),二氧化碳(C02)及水(H20),較佳為〇2 或N2〇之含氧化合物沉積時加以氧化,使得所沉積層之碳 含量係至少1原子量%碳及至少0 · 1原子量%氫含量。氧化 有機矽層較佳具有約3.0或更少之介電常數。氧化有機矽 層相較於傳統氧化矽化合物提供低蝕刻率。 有機矽化合物同時可以沉積為碳化矽層,藉以提供足 夠能量以分解化合物。此碳化矽層可以含低量氧,以協助 改變沉積層之蝕刻率。 於有機矽烷及有機矽氧燒中之碳氫族可以部份氟 化,以轉換C-H鍵為C-F鍵。很多較佳有機矽烷及有機矽 氧烷化合物係已商業化。兩種或多種有機矽烷或有機矽氧 烷之組合可以用以提供想要特性之混合,例如介電常數, 氧含量,疏水性,膜應力及電漿蝕刻特性等。 氧及含氧化合物較佳係被溶解,以於需要完成沉積層 中想要碳含量時增加反應性^ RF功率可以搞合至沉積室 第20頁 •I! ! > ----I I I —訂!--緣 (請先閱讀背面之注意事項再填寫本頁} 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱> 473870 A7 B7 五、發明說明( 中,以增加氧化化合物之溶解。氧之降低溶解或氧之減少 數量造成較南碳含量’特別是相較於鍵之較高含量 乏C-H或S1-CH3鍵。於進入沉積室前,氧化化合物可以 溶解於一微波室中,以減少於含矽化合物之過量溶解。氧 化矽層之沉積可以連續或不連續。雖然,沉積較佳發生於 單一沉積室中,但該層可以依序沉積於兩個或更多沉積室 中。再者,RF功率可以循環或被加脈衝,以降低基材之 加熱及提高於沉積層中之較大之多孔性。於沉積氧心矽層 時,基材係維持於由_20。(:至約4001之溫度,較佳係維持 於-20°C至40°C之間。 氧化有機矽化合物黏著至例如半導體基材之圖案層 之接觸面,以形成一沉積層❶沉積層係固化於低壓及由約 100至約45 01之溫度,較佳係約4〇(rc,以穩定於諸層中 之阻障特性。沉積層具有足夠氫含量以提供阻障特性。碳 含量較佳包含C-H或C-F鍵,以提供優良濕氣阻障之疏水 層。 本發明之方法利用一基材處理系統,具有一含反應區 之谷器,一陰極托架,用以定位一基材於該反應區,及一 真空系統。該處理系統更包含一氣體/流體分配系統連接至 容器之反應區,以供給有機矽烷或有機矽氧烷,氧化氣體 及惰性氣體,及一 RF產生器,連接至該氣體分配系統, 用以於反應區中產生一電漿。處理系統更包含义控制器, 其具有一電腦,用以控制該容器,氣體分配系統及RF產 生器,及一記憶體連接至該控制器,該記憶體包含電腦可 第21頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) (請先閱讀背面之注意事項再填寫本頁) 裝 經濟部智慧財產局員工消费合作社印製 473S70 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明() 用媒體,其包含-電腦可讀程式碼,用以選擇用來以有機 ㈣或有機碎氧烷化合物及—氧化氣體之電聚沉積低介 電常數層之處理步驟。 沉積氧化碎層之蚀刻可以於例如描述於美國專利第 5,843,847錢之傳統㈣室+執行,該案係併人作為參 考。一較佳蝕刻室係為由美國加州聖塔卡拉之應用材料公 司購得之IPS室。該847號專利更進一步描述介電層之餘 刻,其說明也併入作為參考。 本發明之進一步說明係關於用以沉積及蝕刻氧化矽 層4特定設備,及用以備製雙層鑲嵌氧化矽層之較佳沉積 及蚀刻順序。 例示CVD電漿反應室及處理 一可以用以執行本發明之方法之適當CVD電漿反應 器係示於第3圖中,其係為具有一高真空區115之平行板 化學氣相沉積反應器110之垂直,剖面圖。反應器11〇包 含一配氣歧管111,用以將處理氣體分配經於歧管中之穿 孔’至基材或晶圓(未示出),該基材係停放於一基材支撐 板或晶座11 2上,該晶座係為一抬舉馬達11 4所升高或降 低。一例如典型用於TEOS液體噴氣之液體喷氣系統(未示 出)可以提供以用以喷射液體有機矽烷及/或有機矽氧烷化 合物。較佳有機矽烷係為氣體。 广 反應器11 0包含例如藉由電阻性加熱線圈(未示出)或 外部燈(未示出)之處理氣體及基材之加熱。參考第3圖, 第22頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) — — — — — — III In k ·1111111 ^ ·11111111 ^ <請先閱讀背面之注意事項再填寫本頁) A7 B7
473370 五、發明說明() 晶座1 1 2係安裝於一支撐柄11 3上,使得晶座i i 2(及被支 撐於晶座1 1 2上表面之晶圓)可以以可控制方式移動於下 方裝/卸載位置及接近於歧管111之上方處理位置之間。 當晶座1 1 2及晶圓於處理位置丨丨4時,它們被一絕緣 器117所包圍及處理氣體排入至一歧管ι24。於處理時, 至歧管111之氣體入口係均勻地徑向分配於晶圓之整個表 面上。一具有一節流閥之真空泵132控制來自室之氣體之 排氣速率。 於到達歧管111前,沉積及載氣係經由氣體管線i i 8 進入至一混合系統119 ’於其中它們被混合然後送至歧管 111。一選用微波施加器128可以位於用於氧化氣體之輸 入氣體上’以提供只溶解氧化氣體之其他能量。微波施加 器提供由〇至6000瓦。一般而言,用於每一處理氣體之 處理氣體供給管線118同時也包含(〖)安全關閉閥(未示 出)’其可以用以自動或手動關閉進入室中之處理氣體 流’及(Π)質流控制器(也未示出),其量測經氣體供應管線 之氣體流量β當有機氣體用於處理中時,幾個安全關閉闕 係以傳統架構位於每一氣體供給線路上。 執行於反應器110中之沉積處理可以是一熱處瘦戈— 電漿加強處理。於一電漿處理中,一控制電裝係典型以由 RF電源125(晶座112接地)施加至分配歧管in之功 率’形成於靠近晶圓上。或者’ RF功率可以提供給晶座 112或RF功率可以以不同頻率提供至不同元件。RF電源 125可以供給早或混合頻率RF功率,以加強引入高真而 第23頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) -裝! !1 訂·! — 11 丨- 經濟部智慧財產局員工消費合作社印製 473370 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明() 區115中之反應物種之分解。一混合頻率rf電源典型供 給電源於13·56ΜΗζ之高RF頻率(RF1)至分配歧管ln , 及以360KHz之低rf頻率(RF2)供給晶座112。本發明之 氧化碎層係較佳使用低位準定高頻RF功率或脈衝式位準 之高頻RF功率。加脈衝rf功率較佳提供於約2〇瓦至約 5 00瓦之13·56ΜΗζ功率,最好是由約20瓦至約250瓦, 於約10至30%之工作週期。定rf功率較佳提供於約1〇 瓦至約200瓦之13.56MHzRF功率,較佳係由約20瓦至 約100瓦。低功率沉積較佳發生於由約-20至約4〇t之溫 度範圍。於該較佳溫度範圍中,沉積層係部份被聚合化於 沉積時,及聚合化係完成於後續層之固化時。 對於沉積碳化矽層,反應發生,而沒有大量氧源被引 入反應區中。較佳地,13.56MHzRF電源施加約300至700 瓦,以約4.3至10瓦每平方公分之功率密度至陽極及陰 極,以於室中以有機矽化合物形成電漿。於沉積SiC時, 基材表面溫度係維持於約200°C至400°C之間。最妤,處 理區域之三甲基矽烷或甲基矽健流率係於約 50至 200sccm,氦或氬氣流率係約200至lOOOsccm,室壓係由 約5至約10托耳,RF功率係由約400至約600瓦,以約 5.7至8.6瓦每平方公分之功率密度,及維持於約3 00°C至 400t之基材表面溫度。 典型地,任一室接管,分配歧管Π1,晶虚1丨2及各 種其他反應器硬體係由例如鋁或陽極化鋁以外之材料所 作成。此一 CVD反應器之例子係描述於美國專利第 第24頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ----------------\ ^--------^--------- ί請先閱讀背面之注意事項再填寫本頁) 473370 經濟部智慧財產局員工消费合作社印製 A7 五、發明說明() 5,000,1 13號中,其名稱為•,熱CVD/PECVD反應器及使用 沉積二氧化矽之熱化學氣相沉積及原處多步驟平坦化處 理”,該案係由王等人所領證並受讓給應用材料公司’即 本案之受讓人。 抬舉馬達114將晶座112升高及降低於一處理位置及 一下方晶圓裝載位置之間。馬達,氣體混合系統11 9及RF 電源1 2 5係由一於控制線路1 3 6上之系統控制器1 3 4所控 制》反應器包含類比組件,例如質流控制器(MFC)及標準 或加脈衝RF產生器,其係由系統控制器1 3 4所控制’該 控制器執行儲存於一記憶體1 3 8中之系統控制軟體,該記 憶體於此較佳實施例中為一硬碟機。馬達及光學感應器係 用以移動及決定可動機械組件,例如真空泵132及用以定 位晶座1 1 2之馬達的位置。 上述CVD系統說明係主要作例示目的,其他電漿CVD 設備,例如電極迴旋振盪(ECR)電漿CVD裝置,電感耦合 RF高密度電漿CVD裝置等可以被使用。另外,上述系統 之變化,例如於晶座設計,加熱器設計,RF功率連接之 位置等之變化也是可能的。例如,晶圓可以被一電阻性加 熱晶座所支撐及加熱。形成本發明預處理層之處理及方法 並不限定於任一特定設備或任一指定電漿激勵方法。 沉積於處理室中之低k介電質的蝕刻率係藉由調整處 理氣體流速及反應器功率位準加以控制,以沉精具有想要 碳及氫含量之介電層。用於描述於表i之較佳介電層Α·〇 之Si-Ch , Si-H或C-H鍵對Si_〇鍵數量之相對比例係示 第25頁 I ----"ΓΙΙ"7--^ * — — — — — — — ^«— — — — — — 1— (請先閱讀背面之注意事項再填寫本頁) 473370 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明() 於第4圖中。基於屉 增D芡原子分析,估計層a-D之氫及 碳含量係示於表1,栳炎庙 作為原子量%。於第4圖中,A-C代 表以34sccm之甲葚访p、士 士 碎虎 >瓦率’及D為68seem之流率。a 及D係於8 0瓦之功盘p、,隹 力奉位準’ B是於300瓦之功率位準, 及C為20瓦之功皋扦谁 +位旱。用以沉積層A-D之其他條件係 示於表1中。表贫/me 及弟4圖展現基於處理條件之改變之氫 及碳含量之變化性,免你士改。 其係本發明之一方面。於碳或氫含量 之變化然後用以提供且右彳 供 >、育低礙含量或低或含量之層之選 擇性蝕刻,如於以下所詳述。 一夺一1—产丞氫含量之處理條件 程式 A B C D 甲基矽烷 (seem) 34 34 34 68 N2〇(sccm) 360 360 360 360 He(sccm) 2000 2000 2000 2000 功率(瓦) 80 300 20 80 間隔(密耳) 320 320 320 320 壓力(托耳) 3.0 3.0 3.0 3.0 原子量%C 8 5 9.5 10.5 原子量%h2 5 0.3 2.5 3 例示蚀刻處理及室 用於介電層之較佳蚀刻疼理係描述於公告於1998年 十二月1日之美國專利第5,843,847號案中,其係併入作 第26頁 -----1---\ --------β---------^ (請先閲讀背面之注意事項再填寫本頁) 473370 Α7 Β7 五、發明說明() 為參考。於較佳處理中,於垂直及水平内連線之側壁蝕刻 係以形成鈍化沉積物加以控制,該鈍化沉積物係冷凝於側 壁上並降低側壁之蝕刻。蝕刻氣體包含氟碳氣體及混合於 定量之碳-氧氣體,以提供高選擇性或低選擇性,這是取 決於碳·氧氣體之量而定。蝕刻組成物同時提供低微負 載’其為用於大及小尺寸特性之蝕刻率差之量測。 為了提供南選擇性蝕刻及降低之微裝載給含氫及碳 之氧化矽層,吾人發現碳:氧氣體確實協助以去除過量鈍 化化合物,該化合物係由介電層釋放之碳或氩累積於蝕刻 特性表面上者。於蝕刻特性表面上之過量鈍化層限制了側 壁之蚀刻,當碳:氧氣體被引入蝕刻氣體中,及藉由降低 或停止碳·乳氣體流’驚奇地發生鈍化層之降低。 第5圖例示一具有單一晶圓處理室14〇之電感耦合 RF電漿蝕刻室,其係例如由美國加州聖塔卡拉應用材料 公司購得之IPS ETCH室。於此所示之蝕刻室之特定實施 例係提供以只例示本發明,並不用以限定本發明之範圍。 其他可以用以蝕刻介電層之電感耦合室,例如也由應用材 料公司購得之介電質蚀刻ΜχΡ+室也可以使用。諸介電層 可以被蝕刻於平行板電漿室中。 示於第5圖中之钮刻室係典型被抽氣至低於約1 5 〇毫 托耳之壓力,基材係被傳送至處理室140 » —電漿係藉由 雙螺線管線圈142’ 190所產生於處理室中,邊線圈具有 繞組144, 192以一非平面方式被集中於對稱軸ι46之旁, 對稱軸係與處理室140之中心重合。其他線圈架構,例如 第27頁 請 先 閱 讀 背 之 注 意 事 項 再 寫裝 本 頁 訂 t 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 〜丨"111丨-4 473370 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明( 選用線圈1 94對於熟習於本技藝者係明顯的。 處理室140係為一圓柱側壁15〇及一天花板152所包 圍。於處理室140底部之托架154支撐基材156。處理室 140係經由一環形路徑158排氣至抽氣環帶160,該環帶 包圍處理室140之下部份。環帶160之内部較佳以一可替 換襯墊160A加襯墊《環帶通路158係由側壁150之底緣 150A及一可棄式環丨62所定義,該環包圍托架154。處理 氣體經由一或多數氣體饋送管164 A-C加以提供。 中心螺線管線圈142係被繞於一外殼166,該外殼包 圍一中心輻射加熱器172。一第一電漿源RF電源168係 連接至一内線圈142及一第二電源196係連接至外線圈 190。或者,一單一電源197A可以使用一分離器196連接 至兩線圈。一偏壓電源170係連接至托架154。其他輻射 加熱器1 7 2,例如鹵素燈係安裝於天花板之未佔用區域, 以及,一具有冷卻劑通路174a之冷卻板174係停放於天 花板上。一環面175夾持該冷卻板174於室天花板152上。 多數軸孔175A延伸經環面175,用以安裝加熱器或燈 172。天花板溫度係被一熱耦器176所感應為了良好熱接 觸,一導熱材料173係放置於環面175及室天花板15,2之 間及於環面175及冷卻板174之間》 輻射加熱器177例如鎢鹵素燈係位於可遮環162下, 以透過窗178加熱該環。環162之溫度係使用溘度感應器 179加以控制,該感應器可以延伸於環162中之一孔 162A 〇 第28頁 ----------1--\ Μ--------訂---------^ (請先閱讀背面之注意事項再填寫本頁) 473370 經濟部智慧財產局員工消費合作社印製 第29頁 A7 B7 五、發明說明() 電漿侷限磁鐵1 80,1 82係提供於環形開口 1 58旁’ 以防止或減少進入泵環面160之電漿流量。可替換襯螯 160A係較佳被冷卻至一溫度,以收集進入環面160之主 動單體或物種。於抽氣環面1 60之壁中之晶圓狹隙1 84累 積晶圓進入及出口。 本發明之蝕刻處理提供於基材上之介電層之高蝕刻 率及高選擇蝕刻。用於蝕刻處理之處理氣體包含(i)氟碳氣 體,用以蝕刻介電層並形成鈍化沉積於基材上,(ii)碳-氧 氣體,用以減少鈍化沉積物之形成,及(iii)氬或含氮氣體, 用以去除基材上之沉積物。這些氣體之本質及氣體之較隹 容積流率將加以說明。 氟碳氣體係能形成含氟物種,其能蝕刻於基材上之介 電層。例如,一二氧化矽層係藉由含氟離子及中心加以蝕 刻’以形成揮發SiFx物種,其由處理室14〇排出。適當氟 後氣體包含碳,氟及選用氫,例如,CF3,CF4, CH3F, CHF3,C2H4F6,C2F6,C3F8,C4F8,C2HF5,及 C4F10。一 般相仏’於處理氣體中沒有氫提供增加之自由碳及Cf2原 子團,而造成非等向蝕刻及增加蝕刻選擇性。較佳係體包 含 cf4 , C2F6 及 c4f8。 , 當想要藉由控制含碳物種之形成及去除時,碳」氧氣 體係用以提供蝕刻選擇性,該物種形成鈍化沉積於基材 上。另外,碳:氧氣體加強與其他物種反應之自由氧物種 之形成,以減少聚合物之形成,該聚合物係沉積於蝕刻特 性之表面上作為鈍化沉積物。例如,CF2原子困聚合化,
本紙張尺度適用中國國家標準(CNS)A4規格(210 X — — — — — — — —i I I · ·1111111 ^* — — 1 —--I , (請先閱讀背面之注意事項再填寫本頁) 473370 A7 B7 五、發明說明( 以形成沉積在剛被蝕刻特性側壁上之聚合物,其係為鈍化 l積物以改良垂直非等向钱刻。為了這些理由,碳_氧 乳體 < 流速係大量降低或減少,以提供足夠含氟物種以快 速蝕刻介電層,同時,提供高介電質至下層蝕刻選擇性, 及非等向蚀刻。適當碳:氧氣體包含例如C〇,hc〇〇H, HCHO及C02,其巾CO係較佳的。氧可以加入以協助去 除形成於導孔及溝渠側壁上之過量鈍化沉積物β 吾人相信含氧氣體與一些Ch原子團相反應,以形成 揮發原子團,該揮發原子囷係被由處理室14〇排出。於物 種表面或電漿區中之增加之氧物種與自由碳反應,以降低 形成於基材上之純化沉積物之數量,並防止可能阻止蚀刻 處理之過厚鈍化沉積物層之沉積。 對於選擇性蝕刻’氟碳/碳:氧氣體之體積流量比係 被選擇,使得於剛蚀刻特性表面上之麵化沉積之形成速率 係不同於低k值介電材料。對於具有較快㈣率之介電材 料,純化沉積物之形成读襄你4- ^ .. 风逑羊係大約♦於鈍化沉積物之移除 率。對於具有較慢㈣速率之低介電材料,純化沉積物之 形成速率超出純化沉積物之移除率。例如,這提供高蚀刻 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 選擇率至少約3: k㈣選擇性比,於以至少約彻 奈米每分之高關率岭介電層,典型係由約__9〇〇奈 米每分,以降低之㈣率微裝載。m包—下層材料在 介電層下時,例如氮切或碳化發時,氟碳/碳:氧之體積 流量比可以調整’以增加用於材料之特定組合之蚀刻選擇 性比,例…刻介電層至光阻,擴散阻障屠或反反射屠 第30頁
70 70 0〇 經濟部智慧財產局員工消费合作社印製 3 7 4 A7 B7 五、發明說明( 之蚀刻選擇性。氟碳/含碳:氧氣體之體積流量比可以被調 整,使得蝕刻特性之側壁具有平滑表面,以相對於基材上 之介電層纟面形成至少約87。之角度。體#流量比可以在 不脫離本發明之範圍下被調整,用於材料之不同組合,及 特性幾何,例如特性深寬比,以完成特定蝕刻選擇性,蝕 刻率微裝載,或蝕刻率。 較佳地,惰性氣體可以加入處理氣體中,以形成離子 化賤擊物種,其可以被濺離在剛蝕刻特性侧壁上之鈍化沉 積物°惰性氣體同時也離子化以形成離子化介穩態,這加 強了處理氣體之溶解。因此,吾人也想要令惰性氣體具有 大範圍之激勵能量,使得提升處理氣體溶解之能量轉移反 應可以發生於激勵惰性氣體及處理氣體之間。適當惰性氣 體包含氬,氦,氖,氙及氪,其中氬係較佳的《足夠惰性 氣體被加入至處理氣體中,以協助將鈍化沉積濺離基材, 並加強處理氣體之溶解。然而,惰性氣體之過量流動造成 光阻過量漱擊於基材上,造成光阻斜面,蚀刻在光阻下之 介電層,及高分佈微裝載。 適用以蝕刻含碳氧化矽層之處理氣體的較佳組成包 含有氬,CO及一或多數由CF4,C2F6,及C4F8選出氣體 之混合。對於此所述之處理室之體積,(i)CF4之適當流速 係由約0至約80sccm,最佳係由約20至60sccm,(ii)C4Fs 之適當流速係由約〇至約40sccm ’最好是由約5至約 3 0sccm,(iii)CO之適當流係由約〇至200sccm,最佳係由 約20至約1 5Osccm,及(iv)氬之適當流率係由約40至約 第31頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ! — 1!1>1----— — II — — ! — — — (請先閲讀背面之注意事項再填寫本頁) 473S70 A7 B7 經濟部智慧財產局員工消费合作社印製 五、發明說明( 4〇Osccm,最好是由約1〇〇至約300sccme因為實際流量係 取決於室1 4 0之體積,所以本發明並不限定於此所述之流 量。 於較佳介電層中之垂直内連線之蝕刻於一 8吋基材 上’該ϋ刻耽體較佳包含由約l〇sccrn至約8〇sccm之一或 多數氟碳氣體及由約100seem至約200sccm之竣··氧氣 體。於蚀刻垂直内連線時,氟碳氣體之混合較佳係使得鈍 化沉積物可以除了改變氟碳氣體及碳:氧氣體之相對量 外’也可藉由改變特定氟碳氣體之相對量加以控制。一較 佳載氣係由約lOOseem至約300sccm之氯。 於較佳介電層中之水平内連線之蝕刻於一 8吋基材 上’該蝕刻氣體較佳包含由約5sccm至約80sccm之一或 多數氟碳氣體及由少於5sccm之碳:氧氣體。於蝕刻水平 内連線時’氟碳氣體之混合可以用以控制鈍化,雖然,鈍 .化沉積可以藉由調整氟碳氣體之流量加以控制。一較佳載 氣係由約lOOseem至約300sccm之氬。 本發明之蝕刻處理提供非選擇性或選擇性含碳蝕刻 介電層,而不必犧牲蝕刻率微裝載及介電蝕刻率。藉由蝕 刻選擇性比率,表示介電層之蝕刻率對其他材料相琳層之 蚀刻率之比率’其他材料包含下層反反射層,擴散阻障 層’氮化矽或碳化矽,及上層光阻層。高蝕刻率,低微裝 載及高蝕刻選擇性之組合係藉由平衡來自基诗之鈍化物 種之沉積及移除比率,以及,藉由控制含氟物種之數量加 以取得,該物種係可由蝕刻介電層取得。雖然過量鈍化沉 第32頁 -----------:---^ 裝--- (請先閱讀背面之注意事項再填寫本頁) 15J. 473SV0 A7 B7 34 seem 3 60 seem 2000 seem 五、發明說明( 積降低了整體介電蝕刻率,並增加了蝕刻率微裝載,聚合 物之沉積或形成之抑制典型降低蝕刻選擇性。 本發明將藉由以下例子加以說明,這些例子並不是用 以限定本案之範圍。 例子1 一第一氧化甲基矽烷層係沉積於8吋矽基材上,該基 材放置於一 DxZ室,該室係由應用材料所購得,並以3.0 托耳之室壓,及由反應氣體之1 5 °C之溫度,反應氣體係以 下流入反應器中: 甲基矽烷CH3-SiH3於 一氧化二氮,N20於 氦,He於 基材係被放置於離開配氣噴頭320密耳,及高頻RF 功率(1 3MHz)係應用至嘴氣頭,用於電漿加強沉積一第一 氧化甲基矽烷層,該層含約5原子量%碳及約〇·3原子量% 氩,第一層具有至少5 000埤之厚度。然後,甲基矽烷之 流量係增加至68seem及一含約1〇·5原子量%C及約3原 子量%氫之第二氧化甲基矽烷層係以80瓦之功率位準加 以沉積,該第二層具有至少1〇0埃之厚度。然後,甲基矽 烷之流量係被減少至34sccm及含約5原子量碳及0.3原 子量°/〇之氫的第三氧化甲基矽烷層係沉積於一 300瓦之功 第33頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) ------------/ -裝--------訂---------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 473S70 A7 B7 20sccm 40sccm 1 50sccm 250sccm 刻室之陰極托架上 五、發明說明() 率位準,該層具有至少5000埃之厚度。所沉積之介電層 然後固化# 40Gt,以去除剩餘濕氣,並且基材係被傳送 用於蝕刻一雙層鑲嵌結構。 於傳統微影處理中,一光阻,例如由杜邦化學公司所 製造之"RIST〇N”係施加至第三氧化甲基矽烷層上至約〇4 至約1 · 3微米厚,及予以蝕刻於介電層中之導孔係藉由將 光阻曝露至一經由光罩之圖案光而加以定義,該光罩係相 當於想要特性之架構。於光阻之未曝光部份下之介電層係 被蝕刻於IPS ETCH室中,該室係可由應用材料購得,使 用以下量之處理氣體: C4F 8 於 CF4於 CO於 氬,Ar於 作出圖案之基材係被放置於蝕 — _ 至k被維持於約3 0耄托耳之壓力。一電漿係藉由施加 RF電壓至雙螺旋管線圈,以約2〇〇〇瓦之功率位準加以 生。一 1000瓦之偏壓功率係施加至陰極托架上。基材 冷卻或加熱至-10t,使用背側氦流量,以維持一鈍化 積薄層於剛蝕刻特性之側壁上。蝕刻處理係被執行足夠 間,以蝕刻於第三氧化甲基矽烷層之導孔。然後,以 毫托耳蝕刻貫穿第二氧化甲基矽烷層,以以下氣體流 行: 第34頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -------1--- I I I、裝--------訂----------資 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 473870 A7 B7 發明說明() C4F8 於 Osccm CF4於 60sccm CO於 1 50sccm 氬,Ar於 250sccm 蝕刻處理係執行一足夠時間, 以蝕刻穿過第 二氧化甲 基矽烷層。然後,以30毫托耳蚀刻貫穿第一氧化甲基矽 烷層,以以下氣體流進行: c4f8 於 20sccm CF4於 40sccm CO於 1 50sccm 氬,Ar於 250sccm 蝕刻處理係執行一足夠時間, 以蝕刻穿過第 一氧化甲 基矽烷層。然後,以以下流量之改變執行過蝕刻: <請先閱讀背面之注意事項再填寫本頁) -裝 訂- C4F8 於 20sccm CF4於 40sccm CO於 1 OOsccm ' 氬,Ar於 250sccm 過蚀刻處理係執行於一雙螺線管 1600之功率位準及 經濟部智慧財產局員工消費合作社印製 1000瓦之陰極托架功率位準,一足夠時間,以完成經第一 氧化甲基矽烷層之所有導孔。 蚀刻晶圓之SEM圖係用以量測⑴介電層蝕刻率,…) 第35頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 經濟部智慧財產局員工消費合作社印製 473S70 A7 五、發明說明() 介電層蝕刻對光阻蝕刻之蝕刻選擇性率,(iii)蝕刻率均勻 性,及(iv)%蝕刻率微裝載。如下之導孔蝕刻步騾結果顯 示。蚀刻率係藉由量測於基材中之蚀刻特性之深度加以計 算。蝕刻選擇性率係由介電層20之独刻率對光阻層之蝕 刻率之比率加以計算。蝕刻均勻性係使用至少15不同量 測點加以計算。%蝕刻率微裝載係當具有不同大小蝕刻特 性於基材上時’蚀刻率差之量測。於以下例子中,百分比 蝕刻率微裝載係量測用於約0.5微米直徑之大孔,及约 0.25微米直徑之小孔,蝕刻率係被平均基材之中心及週邊 緣。 然後,舊光阻係以氧電漿剥離,及一光阻係再施加並 作出圖案,以定義例如溝渠之水平内連線。於IPS蝕刻室 中,使用以7毫托耳室壓,以以下處理氣體量,於光阻未 曝露部份下之介電層係選擇地蝕刻向下至蚀刻阻擔層: C4F8 於 19sccm CF4 於 Osccm CO 於 Osccm 氬,Ar 於 lOOsccm , 電漿係藉由施加RF電壓至雙螺線管線圈加以產生, 螺線管具有約1400瓦之功率位準。陰極托架功率位準係 被設定於1 500瓦。基材係被冷卻或加熱至+1(rc,使用背 側氦氣流,以維持一薄廣純化沉積物於剛蚀刻特性之側壁 第36頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) — — — — — — — — — — — I ·1111111 ---II---- ^ (請先閱讀背面之注意事項存填寫本頁) 473S70
五、發明說明( 上蚀刻處理係被執行一足夠時 律 ^ f間,以蝕刻所有經由第- 軋化甲基矽烷層之溝渠。 弟一 或者,溝渠之蝕刻可以較高 ^ 阿餐,例如20毫托耳開妒, 藉由增加氣體流約5〇% 增加至螺線管線圈之功率% 1000瓦’然後,蝕刻條件可以 牛4 * i改變至一較低壓,例如7 笔托耳,用以較少蝕刻溝渠 - 浑果以確保停止於第二氧化甲基 矽烷層上。 I 触刻晶圓之SEM圖係再汝田、,田 圃丹入用以量測蝕刻效能,用於 每一蚀刻步驟之結果係被示如下。 一_效能
選擇性 3.5 : 3.5 : 1.2 : 1 均句性 微裝載 ±10% ±5% 10% ±10% ±5% 10% :5% 15% — — III — — — — — — — · »111111— ^ « — III — — —— ^ f請先閱讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 例子2 如述例子藉由改變矽化合物之流量及功率位準,沉積 介電層於單一室中。這例子修改第一例子,以TEOS替代 甲基矽烷,作為第一介電層。 一第一氧化TEOS層係沉積於8吋矽基材上,該基材 放置於一 DxZ室,該室係由應用材料所購得,並以3·〇托 耳之室壓’及由反應氣體之3 5(TC之溫度,反應氣體係以 第37頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 473370 經濟部智慧財產局員工消費合作社印製 五、發明說明() 下流入反應器中: A7 B7
TEOS,(CH3-CH2-0-)於 40sccm 氧 ’〇2 於 360seem 乱 ’ He 於 2000sccm 基材係被放置於離開配氣噴頭320密耳,及750瓦之 高頻RF功率(13MHz)係應用至噴氣頭,用於電漿加強沉積 一第一氧化甲基矽烷層,該層含約1原子量%碳及少於〇 ^ 原子量%氫,該層具有至少5000埃之厚度。然後,沉積第 二及第三介電層,然後使用甲基矽烷持續進行,如於例子 1所述》 雙層鑲嵌結構之蝕刻係如於例子1所述地執行,除了 用於形成於沉積TEOS層中之垂直内連線之蝕刻條件及垂 直内連線之過蝕刻之蝕刻條件係如下外: C4F8 於 c2F6 於 CO於氬,Ar於 1 5 seem 20sccm Oseem 3 50sccm 於蝕刻下層氧化矽層及過蝕刻垂直内連線時,一電漿 係藉由施加2200瓦之RF電壓至雙螺旋管線圈,及1400 瓦之RF功率位準至偏壓電極加以產生。基材被使用背側 第38頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) -----I---^丨丨裝--------有; {請先閱讀背面之注意事項再填寫本頁) 473S70 A7 _ B7_五、發明說明() 氦流量加以冷卻或加熱至-1 〇 °c,以維持一鈍化沉積薄層 於剛蝕刻特性之側壁上。 雖然前述係有關於本發明之較佳實施例,但本發明之 其他實施例可以在不脫離本發明之基本範圍下加以導 出,本發明之範圍係由以下之申請專利範圍加以決定。 ----------τ---裝--------有---------综 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 第39頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
Claims (1)
- 473S70 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 Π8 _______ _^ -----^ - 六、申請專利範圍 1 · 一種用以沉積及蝕刻金屬層間介電層之方法,該方法至 少包含步驟: 沉積一第一介電層,該層真有少於4·〇之介電常數; 沉積一第二介電層於第/介電層上,該層具有少於 4.0之介電常數;及 以下列條件,蝕刻第二介電層’該條件為第二介電 層具有至少三倍大於第一介電層蚀刻率之蝕刻率。 2 ·如申請專利範圍第1項所述之方法’其中上述之第一介 電層包含矽,氧,至少約5原子量%之碳,及其中上述 之第二介電層包含碎,氧及少於含於第一介電層中之碳 之二分之二的碳。 3·如申請專利範圍第2項所述之方法’其中上述之第一介 電層係以第一氣體混合物被蝕刻’以形成垂直内連線, 該第一氣體混合物包含一或多數氟碳化合物及一或多 數碳:氧化合物,及第二介電層以第二氣體混合物加以 蝕刻,以形成水平内連線,該第二氣體混合物包含一或 多數氟竣化合物及本質上沒有碳:氧化合物。 4·如申請專利範圍第3項所述之方法,其中上述之碳:氧 化合物為一氧化碳。 5.如申請專利範圍第1項所述之方法,其中上述之第一介 -----------> t-----r---^---:------^ <請先閱讀背面之注意事項再填寫本頁) 473870 Α8 Β8 C8 D8 六 申請專利範圍 電層包含矽,氧,至少约1原子量%之碳,及第二介電 層包含矽,氧,碳,及少於含於第一介電層中之氫之五 分之一的氫。 6·如申請專利範圍第5項所述之方法,其中上述之第一介 電層係以第一氣體混合物被蝕刻,以形成垂直内連線, 該第一氣體混合物包含一或多數氟碳化合物及一或多 數碳:氧化合物,及第二介電層以第二氣體混合物加以 蝕刻,以形成水平内連線,該第二氣體混合物包含—或 多數氟碳化合物及本質上沒有碳:氧化合物。 7·如申請專利範圍第6項所述之方法,其中上述之碳:氧 化合物為一氧化碳。 ----------.--, 裝--- (請先閱讀背面之注意事項再填寫本頁> 、訂 經濟部智慧財產局員工消費合作社印製 8.如申請專利範圍第1項所述之方法,其中上述之第一及 第二介電層係以氧化一有機碎化合物加以沉積。 9·如申請專利範圍第8項所述之方法,其中上述之有機今 化合物為甲基矽烷或三甲基矽烷。 10.如申請專利範圍第1項所述之方法,其中上述之第 電層係沉積於第三介電層上,該第三介電層具有 • 4.0之介電常數。 —介 少於 绵 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 473S70 經濟部智慧財產局員工消費合作社印製 六 A8 B8 C8 D8 申請專利範圍 11. 一種沉積金屬層間介電層之雙層鑲嵌方法,其至少包含 下列步驟:. 藉由氧化一第一有機碎化合物,來沉積一第一介電 層,該層具有少於4之介電常數; 藉由氧化一第二有機矽化合物,來沉積一第二介電 層於第一介電層上,該層具有少於4之介電常數; 藉由氧化一第三有機矽化合物,來沉積一第三介電 層於第二介電層上,該第三介電層具有少於4之介電常 數;及 以下列條件,蝕刻該第三介電層,以形成水平内連 線,該條件為第第三介電層具有至少三倍大於第二介電 層蝕刻率之蝕刻率。 12. 如申請專利範圍第11項所述之方法,其中上述之第 一,第二及第三有機矽化合物係相同化合物。 13. 如申請專利範圍第12項所述之方法,其中上述之有機 矽化合物係由包含甲基矽烷及三甲基矽烷之群組中選 出。 14. 如申請專利範圍第12項所述之方法,其中上述之第二 介電層包含矽,氧,至少約5原子量%之碳,及至少1 •原子量%之氫,及其中上述之第一及第三介電層包含 矽,氧及少於含於第二介電層中之碳之三分之二的碳, 第42頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 473370 A8 B8 C8 D8 六、申請專利範圍 及少於含於第二介電層中之氫之五分之一的碳。 1 5 ·如申請專利範圍第1 2項所述之方法,其中上述之第二 介電層係以第一氣體混合物被蚀刻,以形成垂直内連 線,該第一氣體混合物包含一或多數氟碳化合物及一或 多_數碳:氧化合物,該第一氣體混合物包含一總體積 碳:氧化合物大於氟碳化合物之總體積;及第三介電層 以第二氣體混合物加以蝕刻,以形成水平内連線,該第 二氣體混合物包含一或多數氟碳化合物,該第二氣體混 合物包含氟碳化合物之總體積大於碳:氧化合物之總體 積。 1 6.如申請專利範圍第1 5項所述之方法,其中上述之垂直 内連線係以含一氧化碳之氣體蝕刻及水平内連線係實 質不含一氧化碳之氣體蝕刻。 17·—種用以沉積低介電常數層之方法,其至少包含步騾: 改變用以沉積有機矽化合物之一或多數處理條件, 以取得具有變化碎,氧,碳及氫含量及介電常數少& 4 之第一及第二介電層;及 使用以下條件以蝕刻第二介電層,該條件為第二介 電層具有一蝕刻率,該蚀刻年係至少三倍大於第一介電 •層之蚀刻率。 第43頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) • — — 、裝 i I (請先閲讀背面之注意事項再填寫本頁) 訂· --線- 經濟部智慧財產局員工消費合作社印製 473S70 A8 B8 C8 D8 六、申請專利範圍 18.如申請專利範圍第17項所述之方法,其中上述之第一 介電層包含琴少約 5原子量%之碳或至少1原子量% 氫,及其中上述之第二介電層包含少於含於第一氧化矽 層中之碳之三分之二的碳或少於第一氧化矽層中之氫 之五分之一。 1 9.如申請專利範圍第1 8項所述之方法,其中上述之第二 介電層係以第一氣體混合物被蝕刻,以形成水平内連 線,該第一氣體混合物包含一或多數氟碳化合物及本質 上沒有碳:氧化合物。 20.如申請專利範圍第17項所述之方法,更包含沉積第一 介電層於一第三介電層上,該第三介電層具有矽,氧, 碳及氩含量類以於第二介電層者。 ------Λ------i -----r---訂---I----- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 第μ頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/329,012 US6340435B1 (en) | 1998-02-11 | 1999-06-09 | Integrated low K dielectrics and etch stops |
Publications (1)
Publication Number | Publication Date |
---|---|
TW473870B true TW473870B (en) | 2002-01-21 |
Family
ID=23283469
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW089109877A TW473870B (en) | 1999-06-09 | 2000-05-22 | Integrated low K dielectrics and etch stops |
Country Status (5)
Country | Link |
---|---|
US (4) | US6340435B1 (zh) |
EP (1) | EP1059664A3 (zh) |
JP (1) | JP2001110789A (zh) |
KR (1) | KR100661201B1 (zh) |
TW (1) | TW473870B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI399808B (zh) * | 2005-03-25 | 2013-06-21 | Tokyo Electron Ltd | Etching method and etching device |
TWI489549B (zh) * | 2009-04-09 | 2015-06-21 | Lam Res Corp | 可減少損壞之低介電常數介電層蝕刻方法 |
Families Citing this family (378)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6660656B2 (en) | 1998-02-11 | 2003-12-09 | Applied Materials Inc. | Plasma processes for depositing low dielectric constant films |
US6287990B1 (en) | 1998-02-11 | 2001-09-11 | Applied Materials, Inc. | CVD plasma assisted low dielectric constant films |
US6054379A (en) | 1998-02-11 | 2000-04-25 | Applied Materials, Inc. | Method of depositing a low k dielectric with organo silane |
US6593247B1 (en) | 1998-02-11 | 2003-07-15 | Applied Materials, Inc. | Method of depositing low k films using an oxidizing plasma |
US6340435B1 (en) | 1998-02-11 | 2002-01-22 | Applied Materials, Inc. | Integrated low K dielectrics and etch stops |
US6303523B2 (en) | 1998-02-11 | 2001-10-16 | Applied Materials, Inc. | Plasma processes for depositing low dielectric constant films |
WO1999052135A1 (en) * | 1998-04-02 | 1999-10-14 | Applied Materials, Inc. | Method for etching low k dielectrics |
US6680248B2 (en) | 1998-06-01 | 2004-01-20 | United Microelectronics Corporation | Method of forming dual damascene structure |
US6759306B1 (en) | 1998-07-10 | 2004-07-06 | Micron Technology, Inc. | Methods of forming silicon dioxide layers and methods of forming trench isolation regions |
JP2000106397A (ja) * | 1998-07-31 | 2000-04-11 | Sony Corp | 半導体装置における配線構造及びその形成方法 |
US6635583B2 (en) * | 1998-10-01 | 2003-10-21 | Applied Materials, Inc. | Silicon carbide deposition for use as a low-dielectric constant anti-reflective coating |
JP2000174123A (ja) * | 1998-12-09 | 2000-06-23 | Nec Corp | 半導体装置及びその製造方法 |
US6503818B1 (en) * | 1999-04-02 | 2003-01-07 | Taiwan Semiconductor Manufacturing Company | Delamination resistant multi-layer composite dielectric layer employing low dielectric constant dielectric material |
US6821571B2 (en) * | 1999-06-18 | 2004-11-23 | Applied Materials Inc. | Plasma treatment to enhance adhesion and to minimize oxidation of carbon-containing layers |
WO2000079586A1 (fr) * | 1999-06-24 | 2000-12-28 | Hitachi, Ltd. | Procede de production de dispositif a circuit integre semi-conducteur et dispositif a circuit integre semi-conducteur |
US6251770B1 (en) * | 1999-06-30 | 2001-06-26 | Lam Research Corp. | Dual-damascene dielectric structures and methods for making the same |
US6727588B1 (en) * | 1999-08-19 | 2004-04-27 | Agere Systems Inc. | Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics |
TW455948B (en) * | 1999-09-13 | 2001-09-21 | Motorola Inc | Process for etching an insulating layer and forming a semiconductor device |
US6593653B2 (en) * | 1999-09-30 | 2003-07-15 | Novellus Systems, Inc. | Low leakage current silicon carbonitride prepared using methane, ammonia and silane for copper diffusion barrier, etchstop and passivation applications |
US6156743A (en) * | 1999-10-18 | 2000-12-05 | Whitcomb; John E. | Method of decreasing fatigue |
JP4381526B2 (ja) * | 1999-10-26 | 2009-12-09 | 東京エレクトロン株式会社 | プラズマエッチング方法 |
GB0001179D0 (en) * | 2000-01-19 | 2000-03-08 | Trikon Holdings Ltd | Methods & apparatus for forming a film on a substrate |
GB2398168B (en) * | 2000-01-19 | 2004-09-15 | Trikon Holdings Ltd | Methods and apparatus for forming a film on a substrate |
WO2001084626A1 (en) * | 2000-04-28 | 2001-11-08 | Tokyo Electron Limited | Semiconductor device having a low dielectric film and fabrication process thereof |
US6562189B1 (en) * | 2000-05-19 | 2003-05-13 | Applied Materials Inc. | Plasma reactor with a tri-magnet plasma confinement apparatus |
KR100326317B1 (ko) * | 2000-07-06 | 2002-03-08 | 윤종용 | 실리카 미세 구조물의 제작 방법 |
US6607675B1 (en) * | 2000-08-29 | 2003-08-19 | Applied Materials Inc. | Method of etching carbon-containing silicon oxide films |
US6762132B1 (en) | 2000-08-31 | 2004-07-13 | Micron Technology, Inc. | Compositions for dissolution of low-K dielectric films, and methods of use |
US6465366B1 (en) * | 2000-09-12 | 2002-10-15 | Applied Materials, Inc. | Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers |
US6531398B1 (en) | 2000-10-30 | 2003-03-11 | Applied Materials, Inc. | Method of depositing organosillicate layers |
TW479315B (en) * | 2000-10-31 | 2002-03-11 | Applied Materials Inc | Continuous depostiton process |
US6753258B1 (en) * | 2000-11-03 | 2004-06-22 | Applied Materials Inc. | Integration scheme for dual damascene structure |
US6737727B2 (en) * | 2001-01-12 | 2004-05-18 | International Business Machines Corporation | Electronic structures with reduced capacitance |
US6893969B2 (en) * | 2001-02-12 | 2005-05-17 | Lam Research Corporation | Use of ammonia for etching organic low-k dielectrics |
US6537733B2 (en) * | 2001-02-23 | 2003-03-25 | Applied Materials, Inc. | Method of depositing low dielectric constant silicon carbide layers |
US6603204B2 (en) * | 2001-02-28 | 2003-08-05 | International Business Machines Corporation | Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics |
US6710450B2 (en) * | 2001-02-28 | 2004-03-23 | International Business Machines Corporation | Interconnect structure with precise conductor resistance and method to form same |
US7781327B1 (en) | 2001-03-13 | 2010-08-24 | Novellus Systems, Inc. | Resputtering process for eliminating dielectric damage |
US8043484B1 (en) | 2001-03-13 | 2011-10-25 | Novellus Systems, Inc. | Methods and apparatus for resputtering process that improves barrier coverage |
US6764940B1 (en) | 2001-03-13 | 2004-07-20 | Novellus Systems, Inc. | Method for depositing a diffusion barrier for copper interconnect applications |
US7186648B1 (en) | 2001-03-13 | 2007-03-06 | Novellus Systems, Inc. | Barrier first method for single damascene trench applications |
US6896968B2 (en) * | 2001-04-06 | 2005-05-24 | Honeywell International Inc. | Coatings and method for protecting carbon-containing components from oxidation |
US6486059B2 (en) * | 2001-04-19 | 2002-11-26 | Silicon Intergrated Systems Corp. | Dual damascene process using an oxide liner for a dielectric barrier layer |
US6879046B2 (en) * | 2001-06-28 | 2005-04-12 | Agere Systems Inc. | Split barrier layer including nitrogen-containing portion and oxygen-containing portion |
US6410426B1 (en) * | 2001-07-09 | 2002-06-25 | Texas Instruments Incorporated | Damascene cap layer process for integrated circuit interconnects |
US20030008490A1 (en) * | 2001-07-09 | 2003-01-09 | Guoqiang Xing | Dual hardmask process for the formation of copper/low-k interconnects |
GB0117600D0 (en) * | 2001-07-19 | 2001-09-12 | Trikon Holdings Ltd | Semiconductor structure |
US6570256B2 (en) * | 2001-07-20 | 2003-05-27 | International Business Machines Corporation | Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates |
US6727183B1 (en) * | 2001-07-27 | 2004-04-27 | Taiwan Semiconductor Manufacturing Company | Prevention of spiking in ultra low dielectric constant material |
US20030027413A1 (en) * | 2001-08-01 | 2003-02-06 | Ting Tsui | Method to improve the adhesion of dielectric layers to copper |
US20030027427A1 (en) * | 2001-08-06 | 2003-02-06 | Applied Materials, Inc. | Integrated system for oxide etching and metal liner deposition |
US6762127B2 (en) * | 2001-08-23 | 2004-07-13 | Yves Pierre Boiteux | Etch process for dielectric materials comprising oxidized organo silane materials |
US7067440B1 (en) | 2001-08-24 | 2006-06-27 | Novellus Systems, Inc. | Gap fill for high aspect ratio structures |
US6914004B2 (en) * | 2001-09-28 | 2005-07-05 | Texas Instruments Incorporated | Method for via etching in organo-silica-glass |
US6864180B2 (en) * | 2001-10-02 | 2005-03-08 | International Business Machines Corporation | Method for reworking low-k polymers used in semiconductor structures |
US6759327B2 (en) | 2001-10-09 | 2004-07-06 | Applied Materials Inc. | Method of depositing low k barrier layers |
US7303995B2 (en) * | 2001-10-18 | 2007-12-04 | Macronix International Co., Ltd. | Method for reducing dimensions between patterns on a photoresist |
US6905968B2 (en) * | 2001-12-12 | 2005-06-14 | Applied Materials, Inc. | Process for selectively etching dielectric layers |
US6838393B2 (en) * | 2001-12-14 | 2005-01-04 | Applied Materials, Inc. | Method for producing semiconductor including forming a layer containing at least silicon carbide and forming a second layer containing at least silicon oxygen carbide |
US7091137B2 (en) * | 2001-12-14 | 2006-08-15 | Applied Materials | Bi-layer approach for a hermetic low dielectric constant layer for barrier applications |
US6699784B2 (en) | 2001-12-14 | 2004-03-02 | Applied Materials Inc. | Method for depositing a low k dielectric film (K>3.5) for hard mask application |
US6890850B2 (en) * | 2001-12-14 | 2005-05-10 | Applied Materials, Inc. | Method of depositing dielectric materials in damascene applications |
US6797628B2 (en) * | 2002-01-16 | 2004-09-28 | Micron Technology, Inc. | Methods of forming integrated circuitry, semiconductor processing methods, and processing method of forming MRAM circuitry |
US20030183905A1 (en) * | 2002-02-14 | 2003-10-02 | Fujitsu Limited | Interconnection structure and interconnection structure formation method |
US20030181034A1 (en) * | 2002-03-19 | 2003-09-25 | Ping Jiang | Methods for forming vias and trenches with controlled SiC etch rate and selectivity |
US7390755B1 (en) | 2002-03-26 | 2008-06-24 | Novellus Systems, Inc. | Methods for post etch cleans |
US20030194496A1 (en) * | 2002-04-11 | 2003-10-16 | Applied Materials, Inc. | Methods for depositing dielectric material |
US20030206337A1 (en) * | 2002-05-06 | 2003-11-06 | Eastman Kodak Company | Exposure apparatus for irradiating a sensitized substrate |
US7008484B2 (en) * | 2002-05-06 | 2006-03-07 | Applied Materials Inc. | Method and apparatus for deposition of low dielectric constant materials |
US6686293B2 (en) | 2002-05-10 | 2004-02-03 | Applied Materials, Inc | Method of etching a trench in a silicon-containing dielectric material |
US20040002210A1 (en) * | 2002-06-28 | 2004-01-01 | Goldberg Cindy K. | Interconnect structure and method for forming |
US6927178B2 (en) * | 2002-07-11 | 2005-08-09 | Applied Materials, Inc. | Nitrogen-free dielectric anti-reflective coating and hardmask |
US7105460B2 (en) * | 2002-07-11 | 2006-09-12 | Applied Materials | Nitrogen-free dielectric anti-reflective coating and hardmask |
US20070158178A1 (en) * | 2002-07-23 | 2007-07-12 | Tosoh Smd, Inc. | Method and apparatus for deposition of low-k dielectric materials |
AU2003282533A1 (en) * | 2002-08-08 | 2004-02-25 | Trikon Technologies Limited | Improvements to showerheads |
DE10240099A1 (de) * | 2002-08-30 | 2004-03-11 | Infineon Technologies Ag | Herstellungsverfahren für eine Halbleiterstruktur |
DE10240176A1 (de) * | 2002-08-30 | 2004-04-29 | Advanced Micro Devices, Inc., Sunnyvale | Ein dielektrischer Schichtstapel mit kleiner Dielektrizitätskonstante einschliesslich einer Ätzindikatorschicht zur Anwendung in der dualen Damaszenertechnik |
US6946033B2 (en) * | 2002-09-16 | 2005-09-20 | Applied Materials Inc. | Heated gas distribution plate for a processing chamber |
US20040052969A1 (en) * | 2002-09-16 | 2004-03-18 | Applied Materials, Inc. | Methods for operating a chemical vapor deposition chamber using a heated gas distribution plate |
US7141483B2 (en) * | 2002-09-19 | 2006-11-28 | Applied Materials, Inc. | Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill |
US20070212850A1 (en) * | 2002-09-19 | 2007-09-13 | Applied Materials, Inc. | Gap-fill depositions in the formation of silicon containing dielectric materials |
US7335609B2 (en) * | 2004-08-27 | 2008-02-26 | Applied Materials, Inc. | Gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials |
US7431967B2 (en) | 2002-09-19 | 2008-10-07 | Applied Materials, Inc. | Limited thermal budget formation of PMD layers |
US7456116B2 (en) * | 2002-09-19 | 2008-11-25 | Applied Materials, Inc. | Gap-fill depositions in the formation of silicon containing dielectric materials |
US6905940B2 (en) * | 2002-09-19 | 2005-06-14 | Applied Materials, Inc. | Method using TEOS ramp-up during TEOS/ozone CVD for improved gap-fill |
KR100441685B1 (ko) * | 2002-09-19 | 2004-07-27 | 삼성전자주식회사 | 듀얼 다마신 공정 |
US7781850B2 (en) * | 2002-09-20 | 2010-08-24 | Qualcomm Mems Technologies, Inc. | Controlling electromechanical behavior of structures within a microelectromechanical systems device |
JP2004274020A (ja) * | 2002-09-24 | 2004-09-30 | Rohm & Haas Electronic Materials Llc | 電子デバイス製造 |
KR100458594B1 (ko) * | 2002-10-02 | 2004-12-03 | 아남반도체 주식회사 | 반도체 소자 제조 방법 |
US7749563B2 (en) * | 2002-10-07 | 2010-07-06 | Applied Materials, Inc. | Two-layer film for next generation damascene barrier application with good oxidation resistance |
JP4606713B2 (ja) * | 2002-10-17 | 2011-01-05 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
CN100352036C (zh) * | 2002-10-17 | 2007-11-28 | 株式会社瑞萨科技 | 半导体器件及其制造方法 |
US7071112B2 (en) * | 2002-10-21 | 2006-07-04 | Applied Materials, Inc. | BARC shaping for improved fabrication of dual damascene integrated circuit features |
JP4109531B2 (ja) * | 2002-10-25 | 2008-07-02 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
US6815332B2 (en) * | 2002-10-30 | 2004-11-09 | Asm Japan K.K. | Method for forming integrated dielectric layers |
US7109119B2 (en) * | 2002-10-31 | 2006-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scum solution for chemically amplified resist patterning in cu/low k dual damascene |
DE10250889B4 (de) * | 2002-10-31 | 2006-12-07 | Advanced Micro Devices, Inc., Sunnyvale | Verbesserte SiC-Barrierenschicht für eine Kupfermetallisierungsschicht mit einem Dielektrikum mit kleinem ε und Verfahren zur Herstellung derselben |
US7214609B2 (en) * | 2002-12-05 | 2007-05-08 | Texas Instruments Incorporated | Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities |
US7122485B1 (en) * | 2002-12-09 | 2006-10-17 | Novellus Systems, Inc. | Deposition profile modification through process chemistry |
KR100587600B1 (ko) * | 2002-12-10 | 2006-06-08 | 매그나칩 반도체 유한회사 | 듀얼 다마신 공정을 이용한 금속배선 형성방법 |
KR100465057B1 (ko) * | 2002-12-23 | 2005-01-05 | 매그나칩 반도체 유한회사 | 반도체 소자의 듀얼 다마신 패턴 형성 방법 |
US7270713B2 (en) * | 2003-01-07 | 2007-09-18 | Applied Materials, Inc. | Tunable gas distribution plate assembly |
JP4028393B2 (ja) * | 2003-01-09 | 2007-12-26 | 株式会社東芝 | 半導体装置およびその製造方法 |
US6790788B2 (en) * | 2003-01-13 | 2004-09-14 | Applied Materials Inc. | Method of improving stability in low k barrier layers |
JP4651076B2 (ja) * | 2003-01-24 | 2011-03-16 | 日本エー・エス・エム株式会社 | 半導体基板上の絶縁膜の形成方法 |
JP4746829B2 (ja) * | 2003-01-31 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2004235548A (ja) * | 2003-01-31 | 2004-08-19 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP2004241675A (ja) * | 2003-02-07 | 2004-08-26 | Renesas Technology Corp | 配線接続構造を有する電子デバイスの製造方法 |
US7238393B2 (en) * | 2003-02-13 | 2007-07-03 | Asm Japan K.K. | Method of forming silicon carbide films |
US7011890B2 (en) * | 2003-03-03 | 2006-03-14 | Applied Materials Inc. | Modulated/composited CVD low-k films with improved mechanical and electrical properties for nanoelectronic devices |
US7176122B2 (en) * | 2003-03-04 | 2007-02-13 | Intel Corporation | Dielectric with sidewall passivating layer |
US6913992B2 (en) * | 2003-03-07 | 2005-07-05 | Applied Materials, Inc. | Method of modifying interlayer adhesion |
JP4454242B2 (ja) | 2003-03-25 | 2010-04-21 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
US20040192058A1 (en) * | 2003-03-28 | 2004-09-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Pre-etching plasma treatment to form dual damascene with improved profile |
US8298933B2 (en) | 2003-04-11 | 2012-10-30 | Novellus Systems, Inc. | Conformal films on semiconductor substrates |
US7842605B1 (en) | 2003-04-11 | 2010-11-30 | Novellus Systems, Inc. | Atomic layer profiling of diffusion barrier and metal seed layers |
US6942753B2 (en) | 2003-04-16 | 2005-09-13 | Applied Materials, Inc. | Gas distribution plate assembly for large area plasma enhanced chemical vapor deposition |
US6753269B1 (en) * | 2003-05-08 | 2004-06-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for low k dielectric deposition |
US20040224524A1 (en) * | 2003-05-09 | 2004-11-11 | Applied Materials, Inc. | Maintaining the dimensions of features being etched on a lithographic mask |
US7256134B2 (en) | 2003-08-01 | 2007-08-14 | Applied Materials, Inc. | Selective etching of carbon-doped low-k dielectrics |
US7067437B2 (en) * | 2003-09-12 | 2006-06-27 | International Business Machines Corporation | Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same |
US6949460B2 (en) * | 2003-11-12 | 2005-09-27 | Lam Research Corporation | Line edge roughness reduction for trench etch |
US7476621B1 (en) | 2003-12-10 | 2009-01-13 | Novellus Systems, Inc. | Halogen-free noble gas assisted H2 plasma etch process in deposition-etch-deposition gap fill |
US7344996B1 (en) | 2005-06-22 | 2008-03-18 | Novellus Systems, Inc. | Helium-based etch process in deposition-etch-deposition gap fill |
JP4917249B2 (ja) * | 2004-02-03 | 2012-04-18 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
SG120976A1 (en) * | 2004-02-11 | 2006-04-26 | Taiwan Semiconductor Mfg | Method for forming openings in low-k dielectric layers |
US20060051966A1 (en) * | 2004-02-26 | 2006-03-09 | Applied Materials, Inc. | In-situ chamber clean process to remove by-product deposits from chemical vapor etch chamber |
US20050230350A1 (en) | 2004-02-26 | 2005-10-20 | Applied Materials, Inc. | In-situ dry clean chamber for front end of line fabrication |
US7030041B2 (en) * | 2004-03-15 | 2006-04-18 | Applied Materials Inc. | Adhesion improvement for low k dielectrics |
US20050214457A1 (en) * | 2004-03-29 | 2005-09-29 | Applied Materials, Inc. | Deposition of low dielectric constant films by N2O addition |
US7015133B2 (en) * | 2004-04-14 | 2006-03-21 | Taiwan Semiconductor Manufacturing Company | Dual damascene structure formed of low-k dielectric materials |
US20050233555A1 (en) * | 2004-04-19 | 2005-10-20 | Nagarajan Rajagopalan | Adhesion improvement for low k dielectrics to conductive materials |
US7229911B2 (en) * | 2004-04-19 | 2007-06-12 | Applied Materials, Inc. | Adhesion improvement for low k dielectrics to conductive materials |
US7528051B2 (en) * | 2004-05-14 | 2009-05-05 | Applied Materials, Inc. | Method of inducing stresses in the channel region of a transistor |
US20050263901A1 (en) * | 2004-05-27 | 2005-12-01 | International Business Machines Corporation | Semiconductor device formed by in-situ modification of dielectric layer and related methods |
US20050277302A1 (en) * | 2004-05-28 | 2005-12-15 | Nguyen Son V | Advanced low dielectric constant barrier layers |
US7229041B2 (en) * | 2004-06-30 | 2007-06-12 | Ohio Central Steel Company | Lifting lid crusher |
US7473644B2 (en) * | 2004-07-01 | 2009-01-06 | Micron Technology, Inc. | Method for forming controlled geometry hardmasks including subresolution elements |
US7288205B2 (en) * | 2004-07-09 | 2007-10-30 | Applied Materials, Inc. | Hermetic low dielectric constant layer for barrier applications |
US7288484B1 (en) | 2004-07-13 | 2007-10-30 | Novellus Systems, Inc. | Photoresist strip method for low-k dielectrics |
KR101354520B1 (ko) * | 2004-07-29 | 2014-01-21 | 퀄컴 엠이엠에스 테크놀로지스, 인크. | 간섭 변조기의 미소기전 동작을 위한 시스템 및 방법 |
US20060021703A1 (en) * | 2004-07-29 | 2006-02-02 | Applied Materials, Inc. | Dual gas faceplate for a showerhead in a semiconductor wafer processing system |
US7642171B2 (en) * | 2004-08-04 | 2010-01-05 | Applied Materials, Inc. | Multi-step anneal of thin films for film densification and improved gap-fill |
US20070212847A1 (en) * | 2004-08-04 | 2007-09-13 | Applied Materials, Inc. | Multi-step anneal of thin films for film densification and improved gap-fill |
US7217658B1 (en) | 2004-09-07 | 2007-05-15 | Novellus Systems, Inc. | Process modulation to prevent structure erosion during gap fill |
US7176039B1 (en) | 2004-09-21 | 2007-02-13 | Novellus Systems, Inc. | Dynamic modification of gap fill process characteristics |
US7327510B2 (en) * | 2004-09-27 | 2008-02-05 | Idc, Llc | Process for modifying offset voltage characteristics of an interferometric modulator |
US7373026B2 (en) * | 2004-09-27 | 2008-05-13 | Idc, Llc | MEMS device fabricated on a pre-patterned substrate |
US7369296B2 (en) * | 2004-09-27 | 2008-05-06 | Idc, Llc | Device and method for modifying actuation voltage thresholds of a deformable membrane in an interferometric modulator |
JP4316469B2 (ja) * | 2004-10-15 | 2009-08-19 | 株式会社東芝 | 自動設計装置 |
US7381451B1 (en) | 2004-11-17 | 2008-06-03 | Novellus Systems, Inc. | Strain engineering—HDP thin film with tensile stress for FEOL and other applications |
US7253116B2 (en) * | 2004-11-18 | 2007-08-07 | International Business Machines Corporation | High ion energy and reative species partial pressure plasma ash process |
KR100668831B1 (ko) * | 2004-11-19 | 2007-01-16 | 주식회사 하이닉스반도체 | 반도체 소자의 랜딩 플러그 폴리 형성방법 |
US7202176B1 (en) * | 2004-12-13 | 2007-04-10 | Novellus Systems, Inc. | Enhanced stripping of low-k films using downstream gas mixing |
US8193096B2 (en) | 2004-12-13 | 2012-06-05 | Novellus Systems, Inc. | High dose implantation strip (HDIS) in H2 base chemistry |
US7253123B2 (en) * | 2005-01-10 | 2007-08-07 | Applied Materials, Inc. | Method for producing gate stack sidewall spacers |
US7259111B2 (en) * | 2005-01-19 | 2007-08-21 | Applied Materials, Inc. | Interface engineering to improve adhesion between low k stacks |
US20060166491A1 (en) * | 2005-01-21 | 2006-07-27 | Kensaku Ida | Dual damascene interconnection having low k layer and cap layer formed in a common PECVD process |
DE102005004409B4 (de) * | 2005-01-31 | 2011-01-20 | Advanced Micro Devices, Inc., Sunnyvale | Technik zur Erhöhung der Prozessflexibilität während der Herstellung von Kontaktdurchführungen und Gräben in Zwischenschichtdielektrika mit kleinem ε |
TW200628877A (en) * | 2005-02-04 | 2006-08-16 | Prime View Int Co Ltd | Method of manufacturing optical interference type color display |
US7309653B2 (en) * | 2005-02-24 | 2007-12-18 | International Business Machines Corporation | Method of forming damascene filament wires and the structure so formed |
US7211525B1 (en) | 2005-03-16 | 2007-05-01 | Novellus Systems, Inc. | Hydrogen treatment enhanced gap fill |
JP4927343B2 (ja) * | 2005-03-18 | 2012-05-09 | ルネサスエレクトロニクス株式会社 | 半導体チップおよびその製造方法 |
US8598044B2 (en) * | 2005-03-25 | 2013-12-03 | Renesas Electronics Corporation | Method of fabricating a semiconductor device |
US7972441B2 (en) | 2005-04-05 | 2011-07-05 | Applied Materials, Inc. | Thermal oxidation of silicon using ozone |
US7332425B2 (en) * | 2005-05-11 | 2008-02-19 | Texas Instruments Incorporated | Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnects |
US7396755B2 (en) * | 2005-05-11 | 2008-07-08 | Texas Instruments Incorporated | Process and integration scheme for a high sidewall coverage ultra-thin metal seed layer |
US8129281B1 (en) | 2005-05-12 | 2012-03-06 | Novellus Systems, Inc. | Plasma based photoresist removal system for cleaning post ash residue |
EP2495212A3 (en) * | 2005-07-22 | 2012-10-31 | QUALCOMM MEMS Technologies, Inc. | Mems devices having support structures and methods of fabricating the same |
US7915735B2 (en) * | 2005-08-05 | 2011-03-29 | Micron Technology, Inc. | Selective metal deposition over dielectric layers |
US7341941B2 (en) * | 2005-08-19 | 2008-03-11 | Texas Instruments Incorporated | Methods to facilitate etch uniformity and selectivity |
US7394154B2 (en) * | 2005-09-13 | 2008-07-01 | International Business Machines Corporation | Embedded barrier for dielectric encapsulation |
JP2009509786A (ja) | 2005-09-30 | 2009-03-12 | クォルコム・メムズ・テクノロジーズ・インコーポレーテッド | Mems装置及びmems装置における相互接続 |
US7432189B2 (en) * | 2005-11-30 | 2008-10-07 | Lam Research Corporation | Device with self aligned gaps for capacitance reduction |
US7390749B2 (en) * | 2005-11-30 | 2008-06-24 | Lam Research Corporation | Self-aligned pitch reduction |
US7485581B2 (en) | 2005-11-30 | 2009-02-03 | Lam Research Corporation | Device with gaps for capacitance reduction |
US7560388B2 (en) * | 2005-11-30 | 2009-07-14 | Lam Research Corporation | Self-aligned pitch reduction |
US7652814B2 (en) | 2006-01-27 | 2010-01-26 | Qualcomm Mems Technologies, Inc. | MEMS device with integrated optical element |
JP4788415B2 (ja) | 2006-03-15 | 2011-10-05 | ソニー株式会社 | 半導体装置の製造方法 |
US20070238254A1 (en) * | 2006-03-28 | 2007-10-11 | Applied Materials, Inc. | Method of etching low dielectric constant films |
US7643203B2 (en) * | 2006-04-10 | 2010-01-05 | Qualcomm Mems Technologies, Inc. | Interferometric optical display system with broadband characteristics |
US7369292B2 (en) * | 2006-05-03 | 2008-05-06 | Qualcomm Mems Technologies, Inc. | Electrode and interconnect materials for MEMS devices |
US20070264843A1 (en) * | 2006-05-09 | 2007-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation and applications of nitrogen-free silicon carbide in semiconductor manufacturing |
US7482245B1 (en) | 2006-06-20 | 2009-01-27 | Novellus Systems, Inc. | Stress profile modulation in STI gap fill |
US7645696B1 (en) * | 2006-06-22 | 2010-01-12 | Novellus Systems, Inc. | Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer |
US7855147B1 (en) | 2006-06-22 | 2010-12-21 | Novellus Systems, Inc. | Methods and apparatus for engineering an interface between a diffusion barrier layer and a seed layer |
US7297376B1 (en) | 2006-07-07 | 2007-11-20 | Applied Materials, Inc. | Method to reduce gas-phase reactions in a PECVD process with silicon and organic precursors to deposit defect-free initial layers |
JPWO2008020592A1 (ja) * | 2006-08-15 | 2010-01-07 | Jsr株式会社 | 膜形成用材料、ならびにケイ素含有絶縁膜およびその形成方法 |
US7740768B1 (en) | 2006-10-12 | 2010-06-22 | Novellus Systems, Inc. | Simultaneous front side ash and backside clean |
US7923819B2 (en) * | 2006-11-09 | 2011-04-12 | National Iniversity Corporation Tohoku University | Interlayer insulating film, wiring structure and electronic device and methods of manufacturing the same |
US7510634B1 (en) | 2006-11-10 | 2009-03-31 | Novellus Systems, Inc. | Apparatus and methods for deposition and/or etch selectivity |
KR100802226B1 (ko) * | 2006-12-21 | 2008-02-11 | 주식회사 하이닉스반도체 | 듀얼 다마신 패턴 형성 방법 |
US7682966B1 (en) | 2007-02-01 | 2010-03-23 | Novellus Systems, Inc. | Multistep method of depositing metal seed layers |
CN101611043B (zh) * | 2007-02-14 | 2013-03-13 | Jsr株式会社 | 含硅膜形成用材料、以及含硅绝缘膜及其形成方法 |
US7733552B2 (en) * | 2007-03-21 | 2010-06-08 | Qualcomm Mems Technologies, Inc | MEMS cavity-coating layers and methods |
US8435895B2 (en) | 2007-04-04 | 2013-05-07 | Novellus Systems, Inc. | Methods for stripping photoresist and/or cleaning metal regions |
US7807579B2 (en) * | 2007-04-19 | 2010-10-05 | Applied Materials, Inc. | Hydrogen ashing enhanced with water vapor and diluent gas |
US7719752B2 (en) | 2007-05-11 | 2010-05-18 | Qualcomm Mems Technologies, Inc. | MEMS structures, methods of fabricating MEMS components on separate substrates and assembly of same |
US7897516B1 (en) | 2007-05-24 | 2011-03-01 | Novellus Systems, Inc. | Use of ultra-high magnetic fields in resputter and plasma etching |
US7922880B1 (en) | 2007-05-24 | 2011-04-12 | Novellus Systems, Inc. | Method and apparatus for increasing local plasma density in magnetically confined plasma |
US20100261925A1 (en) * | 2007-07-10 | 2010-10-14 | Jsr Corporation | Method for producing silicon compound |
US7570415B2 (en) * | 2007-08-07 | 2009-08-04 | Qualcomm Mems Technologies, Inc. | MEMS device and interconnects for same |
KR100897826B1 (ko) * | 2007-08-31 | 2009-05-18 | 주식회사 동부하이텍 | 반도체 소자의 제조 방법 |
US7659197B1 (en) | 2007-09-21 | 2010-02-09 | Novellus Systems, Inc. | Selective resputtering of metal seed layers |
US8017523B1 (en) | 2008-05-16 | 2011-09-13 | Novellus Systems, Inc. | Deposition of doped copper seed layers having improved reliability |
US8133797B2 (en) * | 2008-05-16 | 2012-03-13 | Novellus Systems, Inc. | Protective layer to enable damage free gap fill |
US20100015816A1 (en) * | 2008-07-15 | 2010-01-21 | Kelvin Chan | Methods to promote adhesion between barrier layer and porous low-k film deposited from multiple liquid precursors |
US8591661B2 (en) | 2009-12-11 | 2013-11-26 | Novellus Systems, Inc. | Low damage photoresist strip method for low-K dielectrics |
US8278758B1 (en) * | 2009-04-29 | 2012-10-02 | Massachusetts Institute Of Technology | Multilevel reservoirs for integrated circuit interconnects |
WO2011072061A2 (en) * | 2009-12-11 | 2011-06-16 | Novellus Systems, Inc. | Enhanced passivation process to protect silicon prior to high dose implant strip |
US20110143548A1 (en) | 2009-12-11 | 2011-06-16 | David Cheung | Ultra low silicon loss high dose implant strip |
US9324576B2 (en) | 2010-05-27 | 2016-04-26 | Applied Materials, Inc. | Selective etch for silicon films |
US10283321B2 (en) | 2011-01-18 | 2019-05-07 | Applied Materials, Inc. | Semiconductor processing system and methods using capacitively coupled plasma |
US8771539B2 (en) | 2011-02-22 | 2014-07-08 | Applied Materials, Inc. | Remotely-excited fluorine and water vapor etch |
US8999856B2 (en) | 2011-03-14 | 2015-04-07 | Applied Materials, Inc. | Methods for etch of sin films |
US9064815B2 (en) | 2011-03-14 | 2015-06-23 | Applied Materials, Inc. | Methods for etch of metal and metal-oxide films |
US8771536B2 (en) | 2011-08-01 | 2014-07-08 | Applied Materials, Inc. | Dry-etch for silicon-and-carbon-containing films |
US9613825B2 (en) | 2011-08-26 | 2017-04-04 | Novellus Systems, Inc. | Photoresist strip processes for improved device integrity |
US8679982B2 (en) | 2011-08-26 | 2014-03-25 | Applied Materials, Inc. | Selective suppression of dry-etch rate of materials containing both silicon and oxygen |
US8679983B2 (en) | 2011-09-01 | 2014-03-25 | Applied Materials, Inc. | Selective suppression of dry-etch rate of materials containing both silicon and nitrogen |
US8927390B2 (en) | 2011-09-26 | 2015-01-06 | Applied Materials, Inc. | Intrench profile |
US8808563B2 (en) | 2011-10-07 | 2014-08-19 | Applied Materials, Inc. | Selective etch of silicon by way of metastable hydrogen termination |
WO2013070436A1 (en) | 2011-11-08 | 2013-05-16 | Applied Materials, Inc. | Methods of reducing substrate dislocation during gapfill processing |
US8637403B2 (en) | 2011-12-12 | 2014-01-28 | International Business Machines Corporation | Locally tailoring chemical mechanical polishing (CMP) polish rate for dielectrics |
KR20130081073A (ko) * | 2012-01-06 | 2013-07-16 | 삼성전자주식회사 | 반도체 장치 |
US8994178B2 (en) | 2012-03-29 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method for forming the same |
US8853831B2 (en) * | 2012-03-29 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method for forming the same |
US9267739B2 (en) | 2012-07-18 | 2016-02-23 | Applied Materials, Inc. | Pedestal with multi-zone temperature control and multiple purge capabilities |
US9373517B2 (en) | 2012-08-02 | 2016-06-21 | Applied Materials, Inc. | Semiconductor processing with DC assisted RF power for improved control |
US9034770B2 (en) | 2012-09-17 | 2015-05-19 | Applied Materials, Inc. | Differential silicon oxide etch |
US9023734B2 (en) | 2012-09-18 | 2015-05-05 | Applied Materials, Inc. | Radical-component oxide etch |
US9390937B2 (en) | 2012-09-20 | 2016-07-12 | Applied Materials, Inc. | Silicon-carbon-nitride selective etch |
US9132436B2 (en) | 2012-09-21 | 2015-09-15 | Applied Materials, Inc. | Chemical control features in wafer process equipment |
JP6096470B2 (ja) * | 2012-10-29 | 2017-03-15 | 東京エレクトロン株式会社 | プラズマ処理方法及びプラズマ処理装置 |
US8765574B2 (en) | 2012-11-09 | 2014-07-01 | Applied Materials, Inc. | Dry etch process |
US8969212B2 (en) | 2012-11-20 | 2015-03-03 | Applied Materials, Inc. | Dry-etch selectivity |
CN103839867A (zh) * | 2012-11-21 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | 改善浅沟槽隔离介电材料刻蚀形貌的方法 |
US8980763B2 (en) | 2012-11-30 | 2015-03-17 | Applied Materials, Inc. | Dry-etch for selective tungsten removal |
US9064816B2 (en) | 2012-11-30 | 2015-06-23 | Applied Materials, Inc. | Dry-etch for selective oxidation removal |
US9111877B2 (en) | 2012-12-18 | 2015-08-18 | Applied Materials, Inc. | Non-local plasma oxide etch |
US8921234B2 (en) | 2012-12-21 | 2014-12-30 | Applied Materials, Inc. | Selective titanium nitride etching |
US8901007B2 (en) * | 2013-01-03 | 2014-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Addition of carboxyl groups plasma during etching for interconnect reliability enhancement |
US9018108B2 (en) | 2013-01-25 | 2015-04-28 | Applied Materials, Inc. | Low shrinkage dielectric films |
US10256079B2 (en) | 2013-02-08 | 2019-04-09 | Applied Materials, Inc. | Semiconductor processing systems having multiple plasma configurations |
US9362130B2 (en) | 2013-03-01 | 2016-06-07 | Applied Materials, Inc. | Enhanced etching processes using remote plasma sources |
US9040422B2 (en) | 2013-03-05 | 2015-05-26 | Applied Materials, Inc. | Selective titanium nitride removal |
US8801952B1 (en) | 2013-03-07 | 2014-08-12 | Applied Materials, Inc. | Conformal oxide dry etch |
US10170282B2 (en) | 2013-03-08 | 2019-01-01 | Applied Materials, Inc. | Insulated semiconductor faceplate designs |
US20140271097A1 (en) | 2013-03-15 | 2014-09-18 | Applied Materials, Inc. | Processing systems and methods for halide scavenging |
US8895449B1 (en) | 2013-05-16 | 2014-11-25 | Applied Materials, Inc. | Delicate dry clean |
US9114438B2 (en) | 2013-05-21 | 2015-08-25 | Applied Materials, Inc. | Copper residue chamber clean |
US9493879B2 (en) | 2013-07-12 | 2016-11-15 | Applied Materials, Inc. | Selective sputtering for pattern transfer |
US9773648B2 (en) | 2013-08-30 | 2017-09-26 | Applied Materials, Inc. | Dual discharge modes operation for remote plasma |
US8956980B1 (en) | 2013-09-16 | 2015-02-17 | Applied Materials, Inc. | Selective etch of silicon nitride |
US8951429B1 (en) | 2013-10-29 | 2015-02-10 | Applied Materials, Inc. | Tungsten oxide processing |
US9576809B2 (en) | 2013-11-04 | 2017-02-21 | Applied Materials, Inc. | Etch suppression with germanium |
US9236265B2 (en) | 2013-11-04 | 2016-01-12 | Applied Materials, Inc. | Silicon germanium processing |
US9520303B2 (en) | 2013-11-12 | 2016-12-13 | Applied Materials, Inc. | Aluminum selective etch |
US9245762B2 (en) | 2013-12-02 | 2016-01-26 | Applied Materials, Inc. | Procedure for etch rate consistency |
US9117855B2 (en) | 2013-12-04 | 2015-08-25 | Applied Materials, Inc. | Polarity control for remote plasma |
US9263278B2 (en) | 2013-12-17 | 2016-02-16 | Applied Materials, Inc. | Dopant etch selectivity control |
US9287095B2 (en) | 2013-12-17 | 2016-03-15 | Applied Materials, Inc. | Semiconductor system assemblies and methods of operation |
US9190293B2 (en) | 2013-12-18 | 2015-11-17 | Applied Materials, Inc. | Even tungsten etch for high aspect ratio trenches |
US9287134B2 (en) | 2014-01-17 | 2016-03-15 | Applied Materials, Inc. | Titanium oxide etch |
US9396989B2 (en) | 2014-01-27 | 2016-07-19 | Applied Materials, Inc. | Air gaps between copper lines |
US9293568B2 (en) | 2014-01-27 | 2016-03-22 | Applied Materials, Inc. | Method of fin patterning |
US9385028B2 (en) | 2014-02-03 | 2016-07-05 | Applied Materials, Inc. | Air gap process |
US9499898B2 (en) | 2014-03-03 | 2016-11-22 | Applied Materials, Inc. | Layered thin film heater and method of fabrication |
US9299575B2 (en) | 2014-03-17 | 2016-03-29 | Applied Materials, Inc. | Gas-phase tungsten etch |
US9299538B2 (en) | 2014-03-20 | 2016-03-29 | Applied Materials, Inc. | Radial waveguide systems and methods for post-match control of microwaves |
US9299537B2 (en) | 2014-03-20 | 2016-03-29 | Applied Materials, Inc. | Radial waveguide systems and methods for post-match control of microwaves |
US9136273B1 (en) | 2014-03-21 | 2015-09-15 | Applied Materials, Inc. | Flash gate air gap |
US9903020B2 (en) | 2014-03-31 | 2018-02-27 | Applied Materials, Inc. | Generation of compact alumina passivation layers on aluminum plasma equipment components |
US9269590B2 (en) | 2014-04-07 | 2016-02-23 | Applied Materials, Inc. | Spacer formation |
US9309598B2 (en) | 2014-05-28 | 2016-04-12 | Applied Materials, Inc. | Oxide and metal removal |
US9847289B2 (en) | 2014-05-30 | 2017-12-19 | Applied Materials, Inc. | Protective via cap for improved interconnect performance |
US9514954B2 (en) | 2014-06-10 | 2016-12-06 | Lam Research Corporation | Peroxide-vapor treatment for enhancing photoresist-strip performance and modifying organic films |
US9378969B2 (en) | 2014-06-19 | 2016-06-28 | Applied Materials, Inc. | Low temperature gas-phase carbon removal |
US9406523B2 (en) | 2014-06-19 | 2016-08-02 | Applied Materials, Inc. | Highly selective doped oxide removal method |
US9425058B2 (en) | 2014-07-24 | 2016-08-23 | Applied Materials, Inc. | Simplified litho-etch-litho-etch process |
US9159606B1 (en) | 2014-07-31 | 2015-10-13 | Applied Materials, Inc. | Metal air gap |
US9496167B2 (en) | 2014-07-31 | 2016-11-15 | Applied Materials, Inc. | Integrated bit-line airgap formation and gate stack post clean |
US9378978B2 (en) | 2014-07-31 | 2016-06-28 | Applied Materials, Inc. | Integrated oxide recess and floating gate fin trimming |
US9165786B1 (en) | 2014-08-05 | 2015-10-20 | Applied Materials, Inc. | Integrated oxide and nitride recess for better channel contact in 3D architectures |
US9659753B2 (en) | 2014-08-07 | 2017-05-23 | Applied Materials, Inc. | Grooved insulator to reduce leakage current |
US9553102B2 (en) | 2014-08-19 | 2017-01-24 | Applied Materials, Inc. | Tungsten separation |
US9355856B2 (en) | 2014-09-12 | 2016-05-31 | Applied Materials, Inc. | V trench dry etch |
US9368364B2 (en) | 2014-09-24 | 2016-06-14 | Applied Materials, Inc. | Silicon etch process with tunable selectivity to SiO2 and other materials |
US9478434B2 (en) | 2014-09-24 | 2016-10-25 | Applied Materials, Inc. | Chlorine-based hardmask removal |
US9613822B2 (en) | 2014-09-25 | 2017-04-04 | Applied Materials, Inc. | Oxide etch selectivity enhancement |
US9966240B2 (en) | 2014-10-14 | 2018-05-08 | Applied Materials, Inc. | Systems and methods for internal surface conditioning assessment in plasma processing equipment |
US9355922B2 (en) | 2014-10-14 | 2016-05-31 | Applied Materials, Inc. | Systems and methods for internal surface conditioning in plasma processing equipment |
US11637002B2 (en) | 2014-11-26 | 2023-04-25 | Applied Materials, Inc. | Methods and systems to enhance process uniformity |
US9299583B1 (en) | 2014-12-05 | 2016-03-29 | Applied Materials, Inc. | Aluminum oxide selective etch |
US10224210B2 (en) | 2014-12-09 | 2019-03-05 | Applied Materials, Inc. | Plasma processing system with direct outlet toroidal plasma source |
US10573496B2 (en) | 2014-12-09 | 2020-02-25 | Applied Materials, Inc. | Direct outlet toroidal plasma source |
US9502258B2 (en) | 2014-12-23 | 2016-11-22 | Applied Materials, Inc. | Anisotropic gap etch |
US9343272B1 (en) | 2015-01-08 | 2016-05-17 | Applied Materials, Inc. | Self-aligned process |
US11257693B2 (en) | 2015-01-09 | 2022-02-22 | Applied Materials, Inc. | Methods and systems to improve pedestal temperature control |
US9373522B1 (en) | 2015-01-22 | 2016-06-21 | Applied Mateials, Inc. | Titanium nitride removal |
US9449846B2 (en) | 2015-01-28 | 2016-09-20 | Applied Materials, Inc. | Vertical gate separation |
US9728437B2 (en) | 2015-02-03 | 2017-08-08 | Applied Materials, Inc. | High temperature chuck for plasma processing systems |
US20160225652A1 (en) | 2015-02-03 | 2016-08-04 | Applied Materials, Inc. | Low temperature chuck for plasma processing systems |
US9881805B2 (en) | 2015-03-02 | 2018-01-30 | Applied Materials, Inc. | Silicon selective removal |
US9691645B2 (en) | 2015-08-06 | 2017-06-27 | Applied Materials, Inc. | Bolted wafer chuck thermal management systems and methods for wafer processing systems |
US9741593B2 (en) | 2015-08-06 | 2017-08-22 | Applied Materials, Inc. | Thermal management systems and methods for wafer processing systems |
US9349605B1 (en) | 2015-08-07 | 2016-05-24 | Applied Materials, Inc. | Oxide etch selectivity systems and methods |
US10504700B2 (en) | 2015-08-27 | 2019-12-10 | Applied Materials, Inc. | Plasma etching systems and methods with secondary plasma injection |
US9934984B2 (en) * | 2015-09-09 | 2018-04-03 | International Business Machines Corporation | Hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication |
US9490143B1 (en) * | 2015-11-25 | 2016-11-08 | Texas Instruments Incorporated | Method of fabricating semiconductors |
US10522371B2 (en) | 2016-05-19 | 2019-12-31 | Applied Materials, Inc. | Systems and methods for improved semiconductor etching and component protection |
US10504754B2 (en) | 2016-05-19 | 2019-12-10 | Applied Materials, Inc. | Systems and methods for improved semiconductor etching and component protection |
US9865484B1 (en) | 2016-06-29 | 2018-01-09 | Applied Materials, Inc. | Selective etch using material modification and RF pulsing |
US10629473B2 (en) | 2016-09-09 | 2020-04-21 | Applied Materials, Inc. | Footing removal for nitride spacer |
US10062575B2 (en) | 2016-09-09 | 2018-08-28 | Applied Materials, Inc. | Poly directional etch by oxidation |
US9934942B1 (en) | 2016-10-04 | 2018-04-03 | Applied Materials, Inc. | Chamber with flow-through source |
US9721789B1 (en) | 2016-10-04 | 2017-08-01 | Applied Materials, Inc. | Saving ion-damaged spacers |
US10546729B2 (en) | 2016-10-04 | 2020-01-28 | Applied Materials, Inc. | Dual-channel showerhead with improved profile |
US10062585B2 (en) | 2016-10-04 | 2018-08-28 | Applied Materials, Inc. | Oxygen compatible plasma source |
US10062579B2 (en) | 2016-10-07 | 2018-08-28 | Applied Materials, Inc. | Selective SiN lateral recess |
US9947549B1 (en) | 2016-10-10 | 2018-04-17 | Applied Materials, Inc. | Cobalt-containing material removal |
US9768034B1 (en) | 2016-11-11 | 2017-09-19 | Applied Materials, Inc. | Removal methods for high aspect ratio structures |
US10163696B2 (en) | 2016-11-11 | 2018-12-25 | Applied Materials, Inc. | Selective cobalt removal for bottom up gapfill |
US10026621B2 (en) | 2016-11-14 | 2018-07-17 | Applied Materials, Inc. | SiN spacer profile patterning |
US10242908B2 (en) | 2016-11-14 | 2019-03-26 | Applied Materials, Inc. | Airgap formation with damage-free copper |
US10566206B2 (en) | 2016-12-27 | 2020-02-18 | Applied Materials, Inc. | Systems and methods for anisotropic material breakthrough |
US10403507B2 (en) | 2017-02-03 | 2019-09-03 | Applied Materials, Inc. | Shaped etch profile with oxidation |
US10431429B2 (en) | 2017-02-03 | 2019-10-01 | Applied Materials, Inc. | Systems and methods for radial and azimuthal control of plasma uniformity |
US10043684B1 (en) | 2017-02-06 | 2018-08-07 | Applied Materials, Inc. | Self-limiting atomic thermal etching systems and methods |
US10319739B2 (en) | 2017-02-08 | 2019-06-11 | Applied Materials, Inc. | Accommodating imperfectly aligned memory holes |
US10943834B2 (en) | 2017-03-13 | 2021-03-09 | Applied Materials, Inc. | Replacement contact process |
US10319649B2 (en) | 2017-04-11 | 2019-06-11 | Applied Materials, Inc. | Optical emission spectroscopy (OES) for remote plasma monitoring |
US10832909B2 (en) * | 2017-04-24 | 2020-11-10 | Lam Research Corporation | Atomic layer etch, reactive precursors and energetic sources for patterning applications |
US11276590B2 (en) | 2017-05-17 | 2022-03-15 | Applied Materials, Inc. | Multi-zone semiconductor substrate supports |
US11276559B2 (en) | 2017-05-17 | 2022-03-15 | Applied Materials, Inc. | Semiconductor processing chamber for multiple precursor flow |
US10497579B2 (en) | 2017-05-31 | 2019-12-03 | Applied Materials, Inc. | Water-free etching methods |
US10049891B1 (en) | 2017-05-31 | 2018-08-14 | Applied Materials, Inc. | Selective in situ cobalt residue removal |
US10920320B2 (en) | 2017-06-16 | 2021-02-16 | Applied Materials, Inc. | Plasma health determination in semiconductor substrate processing reactors |
US10541246B2 (en) | 2017-06-26 | 2020-01-21 | Applied Materials, Inc. | 3D flash memory cells which discourage cross-cell electrical tunneling |
US10727080B2 (en) | 2017-07-07 | 2020-07-28 | Applied Materials, Inc. | Tantalum-containing material removal |
US10541184B2 (en) | 2017-07-11 | 2020-01-21 | Applied Materials, Inc. | Optical emission spectroscopic techniques for monitoring etching |
US10354889B2 (en) | 2017-07-17 | 2019-07-16 | Applied Materials, Inc. | Non-halogen etching of silicon-containing materials |
US10170336B1 (en) | 2017-08-04 | 2019-01-01 | Applied Materials, Inc. | Methods for anisotropic control of selective silicon removal |
US10043674B1 (en) | 2017-08-04 | 2018-08-07 | Applied Materials, Inc. | Germanium etching systems and methods |
US10297458B2 (en) | 2017-08-07 | 2019-05-21 | Applied Materials, Inc. | Process window widening using coated parts in plasma etch processes |
US10283324B1 (en) | 2017-10-24 | 2019-05-07 | Applied Materials, Inc. | Oxygen treatment for nitride etching |
US10128086B1 (en) | 2017-10-24 | 2018-11-13 | Applied Materials, Inc. | Silicon pretreatment for nitride removal |
US10256112B1 (en) | 2017-12-08 | 2019-04-09 | Applied Materials, Inc. | Selective tungsten removal |
US10903054B2 (en) | 2017-12-19 | 2021-01-26 | Applied Materials, Inc. | Multi-zone gas distribution systems and methods |
US11328909B2 (en) | 2017-12-22 | 2022-05-10 | Applied Materials, Inc. | Chamber conditioning and removal processes |
US10854426B2 (en) | 2018-01-08 | 2020-12-01 | Applied Materials, Inc. | Metal recess for semiconductor structures |
US10586801B2 (en) | 2018-01-12 | 2020-03-10 | Intel Corporation | Flash memory cells |
US10679870B2 (en) | 2018-02-15 | 2020-06-09 | Applied Materials, Inc. | Semiconductor processing chamber multistage mixing apparatus |
US10964512B2 (en) | 2018-02-15 | 2021-03-30 | Applied Materials, Inc. | Semiconductor processing chamber multistage mixing apparatus and methods |
TWI716818B (zh) | 2018-02-28 | 2021-01-21 | 美商應用材料股份有限公司 | 形成氣隙的系統及方法 |
US10593560B2 (en) | 2018-03-01 | 2020-03-17 | Applied Materials, Inc. | Magnetic induction plasma source for semiconductor processes and equipment |
US10319600B1 (en) | 2018-03-12 | 2019-06-11 | Applied Materials, Inc. | Thermal silicon etch |
US10497573B2 (en) | 2018-03-13 | 2019-12-03 | Applied Materials, Inc. | Selective atomic layer etching of semiconductor materials |
US10573527B2 (en) | 2018-04-06 | 2020-02-25 | Applied Materials, Inc. | Gas-phase selective etching systems and methods |
US10490406B2 (en) | 2018-04-10 | 2019-11-26 | Appled Materials, Inc. | Systems and methods for material breakthrough |
US10699879B2 (en) | 2018-04-17 | 2020-06-30 | Applied Materials, Inc. | Two piece electrode assembly with gap for plasma control |
US10886137B2 (en) | 2018-04-30 | 2021-01-05 | Applied Materials, Inc. | Selective nitride removal |
US10755941B2 (en) | 2018-07-06 | 2020-08-25 | Applied Materials, Inc. | Self-limiting selective etching systems and methods |
US10872778B2 (en) | 2018-07-06 | 2020-12-22 | Applied Materials, Inc. | Systems and methods utilizing solid-phase etchants |
US10672642B2 (en) | 2018-07-24 | 2020-06-02 | Applied Materials, Inc. | Systems and methods for pedestal configuration |
US10892198B2 (en) | 2018-09-14 | 2021-01-12 | Applied Materials, Inc. | Systems and methods for improved performance in semiconductor processing |
US11049755B2 (en) | 2018-09-14 | 2021-06-29 | Applied Materials, Inc. | Semiconductor substrate supports with embedded RF shield |
US11062887B2 (en) | 2018-09-17 | 2021-07-13 | Applied Materials, Inc. | High temperature RF heater pedestals |
US11417534B2 (en) | 2018-09-21 | 2022-08-16 | Applied Materials, Inc. | Selective material removal |
US11682560B2 (en) | 2018-10-11 | 2023-06-20 | Applied Materials, Inc. | Systems and methods for hafnium-containing film removal |
US11121002B2 (en) | 2018-10-24 | 2021-09-14 | Applied Materials, Inc. | Systems and methods for etching metals and metal derivatives |
US10950549B2 (en) | 2018-11-16 | 2021-03-16 | International Business Machines Corporation | ILD gap fill for memory device stack array |
US11437242B2 (en) | 2018-11-27 | 2022-09-06 | Applied Materials, Inc. | Selective removal of silicon-containing materials |
US11721527B2 (en) | 2019-01-07 | 2023-08-08 | Applied Materials, Inc. | Processing chamber mixing systems |
US10741609B2 (en) | 2019-01-08 | 2020-08-11 | International Business Machines Corporation | Pre-patterned etch stop for interconnect trench formation overlying embedded MRAM structures |
US10920319B2 (en) | 2019-01-11 | 2021-02-16 | Applied Materials, Inc. | Ceramic showerheads with conductive electrodes |
US11177170B2 (en) | 2020-01-16 | 2021-11-16 | International Business Machines Corporation | Removal of barrier and liner layers from a bottom of a via |
CN115775768B (zh) * | 2023-02-13 | 2023-07-04 | 长鑫存储技术有限公司 | 半导体结构及其制作方法 |
Family Cites Families (106)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4303632A (en) | 1979-12-14 | 1981-12-01 | E. I. Du Pont De Nemours And Company | Preparation of hydrogen peroxide |
US4845054A (en) | 1985-06-14 | 1989-07-04 | Focus Semiconductor Systems, Inc. | Low temperature chemical vapor deposition of silicon dioxide films |
US4789648A (en) | 1985-10-28 | 1988-12-06 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias |
US4676867A (en) * | 1986-06-06 | 1987-06-30 | Rockwell International Corporation | Planarization process for double metal MOS using spin-on glass as a sacrificial layer |
JPS6343157A (ja) * | 1986-08-11 | 1988-02-24 | Toshiba Corp | 電子写真感光体 |
US5000113A (en) | 1986-12-19 | 1991-03-19 | Applied Materials, Inc. | Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process |
ZA884511B (en) | 1987-07-15 | 1989-03-29 | Boc Group Inc | Method of plasma enhanced silicon oxide deposition |
JPH077759B2 (ja) | 1987-08-20 | 1995-01-30 | 株式会社半導体エネルギ−研究所 | 絶縁膜形成方法 |
US4900591A (en) | 1988-01-20 | 1990-02-13 | The United States Of America As Represented By The Secretary Of The Air Force | Method for the deposition of high quality silicon dioxide at low temperature |
US4808259A (en) * | 1988-01-25 | 1989-02-28 | Intel Corporation | Plasma etching process for MOS circuit pregate etching utiliizing a multi-step power reduction recipe |
CA1317740C (en) | 1988-10-24 | 1993-05-18 | Karl T. Chuang | Production of hydrogen peroxide |
KR910010516A (ko) | 1989-11-15 | 1991-06-29 | 아오이 죠이치 | 반도체 메모리장치 |
CA2048168A1 (en) | 1990-08-03 | 1992-02-04 | John T. Felts | Silicon oxide based thin film vapour barriers |
US5356515A (en) | 1990-10-19 | 1994-10-18 | Tokyo Electron Limited | Dry etching method |
US5262279A (en) | 1990-12-21 | 1993-11-16 | Intel Corporation | Dry process for stripping photoresist from a polyimide surface |
EP0519079B1 (en) | 1991-01-08 | 1999-03-03 | Fujitsu Limited | Process for forming silicon oxide film |
US5389581A (en) * | 1991-06-07 | 1995-02-14 | Intel Corporation | High density TEOS-based film for intermetal dielectrics |
US6238588B1 (en) | 1991-06-27 | 2001-05-29 | Applied Materials, Inc. | High pressure high non-reactive diluent gas content high plasma ion density plasma oxide etch process |
US5246887A (en) | 1991-07-10 | 1993-09-21 | At&T Bell Laboratories | Dielectric deposition |
US5204141A (en) | 1991-09-18 | 1993-04-20 | Air Products And Chemicals, Inc. | Deposition of silicon dioxide films at temperatures as low as 100 degree c. by lpcvd using organodisilane sources |
JPH05267480A (ja) | 1992-03-21 | 1993-10-15 | Ricoh Co Ltd | 半導体装置とその製造方法 |
JP2934353B2 (ja) | 1992-06-24 | 1999-08-16 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US5739579A (en) | 1992-06-29 | 1998-04-14 | Intel Corporation | Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections |
JP3262334B2 (ja) | 1992-07-04 | 2002-03-04 | トリコン ホルディングズ リミテッド | 半導体ウエハーを処理する方法 |
US5271972A (en) | 1992-08-17 | 1993-12-21 | Applied Materials, Inc. | Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity |
JPH0795548B2 (ja) | 1992-09-10 | 1995-10-11 | アプライド マテリアルズ インコーポレイテッド | 二酸化珪素膜の気相成長法 |
US5610105A (en) | 1992-10-23 | 1997-03-11 | Vlsi Technology, Inc. | Densification in an intermetal dielectric film |
JP2684942B2 (ja) | 1992-11-30 | 1997-12-03 | 日本電気株式会社 | 化学気相成長法と化学気相成長装置および多層配線の製造方法 |
GB9402486D0 (en) | 1994-02-09 | 1994-03-30 | Electrotech Ltd | Forming a layer |
US5486493A (en) | 1994-02-25 | 1996-01-23 | Jeng; Shin-Puu | Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators |
US5509553A (en) | 1994-04-22 | 1996-04-23 | Litel Instruments | Direct etch processes for the manufacture of high density multichip modules |
US5858880A (en) | 1994-05-14 | 1999-01-12 | Trikon Equipment Limited | Method of treating a semi-conductor wafer |
US5488015A (en) | 1994-05-20 | 1996-01-30 | Texas Instruments Incorporated | Method of making an interconnect structure with an integrated low density dielectric |
JPH0855913A (ja) | 1994-06-07 | 1996-02-27 | Texas Instr Inc <Ti> | サブミクロン相互接続の選択的空隙充填方法 |
US5492736A (en) | 1994-11-28 | 1996-02-20 | Air Products And Chemicals, Inc. | Fluorine doped silicon oxide process |
US5550405A (en) | 1994-12-21 | 1996-08-27 | Advanced Micro Devices, Incorporated | Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS |
US5559055A (en) | 1994-12-21 | 1996-09-24 | Advanced Micro Devices, Inc. | Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance |
JPH08181210A (ja) | 1994-12-26 | 1996-07-12 | Toshiba Corp | 半導体装置の製造方法 |
JPH08181276A (ja) | 1994-12-26 | 1996-07-12 | Toshiba Corp | 半導体装置の製造方法 |
TW285753B (zh) | 1995-01-04 | 1996-09-11 | Air Prod & Chem | |
US5534462A (en) | 1995-02-24 | 1996-07-09 | Motorola, Inc. | Method for forming a plug and semiconductor device having the same |
FR2734402B1 (fr) | 1995-05-15 | 1997-07-18 | Brouquet Pierre | Procede pour l'isolement electrique en micro-electronique, applicable aux cavites etroites, par depot d'oxyde a l'etat visqueux et dispositif correspondant |
JP3463416B2 (ja) | 1995-06-23 | 2003-11-05 | ソニー株式会社 | 絶縁膜の製造方法および半導体装置 |
KR0161422B1 (ko) | 1995-07-31 | 1999-02-01 | 김광호 | 접촉창을 용이하게 매몰한 반도체 장치 및 그 제조 방법 |
JPH09116011A (ja) | 1995-10-23 | 1997-05-02 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
TW328971B (en) | 1995-10-30 | 1998-04-01 | Dow Corning | Method for depositing Si-O containing coatings |
US5968324A (en) * | 1995-12-05 | 1999-10-19 | Applied Materials, Inc. | Method and apparatus for depositing antireflective coating |
JPH09237785A (ja) | 1995-12-28 | 1997-09-09 | Toshiba Corp | 半導体装置およびその製造方法 |
US5843847A (en) | 1996-04-29 | 1998-12-01 | Applied Materials, Inc. | Method for etching dielectric layers with high selectivity and low microloading |
US5710079A (en) | 1996-05-24 | 1998-01-20 | Lsi Logic Corporation | Method and apparatus for forming dielectric films |
US6127262A (en) * | 1996-06-28 | 2000-10-03 | Applied Materials, Inc. | Method and apparatus for depositing an etch stop layer |
US6156149A (en) * | 1997-05-07 | 2000-12-05 | Applied Materials, Inc. | In situ deposition of a dielectric oxide layer and anti-reflective coating |
US6083852A (en) * | 1997-05-07 | 2000-07-04 | Applied Materials, Inc. | Method for applying films using reduced deposition rates |
US5693563A (en) | 1996-07-15 | 1997-12-02 | Chartered Semiconductor Manufacturing Pte Ltd. | Etch stop for copper damascene process |
US5807785A (en) | 1996-08-02 | 1998-09-15 | Applied Materials, Inc. | Low dielectric constant silicon dioxide sandwich layer |
KR100440233B1 (ko) | 1996-08-24 | 2004-07-15 | 트리콘 이큅먼츠 리미티드 | 반도체 기판 처리방법 |
GB9618620D0 (en) | 1996-09-06 | 1996-10-16 | Electrotech Equipments Ltd | A method of forming a layer |
US5812403A (en) | 1996-11-13 | 1998-09-22 | Applied Materials, Inc. | Methods and apparatus for cleaning surfaces in a substrate processing system |
JP3773340B2 (ja) | 1996-12-18 | 2006-05-10 | 大日本印刷株式会社 | 低屈折率SiO2 膜及びその製造方法 |
US5691247A (en) | 1996-12-19 | 1997-11-25 | Tower Semiconductor Ltd. | Method for depositing a flow fill layer on an integrated circuit wafer |
KR19980064444A (ko) | 1996-12-20 | 1998-10-07 | 윌리엄비.켐플러 | 다층 집적 회로 유전체 구조의 에칭 방법 |
US6077764A (en) * | 1997-04-21 | 2000-06-20 | Applied Materials, Inc. | Process for depositing high deposition rate halogen-doped silicon oxide layer |
EP0885983A1 (en) | 1997-06-19 | 1998-12-23 | N.V. Bekaert S.A. | Method for coating a substrate with a diamond like nanocomposite composition |
DE19804375B4 (de) | 1997-06-26 | 2005-05-19 | Mitsubishi Denki K.K. | Verfahren zur Herstellung eines Zwischenschichtisolierfilmes |
JPH1116904A (ja) | 1997-06-26 | 1999-01-22 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US5891799A (en) | 1997-08-18 | 1999-04-06 | Industrial Technology Research Institute | Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates |
US6035803A (en) * | 1997-09-29 | 2000-03-14 | Applied Materials, Inc. | Method and apparatus for controlling the deposition of a fluorinated carbon film |
US5908672A (en) * | 1997-10-15 | 1999-06-01 | Applied Materials, Inc. | Method and apparatus for depositing a planarized passivation layer |
US6291334B1 (en) * | 1997-12-19 | 2001-09-18 | Applied Materials, Inc. | Etch stop layer for dual damascene process |
US6140226A (en) | 1998-01-16 | 2000-10-31 | International Business Machines Corporation | Dual damascene processing for semiconductor chip interconnects |
US6514880B2 (en) | 1998-02-05 | 2003-02-04 | Asm Japan K.K. | Siloxan polymer film on semiconductor substrate and method for forming same |
TW437017B (en) | 1998-02-05 | 2001-05-28 | Asm Japan Kk | Silicone polymer insulation film on semiconductor substrate and method for formation thereof |
US6287990B1 (en) * | 1998-02-11 | 2001-09-11 | Applied Materials, Inc. | CVD plasma assisted low dielectric constant films |
US6413583B1 (en) | 1998-02-11 | 2002-07-02 | Applied Materials, Inc. | Formation of a liquid-like silica layer by reaction of an organosilicon compound and a hydroxyl forming compound |
US6340435B1 (en) | 1998-02-11 | 2002-01-22 | Applied Materials, Inc. | Integrated low K dielectrics and etch stops |
US6054379A (en) | 1998-02-11 | 2000-04-25 | Applied Materials, Inc. | Method of depositing a low k dielectric with organo silane |
US6303523B2 (en) | 1998-02-11 | 2001-10-16 | Applied Materials, Inc. | Plasma processes for depositing low dielectric constant films |
US6068884A (en) | 1998-04-28 | 2000-05-30 | Silcon Valley Group Thermal Systems, Llc | Method of making low κ dielectric inorganic/organic hybrid films |
US6159871A (en) | 1998-05-29 | 2000-12-12 | Dow Corning Corporation | Method for producing hydrogenated silicon oxycarbide films having low dielectric constant |
US6232235B1 (en) * | 1998-06-03 | 2001-05-15 | Motorola, Inc. | Method of forming a semiconductor device |
US6054206A (en) | 1998-06-22 | 2000-04-25 | Novellus Systems, Inc. | Chemical vapor deposition of low density silicon dioxide films |
US6316167B1 (en) | 2000-01-10 | 2001-11-13 | International Business Machines Corporation | Tunabale vapor deposited materials as antireflective coatings, hardmasks and as combined antireflective coating/hardmasks and methods of fabrication thereof and application thereof |
US6147009A (en) * | 1998-06-29 | 2000-11-14 | International Business Machines Corporation | Hydrogenated oxidized silicon carbon material |
US6248429B1 (en) * | 1998-07-06 | 2001-06-19 | Micron Technology, Inc. | Metallized recess in a substrate |
US6211092B1 (en) * | 1998-07-09 | 2001-04-03 | Applied Materials, Inc. | Counterbore dielectric plasma etch process particularly useful for dual damascene |
TW437040B (en) | 1998-08-12 | 2001-05-28 | Applied Materials Inc | Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics |
US6284149B1 (en) * | 1998-09-18 | 2001-09-04 | Applied Materials, Inc. | High-density plasma etching of carbon-based low-k materials in a integrated circuit |
US6181055B1 (en) * | 1998-10-12 | 2001-01-30 | Extreme Devices, Inc. | Multilayer carbon-based field emission electron device for high current density applications |
US6228758B1 (en) * | 1998-10-14 | 2001-05-08 | Advanced Micro Devices, Inc. | Method of making dual damascene conductive interconnections and integrated circuit device comprising same |
US6225211B1 (en) * | 1999-04-29 | 2001-05-01 | Industrial Technology Research Institute | Method for making stacked and borderless via structures on semiconductor substrates for integrated circuits |
US6251770B1 (en) | 1999-06-30 | 2001-06-26 | Lam Research Corp. | Dual-damascene dielectric structures and methods for making the same |
JP2001044191A (ja) | 1999-07-27 | 2001-02-16 | Sony Corp | 積層絶縁膜とその製造方法および半導体装置とその製造方法 |
US6756674B1 (en) | 1999-10-22 | 2004-06-29 | Lsi Logic Corporation | Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same |
US6350670B1 (en) | 1999-12-17 | 2002-02-26 | Intel Corporation | Method for making a semiconductor device having a carbon doped oxide insulating layer |
EP1123991A3 (en) | 2000-02-08 | 2002-11-13 | Asm Japan K.K. | Low dielectric constant materials and processes |
US6362091B1 (en) * | 2000-03-14 | 2002-03-26 | Intel Corporation | Method for making a semiconductor device having a low-k dielectric layer |
US6363091B1 (en) | 2000-06-05 | 2002-03-26 | Agilent Technologies, Inc | Coherent population trapping-based method for generating a frequency standard having a reduced magnitude of total a.c. stark shift |
EP1172847A3 (en) * | 2000-07-10 | 2004-07-28 | Interuniversitair Micro-Elektronica Centrum Vzw | A method to produce a porous oxygen-silicon layer |
US6451683B1 (en) | 2000-08-28 | 2002-09-17 | Micron Technology, Inc. | Damascene structure and method of making |
US6395632B1 (en) | 2000-08-31 | 2002-05-28 | Micron Technology, Inc. | Etch stop in damascene interconnect structure and method of making |
US6518646B1 (en) | 2001-03-29 | 2003-02-11 | Advanced Micro Devices, Inc. | Semiconductor device with variable composition low-k inter-layer dielectric and method of making |
US7311852B2 (en) | 2001-03-30 | 2007-12-25 | Lam Research Corporation | Method of plasma etching low-k dielectric materials |
US6570256B2 (en) * | 2001-07-20 | 2003-05-27 | International Business Machines Corporation | Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates |
US6887780B2 (en) | 2001-08-31 | 2005-05-03 | Intel Corporation | Concentration graded carbon doped oxide |
US6972253B2 (en) | 2003-09-09 | 2005-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming dielectric barrier layer in damascene structure |
US7008882B2 (en) | 2003-11-28 | 2006-03-07 | United Microelectronics Corp. | Method and structure for the adhesion between dielectric layers |
-
1999
- 1999-06-09 US US09/329,012 patent/US6340435B1/en not_active Expired - Fee Related
-
2000
- 2000-05-22 TW TW089109877A patent/TW473870B/zh not_active IP Right Cessation
- 2000-06-08 EP EP00112300A patent/EP1059664A3/en not_active Withdrawn
- 2000-06-09 KR KR1020000031621A patent/KR100661201B1/ko active IP Right Grant
- 2000-06-09 JP JP2000173807A patent/JP2001110789A/ja not_active Withdrawn
-
2001
- 2001-11-05 US US10/011,368 patent/US6858153B2/en not_active Expired - Lifetime
- 2001-11-05 US US10/011,369 patent/US6669858B2/en not_active Expired - Lifetime
-
2004
- 2004-08-24 US US10/924,551 patent/US7227244B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI399808B (zh) * | 2005-03-25 | 2013-06-21 | Tokyo Electron Ltd | Etching method and etching device |
TWI489549B (zh) * | 2009-04-09 | 2015-06-21 | Lam Res Corp | 可減少損壞之低介電常數介電層蝕刻方法 |
Also Published As
Publication number | Publication date |
---|---|
US6858153B2 (en) | 2005-02-22 |
KR100661201B1 (ko) | 2006-12-22 |
KR20010007315A (ko) | 2001-01-26 |
US20020084257A1 (en) | 2002-07-04 |
US20020074309A1 (en) | 2002-06-20 |
US6669858B2 (en) | 2003-12-30 |
US7227244B2 (en) | 2007-06-05 |
JP2001110789A (ja) | 2001-04-20 |
US6340435B1 (en) | 2002-01-22 |
EP1059664A2 (en) | 2000-12-13 |
US20050023694A1 (en) | 2005-02-03 |
EP1059664A3 (en) | 2001-10-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW473870B (en) | Integrated low K dielectrics and etch stops | |
TW466632B (en) | Method of depositing a low K films using an oxidizing plasma | |
TWI426545B (zh) | 沉積具有改進密度與階梯覆蓋率之非晶系碳膜的方法 | |
TWI332034B (en) | Method for depositing an amorphous carbon films in a cvd chamber | |
TWI314588B (en) | Dielectric materials to prevent photoresist poisoning | |
JP3400770B2 (ja) | エッチング方法、半導体装置及びその製造方法 | |
JP5090430B2 (ja) | 低誘電率膜の堆積処理方法、基板処理システム、デュアルダマシン構造の形成方法、およびデュアルダマシン構造 | |
TWI352387B (en) | Etch methods to form anisotropic features for high | |
TWI320203B (en) | Process to open carbon based hardmask | |
TW558769B (en) | Etch process for dielectric materials comprising oxidized organo silane materials | |
TW201726965A (zh) | 形成氮碳氧化矽薄膜的方法 | |
TWI528454B (zh) | 半導體裝置及半導體裝置之製造方法 | |
TW546768B (en) | Method of depositing organosilicate layers | |
TW200300980A (en) | Process for selectively etching dielectric layers | |
KR20050034566A (ko) | 실리콘 탄화물막을 제조하는 방법 | |
TW201142945A (en) | Ultra low dielectric materials using hybrid precursors containing silicon with organic functional groups by plasma-enhanced chemical vapor deposition | |
TW201009933A (en) | Post etch reactive plasma milling to smooth through substrate via sidewalls and other deeply etched features | |
TW200405467A (en) | An oxide etching process for etching an oxide layer over a nitride layer | |
TW200949909A (en) | Method for depositing an amorphous carbon film with improved density and step coverage | |
JP2004247725A (ja) | シリコンカーバイド膜を形成する方法 | |
JP2011526078A (ja) | 薄いバリア層を用いた多孔性誘電体への溶媒および溶液の侵入の阻止および低減 | |
TWI244136B (en) | Low oxygen content photoresist stripping process for low dielectric constant materials | |
JP4015510B2 (ja) | 半導体集積回路の多層配線用層間絶縁膜及びその製造方法 | |
US7105460B2 (en) | Nitrogen-free dielectric anti-reflective coating and hardmask | |
TW569340B (en) | Electronic devices and methods of manufacture |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MK4A | Expiration of patent term of an invention patent |