GB9618620D0 - A method of forming a layer - Google Patents

A method of forming a layer

Info

Publication number
GB9618620D0
GB9618620D0 GB9618620A GB9618620A GB9618620D0 GB 9618620 D0 GB9618620 D0 GB 9618620D0 GB 9618620 A GB9618620 A GB 9618620A GB 9618620 A GB9618620 A GB 9618620A GB 9618620 D0 GB9618620 D0 GB 9618620D0
Authority
GB
Grant status
Application
Patent type
Prior art keywords
layer
forming
method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
GB9618620A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Electrotech Equipments Ltd
Original Assignee
Electrotech Equipments Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/312Organic layers, e.g. photoresist
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
GB9618620A 1996-09-06 1996-09-06 A method of forming a layer Pending GB9618620D0 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9618620A GB9618620D0 (en) 1996-09-06 1996-09-06 A method of forming a layer

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB9618620A GB9618620D0 (en) 1996-09-06 1996-09-06 A method of forming a layer
DE1997137825 DE19737825A1 (en) 1996-09-06 1997-08-29 A process for preparing a coating
GB9718654A GB2317270A (en) 1996-09-06 1997-09-04 Forming a layer on a pre-stressed semiconductor wafer
JP24095197A JPH10177938A (en) 1996-09-06 1997-09-05 Method of forming layer

Publications (1)

Publication Number Publication Date
GB9618620D0 true true GB9618620D0 (en) 1996-10-16

Family

ID=10799521

Family Applications (2)

Application Number Title Priority Date Filing Date
GB9618620A Pending GB9618620D0 (en) 1996-09-06 1996-09-06 A method of forming a layer
GB9718654A Withdrawn GB2317270A (en) 1996-09-06 1997-09-04 Forming a layer on a pre-stressed semiconductor wafer

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB9718654A Withdrawn GB2317270A (en) 1996-09-06 1997-09-04 Forming a layer on a pre-stressed semiconductor wafer

Country Status (3)

Country Link
JP (1) JPH10177938A (en)
DE (1) DE19737825A1 (en)
GB (2) GB9618620D0 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6340435B1 (en) 1998-02-11 2002-01-22 Applied Materials, Inc. Integrated low K dielectrics and etch stops
US6800571B2 (en) 1998-09-29 2004-10-05 Applied Materials Inc. CVD plasma assisted low dielectric constant films
US6413583B1 (en) 1998-02-11 2002-07-02 Applied Materials, Inc. Formation of a liquid-like silica layer by reaction of an organosilicon compound and a hydroxyl forming compound
GB0029570D0 (en) * 2000-12-05 2001-01-17 Trikon Holdings Ltd Electrostatic clamp
KR100809335B1 (en) 2006-09-28 2008-03-05 삼성전자주식회사 Semiconductor device and method of fabricating the same
US20080116521A1 (en) 2006-11-16 2008-05-22 Samsung Electronics Co., Ltd CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities and Methods of Forming Same
US7534678B2 (en) 2007-03-27 2009-05-19 Samsung Electronics Co., Ltd. Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby
US7902082B2 (en) 2007-09-20 2011-03-08 Samsung Electronics Co., Ltd. Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers
US7923365B2 (en) 2007-10-17 2011-04-12 Samsung Electronics Co., Ltd. Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5275683A (en) * 1991-10-24 1994-01-04 Tokyo Electron Limited Mount for supporting substrates and plasma processing apparatus using the same

Also Published As

Publication number Publication date Type
JPH10177938A (en) 1998-06-30 application
DE19737825A1 (en) 1998-03-12 application
GB2317270A (en) 1998-03-18 application
GB9718654D0 (en) 1997-11-05 application

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