SG157957A1 - Package for integrated circuit die - Google Patents

Package for integrated circuit die

Info

Publication number
SG157957A1
SG157957A1 SG200604978-7A SG2006049787A SG157957A1 SG 157957 A1 SG157957 A1 SG 157957A1 SG 2006049787 A SG2006049787 A SG 2006049787A SG 157957 A1 SG157957 A1 SG 157957A1
Authority
SG
Singapore
Prior art keywords
frame
flange
leads
integrated circuit
cte
Prior art date
Application number
SG200604978-7A
Other languages
English (en)
Inventor
Michael Zimmerman
Original Assignee
Interplex Qlp Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interplex Qlp Inc filed Critical Interplex Qlp Inc
Publication of SG157957A1 publication Critical patent/SG157957A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4817Conductive parts for containers, e.g. caps
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    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
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    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/047Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
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    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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    • H01L23/492Bases or plates or solder therefor
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2924/102Material of the semiconductor or solid state bodies
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    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24132Structurally defined web or sheet [e.g., overall dimension, etc.] including grain, strips, or filamentary elements in different layers or components parallel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Compositions Of Macromolecular Compounds (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
SG200604978-7A 2003-01-29 2004-01-28 Package for integrated circuit die SG157957A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US44347003P 2003-01-29 2003-01-29

Publications (1)

Publication Number Publication Date
SG157957A1 true SG157957A1 (en) 2010-01-29

Family

ID=32825334

Family Applications (4)

Application Number Title Priority Date Filing Date
SG200604978-7A SG157957A1 (en) 2003-01-29 2004-01-28 Package for integrated circuit die
SG200604979A SG160192A1 (en) 2003-01-29 2004-01-29 Package for integrated circuit die
SG200604976-1A SG158738A1 (en) 2003-01-29 2004-01-29 Package for integrated circuit die
SG200604977-9A SG157956A1 (en) 2003-01-29 2004-01-29 Package for integrated circuit die

Family Applications After (3)

Application Number Title Priority Date Filing Date
SG200604979A SG160192A1 (en) 2003-01-29 2004-01-29 Package for integrated circuit die
SG200604976-1A SG158738A1 (en) 2003-01-29 2004-01-29 Package for integrated circuit die
SG200604977-9A SG157956A1 (en) 2003-01-29 2004-01-29 Package for integrated circuit die

Country Status (8)

Country Link
US (6) US6867367B2 (fr)
EP (1) EP1627419A4 (fr)
JP (3) JP4780718B2 (fr)
KR (1) KR101025079B1 (fr)
CN (4) CN101434737B (fr)
CA (1) CA2514515C (fr)
SG (4) SG157957A1 (fr)
WO (1) WO2004068558A2 (fr)

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US20070164424A1 (en) * 2003-04-02 2007-07-19 Nancy Dean Thermal interconnect and interface systems, methods of production and uses thereof
EP1636839A2 (fr) * 2003-06-06 2006-03-22 Honeywell International Inc. Systemes d'interconnexion thermiques, procedes de production et utilisations associees
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US7259460B1 (en) * 2004-06-18 2007-08-21 National Semiconductor Corporation Wire bonding on thinned portions of a lead-frame configured for use in a micro-array integrated circuit package
US20060145317A1 (en) * 2004-12-31 2006-07-06 Brennan John M Leadframe designs for plastic cavity transistor packages
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US7336491B2 (en) * 2005-09-06 2008-02-26 Lear Corporation Heat sink
US8120153B1 (en) * 2005-09-16 2012-02-21 University Of Central Florida Research Foundation, Inc. High-temperature, wirebondless, injection-molded, ultra-compact hybrid power module
US7446411B2 (en) * 2005-10-24 2008-11-04 Freescale Semiconductor, Inc. Semiconductor structure and method of assembly
US7429790B2 (en) * 2005-10-24 2008-09-30 Freescale Semiconductor, Inc. Semiconductor structure and method of manufacture
US20070175660A1 (en) * 2006-01-27 2007-08-02 Yeung Betty H Warpage-reducing packaging design
US8565943B2 (en) * 2006-09-25 2013-10-22 Appereo Systems, LLC Fleet operations quality management system
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US6867367B2 (en) 2005-03-15
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US7736573B2 (en) 2010-06-15
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CN100461382C (zh) 2009-02-11
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