KR970072486A - 절연 게이트형 반도체 장치 및 그 제조방법 - Google Patents

절연 게이트형 반도체 장치 및 그 제조방법 Download PDF

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KR970072486A
KR970072486A KR1019960054023A KR19960054023A KR970072486A KR 970072486 A KR970072486 A KR 970072486A KR 1019960054023 A KR1019960054023 A KR 1019960054023A KR 19960054023 A KR19960054023 A KR 19960054023A KR 970072486 A KR970072486 A KR 970072486A
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semiconductor layer
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히데키 다카하시
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기다오까 다까시
미쓰비시 뎅끼 가부시끼가이샤
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Abstract

장치의 RSOA를 향상시킨다.
게이트 전극(10)은 셀영역(CR)에 형성되어 있는 p베이스층(4)에 연결되어 있고, p반도체층(13)은 셀영역 (CR)을 포위하도록 형성된다.
에미터 전극(11)은 콘택트 홀(CH)을 통해서 p반도체층(13)의 사이드 확산영역(SD)의 상면 및 사이드 확산영역 (SD)에 인접한 마진영역(MR)의 상면에 접속된다.또한, 이들 영역에 있어서, n+에미터층(5)은 형성되어 있지 않다.
전압이 높은 경우에 사이드 확산영역(SD)의 부근에서 생성되는 대부분의 에벌란쉬 홀(H)은 사이드 확산영역(SD)을 통과하지만, 약간의 애벌란쉬 홀(H)은 마진영역(MR)을 통과한 후 에미터 전극(11)에 방출된다.
이들 경로에는 n+에미터층(5)이 없기 때문에, 홀(H)의 흐름은 기생 바이폴라 트랜지스터를 도통시키지 않는다.
그 결과, RSOA가 향상된다.

Description

절연 게이트형 반도체 장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (3)

  1. 최상의 주면과 하부 주면을 규정하는 반도체 기체를 구비하는 절연 게이트형 반도체 장치에 있어서, 상기 반도체 기체는 상기 최상의 주면에 노출되어 있는 제1도전형의 제1반도체층; 상기 제1반도체층의 내부의 상기 최상의 주면의 부분에 형성된 제2도전형의 제2반도체층; 불순물을 선택적으로 확산함으로써 상기 제1반도체층 내부의 상기 최상의 주면의 부분에 형성되고, 상기 제2반도체층보다도 깊고, 상기 제2반도체층에 연결되며, 상기 제2반도체층의 주위를 둘러싸는 제3반도체층; 및 상기 제2반도체층의 내부의 상기 최상의 주면의 부분에 선택적으로 형성된 제1도전형의 제4반도체층을 구비하고 있고, 상기 반도체 기체에서, 상기 최상의 주면에 개구되고, 상기 제4 및 제2반도체층을 관통하여 상기 제1반도체층에까지 달하는 홈이 형성되어 있고, 상기 장치는 상기 홈의 내벽을 덮는 전기 절연성의 게이트 절연막; 상기 반도체 기체와의 사이에 게이트 절연막을 삽입하고 상기 홈에 매설된 게이트전극; 상기 제3반도체층을 따라 연장하도록 상기 최상의 주면상에 절연막을 통해 배치되고, 상기 게이트 전극에 전기적으로 접속된 게이트 배선; 상기 최상의 주면상에 배치되고, 상기 제2 및 제4반도체층에 전기적으로 접속된 제1주전극; 및 상기 하부 주면상에 배치되고, 상기 하부 주면에 전기적으로 접속된 제2주전극을 더 구비하고, 상기 제1주전극은 상기 제3반도체층의 내부에서 상기 제2반도체 층에 인접하는 사이드 확산영역에도 전기적으로접속되어 있고, 상기 사이드 확산영역에는 상기 제4반도체층이 형성되어 있지 않은 것을 특징으로 하는 절연 게이트 반도체 장치.
  2. 제1항에 있어서, 상기 제1주전극은 상기 제2반도체층의 내부에서 상기 사이드 확산영역으로부터 일정 거리이내의 영역으로서 규정되는 마진영역에도 전기적으로 접속되어 있고, 상기 마진영역에는 상기 제4반도체층이 형성되어 있지 않은 것을 특징으로 하는 절연 게이트형 반도체 장치.
  3. 절연 게이트형 반도체 장치의 제조방법에 있어서, (a) 최상의 주면과 하부 주면을 규정함과 동시에 상기 최상의 주면에 노출되는 제1도전형의 제1반도체층을 구비하는 반도체 기체를 준비하는 공정; (b) 상기 최상의 주면에 제2도전형의 불순물을 도입함으로써 제2도전형의 제2반도체층과 제3반도체층을 상기 제3반도체층이 상기 제2반도체층보다도 깊고, 상기 제3반도체층이 상기 제2반도체층에 연결됨과 동시에 상기 제2반도체층 주위를 포위하도록,상기 제1반도체층의 상기 최상의 주면의 부분에 형성하는 공정; (c) 상기 최상의 주면에 선택적으로 제1도전형의 불순물을 도입함으로써 상기 제3반도체층 내부에서 상기 제2반도체층에 인접한 사이드 확산영역을 제외하고 상기 제2반도체층의 상기 최상의 주면의 부분에 선택적으로 제1도전형이 제4반도체층을 형성하는 공정; (d) 상기 최상의 주면으로부터 선택적으로 에칭함으로써, 상기 제4 및 제2반도체층을 관통하여 상기 제1반도체층에 달하는 홈을 상기 반도체 기체에 선택적으로 형성하는 공정; (e) 상기 홈의 내벽 및 상기 반도체 기체의 상면을 덮는 절연막을 형성하는 공정; (f) 상기 절연막을 덮도록 도전층을 형성하는 공정; (g)상기 홈의 내부와 상기 제3반도체층을 따른 부분을 남기도록, 상기 도전층을 선택적으로 제거함으로써, 게이트 전극과 게이트 배선을 형성하는 공정; (h) 상기 제2 및 제4반도체층에 전기적으로 접속되고, 또 상기 사이드 확산영역에도 전기적으로 접속되는 상기 제1주전극을 상기 최상의 주면상에 형성하는 공정; 및 (i) 상기 하부주면에 전기적으로 접속되는 제2주전극을 형성하는 공정을 구비하는 것을 특징으로 하는 절연 게이트형 반도체 장치의 제조방법.
    ※참고사항: 최초출원 내용에 의하여 공개하는 것임.
KR1019960054023A 1996-04-01 1996-11-14 절연 게이트형 반도체 장치의 제조방법 KR100272057B1 (ko)

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JP07867496A JP3410286B2 (ja) 1996-04-01 1996-04-01 絶縁ゲート型半導体装置

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KR1020000012431A KR100353605B1 (ko) 1996-04-01 2000-03-13 절연 게이트형 반도체 장치
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