CN113632238A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN113632238A
CN113632238A CN201980094734.1A CN201980094734A CN113632238A CN 113632238 A CN113632238 A CN 113632238A CN 201980094734 A CN201980094734 A CN 201980094734A CN 113632238 A CN113632238 A CN 113632238A
Authority
CN
China
Prior art keywords
diode
layer
type
semiconductor substrate
igbt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201980094734.1A
Other languages
English (en)
Other versions
CN113632238B (zh
Inventor
木村光太
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN113632238A publication Critical patent/CN113632238A/zh
Application granted granted Critical
Publication of CN113632238B publication Critical patent/CN113632238B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

IGBT(2)、二极管(3)以及阱区域(4)设置于半导体衬底(1)。IGBT(2)具有在半导体衬底(1)的第1主面设置的沟槽栅极(6)。二极管(3)具有在半导体衬底(1)的第1主面设置的p型阳极层(19)。阱区域(4)设置于半导体衬底(1)的第1主面，具有比p型阳极层(19)浓度高、比沟槽栅极(6)深度深的p型阱层(21)。沟槽栅极(6)的末端设置于阱区域(4)，被p型阱层(21)包围。二极管(3)设置于比IGBT(2)更靠半导体衬底(1)的外侧处。阱区域(4)设置于比二极管(3)更靠半导体衬底(1)的外侧处。

Description

半导体装置
技术领域
本发明涉及在相同半导体衬底设置有IGBT和二极管的半导体装置。
背景技术
作为电力用半导体元件的功率器件在家电产品、电动汽车以及铁路这样的领域乃至作为可再生能源而备受瞩目的太阳能发电或者风力发电的领域被广泛地使用。大多由功率器件构建逆变器电路，对感应电动机等电感性负载进行驱动。在这种情况下，需要用于对通过电感性负载的反电动势产生的电流进行续流的续流二极管(以下记作二极管)，通常的逆变器电路具有多个绝缘栅型双极晶体管(以下记作IGBT)和多个二极管。但是，强烈期望逆变器装置的小型轻量化和低成本化，不希望搭载多个半导体装置。作为其解决方法之一，正在推进将IGBT和二极管一体化的反向导通型IGBT(以下记作RC-IGBT)的开发。提出了为了减小RC-IGBT的芯片面积，在IGBT的外侧配置有二极管的装置(例如，参照专利文献1)。
专利文献1：日本特开2018-46187号公报
发明内容
但是，就以往的装置而言，阱区域配置于IGBT与二极管之间，其中，在该阱区域设置有沟槽栅极的末端。因此，二极管被形成有高浓度的p+型层的阱区域和末端区域夹着。因此，有可能由于二极管动作时的电流集中而使恢复电流增大，半导体装置被破坏。
本发明就是为了解决上述这样的课题而提出的，其目的在于得到能够防止恢复破坏的半导体装置。
本发明涉及的半导体装置的特征在于，具有：半导体衬底，其具有彼此相反侧的第1主面和第2主面；以及IGBT、二极管以及阱区域，它们设置于所述半导体衬底，所述IGBT具有在所述半导体衬底的所述第1主面设置的沟槽栅极，所述二极管具有在所述半导体衬底的所述第1主面设置的p型阳极层，所述阱区域设置于所述半导体衬底的所述第1主面，具有比所述p型阳极层浓度高、比所述沟槽栅极深度深的p型阱层，所述沟槽栅极的末端设置于所述阱区域，被所述p型阱层包围，所述二极管设置于比所述IGBT更靠所述半导体衬底的外侧处，所述阱区域设置于比所述二极管更靠所述半导体衬底的外侧处。
发明的效果
在本发明中，阱区域设置于比二极管更靠半导体衬底的外侧处。因此，二极管只受阱区域的p型阱层的影响，不受末端区域的高浓度的p+型层的影响，因此，能够防止恢复破坏。
附图说明
图1是表示实施方式1涉及的半导体装置的俯视图。
图2是将图1的区域A放大的俯视图。
图3是沿图2的I-II的IGBT的剖视图。
图4是沿图2的III-IV的二极管的剖视图。
图5是沿图2的V-VI的剖视图。
图6是沿图1的I-II的剖视图。
图7是表示芯片面积与热阻的关系的图。
图8是表示单元分割数与热阻的关联的图。
图9是表示热解析模拟出的RC-IGBT的温度分布的图。
图10是表示热解析模拟出的单体的IGBT的温度分布的图。
图11是表示实施方式2涉及的半导体装置的二极管的剖视图。
图12是表示实施方式3涉及的半导体装置的剖视图。
图13是表示实施方式4涉及的半导体装置的剖视图。
具体实施方式
参照附图，对实施方式涉及的半导体装置进行说明。对相同或者相应的结构要素标注相同的标号，有时省略重复说明。
实施方式1.
图1是表示实施方式1涉及的半导体装置的俯视图。该半导体装置是在相同半导体衬底1设置有IGBT 2、二极管3、阱区域4以及末端区域5的RC-IGBT。IGBT 2设置于芯片中央附近，二极管3设置于比IGBT 2更靠半导体衬底1的外侧处。阱区域4设置于比二极管3更靠半导体衬底1的外侧处。在阱区域4的更外侧设置有末端区域5。
图2是将图1的区域A放大的俯视图。由多晶硅构成的多个沟槽栅极6平行地排列而横穿IGBT 2和二极管3，全部沟槽栅极6的末端都设置于阱区域4。由Al或者AlSi构成的栅极配线7与多个沟槽栅极6连接，设置于阱区域4。此外，在图2中，省略了栅极配线7以外的衬底之上的电极和绝缘膜。
图3是沿图2的I-II的IGBT的剖视图。半导体衬底1具有彼此相反侧的第1主面和第2主面。在半导体衬底1的n-型漂移层8的第1主面侧设置有p型基极层9。在p型基极层9的表面设置有n+型发射极层10和p+型接触层11。在将p型基极层9和n+型发射极层10贯通的沟槽内隔着栅极绝缘膜12而设置有沟槽栅极6。由SiO2构成的层间膜13设置于沟槽栅极6之上。由Al或者AlSi构成的发射极电极14经由由Ti构成的阻挡金属15而与n+型发射极层10和p+型接触层11连接。这样，在IGBT 2的第1主面设置有MOSFET构造。在n-型漂移层8的第2主面侧依次设置有n型缓冲层16和p+型集电极层17。由Al或者AlSi构成的集电极(collector)电极(electrode)18与p+型集电极层17连接。
图4是沿图2的III-IV的二极管的剖视图。在半导体衬底1的n-型漂移层8的第1主面侧设置有p型阳极层19。这样，在二极管3的第1主面设置有阳极构造。p型阳极层19与IGBT2的p型基极层9同时形成，杂质浓度和深度相同。在二极管3也形成有沟槽栅极6。在第2主面设置有n+型阴极层20以取代IGBT 2的p+型接触层11。
图5是沿图2的V-VI的剖视图。在阱区域4，在半导体衬底1的第1主面设置有p+型阱层21。p+型阱层21比p型阳极层19杂质浓度高，比沟槽栅极6深度深。沟槽栅极6的末端被p+型阱层21包围。沟槽栅极6的升高部22在阱区域4与栅极配线7连接。在阱区域4，在半导体衬底1的第2主面设置有p+型层23。p+型层23的杂质浓度是与IGBT 2的p+型集电极层17相等或者与其接近的浓度。此外，第2主面的p+型集电极层17与n+型阴极层20的边界和IGBT 2与二极管3的边界相同，但不限于此，边界也可以不一致。
图6是沿图1的I-II的剖视图。在图1的IGBT 2的上下2条边，与沟槽栅极6平行地设置有二极管3和阱区域4。因此，在二极管3和阱区域4未设置沟槽栅极6，在阱区域4未设置栅极配线7。
此外，在本实施方式中，二极管3以将IGBT 2的四周包围的方式而配置，但不限于此，只要以在比IGBT 2更靠外侧处与阱区域4接触的方式配置二极管3即可。例如，也可以将二极管3仅配置于IGBT 2的1条边、2条边或者3条边，也可以不是连续的，而是隔开间隔地配置。另外，也可以在IGBT 2的p型基极层9和二极管3的p型阳极层19的正下方设置n型载流子积蓄区域。
在IGBT和二极管是单独的元件的情况下，元件自身的热阻仅由芯片面积和厚度决定。图7是表示芯片面积与热阻的关系的图。为了改善热阻，需要增大芯片面积，成为逆变器装置的小型轻量化和低成本化的阻碍。与此相对，本实施方式涉及的半导体装置是IGBT 2和二极管3形成于相同半导体衬底1的RC-IGBT。因此，在IGBT 2进行动作时，二极管3有助于散热，在二极管进行动作时，IGBT 2有助于散热。因此，与IGBT 2和二极管3是单独的元件的情况相比，能够改善热阻。
通过IGBT 2和二极管3的配置的方式也能够对热阻进行控制。图8是表示单元分割数与热阻的关联的图。如本实施方式所示，在IGBT 2和二极管3为交替地配置的条带构造的情况下，能够通过增加分割数而改善热阻。
图9是表示热解析模拟出的RC-IGBT的温度分布的图。图10是表示热解析模拟出的单体的IGBT的温度分布的图。与单体的IGBT相比，RC-IGBT能够确认到热的分散。但是，可知，由于与相邻的区域之间的热干涉，与单体的IGBT或者二极管同样地，就RC-IGBT而言，芯片中央也成为最高温。模块构造大多由通电时的最高到达温度Tjmax决定，在芯片设计时不希望热在芯片中央集中。
在以减小RC-IGBT整体的损耗的方式而进行了布局设计的情况下，大多与二极管3的有效面积相比，IGBT 2的有效面积增大。由于二极管3的有效面积减小，热在芯片中难以扩散，二极管3的热阻比设想更差。因此，将热负荷高的二极管3设置于比IGBT 2更靠外侧处，远离温度变高的芯片中心部。
这里，当在二极管3不形成沟槽栅极6，在IGBT 2与二极管3的边界或者在IGBT 2内设置沟槽栅极6的末端时，栅极电容减小，有利于通断特性。但是，如果沟槽栅极6的末端设置于杂质浓度低的二极管3的p型阳极层19或者IGBT 2的p型基极层9，则耐压显著地下降。因此，在本实施方式中，沟槽栅极6横穿IGBT 2和二极管3，沟槽栅极6的末端设置于阱区域4。通过在阱区域4设置比沟槽栅极6深、比二极管3的p型阳极层19杂质浓度高的p+型阱层21而将沟槽栅极6的末端包围，从而能够防止耐压的下降。该构造仅设置于芯片的4条边中的IGBT 2和二极管3的边界面与沟槽栅极6的方向垂直的边。在两者平行的边处，也可以不在二极管3和阱区域4设置沟槽栅极6。
以往，二极管被形成有高浓度的p+型层的阱区域和末端区域夹着，因此，存在由于二极管动作时的电流集中而产生恢复破坏这一问题。与此相对，在本实施方式中，阱区域4设置于比二极管3更靠半导体衬底1的外侧处。因此，二极管3只受阱区域4的p+型阱层21的影响，不受末端区域的影响，因此能够防止恢复破坏。
另外，二极管3与在通电时不发热的阱区域4接触。由此，有助于二极管3的散热的面积扩大，能够降低面积小、热负荷高的二极管3的热阻。因此，能够使在通电时在芯片中央集中的热向外侧分散。
如果阱区域4的p+型阱层21作为二极管而进行动作，则恢复时的电流增大，导致损耗的恶化和恢复破坏。因此，在阱区域4，在半导体衬底1的第2主面设置p+型层23。由此，能够抑制阱区域4的二极管动作。
实施方式2.
图11是表示实施方式2涉及的半导体装置的二极管的剖视图。在二极管3的沟槽栅极6的侧旁设置有n+型发射极层10。此外，也可以在阱区域4的沟槽栅极6的侧旁也设置n+型发射极层10。
通过在二极管3的恢复动作时对沟槽栅极6施加电压，从而能够在p型阳极层19内形成n反转层。由此，从p型阳极层19注入的空穴受到抑制，能够减小恢复电流。由于p+型阱层21比p型阳极层19浓度高，恢复电流变大，因此，本实施方式特别有效。其它结构及效果与实施方式1相同。
实施方式3.
图12是表示实施方式3涉及的半导体装置的剖视图。剖面部位与实施方式1的图6相同。半导体衬底1的第2主面侧的n+型阴极层20与p+型层23的边界配置于比第1主面侧的p型阳极层19与p+型阱层21的边界更靠半导体衬底1的中心侧处。
在实施方式1中，通过在阱区域4，在半导体衬底1的第2主面侧设置p+型层23，从而防止了阱区域4的二极管动作。但是，在二极管3与阱区域4的边界部分处，由于第1主面侧的阱区域4的高浓度的p+型层23的影响，恢复电流变大，损耗恶化。与此相对，在本实施方式中，通过使第2主面侧的n+型阴极层20与p+型层23的边界向半导体衬底1的中心侧偏移，从而来自二极管3的第2主面侧的电子不再流入至阱区域4，能够减小恢复电流。其它结构及效果与实施方式1相同。
实施方式4.
图13是表示实施方式4涉及的半导体装置的剖视图。剖面部位与实施方式1的图6相同。在二极管3的p型阳极层19和阱区域4的p+型阱层21的下方设置有通过氦或者质子等的粒子束照射而局部地存在晶体缺陷的寿命控制层24。
如上所述，在实施方式1中，在二极管3与阱区域4的边界部分处，由于第1主面侧的阱区域4的高浓度的p+型阱层21的影响，恢复电流变大，损耗恶化。与此相对，在本实施方式中，通过在二极管3的p型阳极层19和阱区域4的p+型阱层21的下方形成载流子的寿命短的寿命控制层24，从而能够减小恢复电流。其它结构及效果与实施方式1相同。此外，也可以将实施方式2-4的结构彼此组合。
此外，半导体衬底1不限于由硅形成，也可以由与硅相比带隙大的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料或者金刚石。由这样的宽带隙半导体形成的半导体装置的耐电压性和容许电流密度高，因此能够小型化。通过使用该小型化后的半导体装置，从而组装有该半导体装置的半导体模块也能够小型化。另外，半导体装置的耐热性高，因此，能够使散热器的散热鳍片小型化，能够使水冷部空冷化，因而能够使半导体模块进一步小型化。另外，半导体装置的电力损耗低且高效，因此，能够使半导体模块高效化。
标号的说明
1 半导体衬底，2 IGBT，3 二极管，4 阱区域，6 沟槽栅极，10 n+型发射极层，19 p型阳极层，20 n+型阴极层，21 p型阱层，23 p+型层，24 寿命控制层

Claims (7)

1.一种半导体装置，其特征在于，具有：
半导体衬底，其具有彼此相反侧的第1主面和第2主面；以及
IGBT、二极管以及阱区域，它们设置于所述半导体衬底，
所述IGBT具有在所述半导体衬底的所述第1主面设置的沟槽栅极，
所述二极管具有在所述半导体衬底的所述第1主面设置的p型阳极层，
所述阱区域设置于所述半导体衬底的所述第1主面，具有比所述p型阳极层浓度高、比所述沟槽栅极深度深的p型阱层，
所述沟槽栅极的末端设置于所述阱区域，被所述p型阱层包围，
所述二极管设置于比所述IGBT更靠所述半导体衬底的外侧处，
所述阱区域设置于比所述二极管更靠所述半导体衬底的外侧处。
2.根据权利要求1所述的半导体装置，其特征在于，
所述二极管与所述阱区域接触。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述阱区域具有在所述半导体衬底的所述第2主面设置的p型层。
4.根据权利要求1至3中任一项所述的半导体装置，其特征在于，
在所述二极管，在所述沟槽栅极的侧旁设置有n型发射极层。
5.根据权利要求3所述的半导体装置，其特征在于，
所述二极管具有在所述半导体衬底的所述第2主面设置的n型阴极层，
所述第2主面侧的所述n型阴极层与所述p型层的边界配置于比所述第1主面侧的所述p型阳极层与所述p型阱层的边界更靠所述半导体衬底的中心侧处。
6.根据权利要求1至5中任一项所述的半导体装置，其特征在于，
在所述二极管的所述p型阳极层和所述阱区域的所述p型阱层的下方设置有寿命控制层。
7.根据权利要求1至6中任一项所述的半导体装置，其特征在于，
所述半导体衬底由宽带隙半导体形成。
CN201980094734.1A 2019-04-01 2019-04-01 半导体装置 Active CN113632238B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/014449 WO2020202430A1 (ja) 2019-04-01 2019-04-01 半導体装置

Publications (2)

Publication Number Publication Date
CN113632238A true CN113632238A (zh) 2021-11-09
CN113632238B CN113632238B (zh) 2024-08-02

Family

ID=72666189

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980094734.1A Active CN113632238B (zh) 2019-04-01 2019-04-01 半导体装置

Country Status (5)

Country Link
US (1) US11973132B2 (zh)
JP (1) JP7192968B2 (zh)
CN (1) CN113632238B (zh)
DE (1) DE112019007159T5 (zh)
WO (1) WO2020202430A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7395844B2 (ja) * 2019-05-14 2023-12-12 富士電機株式会社 半導体装置および製造方法
US20220416077A1 (en) * 2021-06-24 2022-12-29 Wolfspeed, Inc. Power semiconductor die with improved thermal performance
WO2023189059A1 (ja) * 2022-03-31 2023-10-05 ローム株式会社 半導体装置

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10163482A (ja) * 1996-11-27 1998-06-19 Denso Corp 絶縁分離型半導体装置
JP2011134951A (ja) * 2009-12-25 2011-07-07 Toyota Motor Corp 半導体装置
CN102959705A (zh) * 2010-07-01 2013-03-06 株式会社电装 半导体器件
CN202796960U (zh) * 2012-07-12 2013-03-13 宁波比亚迪半导体有限公司 一种具有内置二极管的igbt结构
US20140167150A1 (en) * 2012-12-14 2014-06-19 Samsung Electro-Mechanics Co., Ltd. Power semiconductor device and method of manufacturing the same
CN106688083A (zh) * 2014-09-29 2017-05-17 丰田自动车株式会社 半导体装置
US20170250269A1 (en) * 2014-07-14 2017-08-31 Denso Corporation Semiconductor device and manufacturing method of the same
US20180294259A1 (en) * 2017-04-06 2018-10-11 Fuji Electric Co., Ltd. Semiconductor device
CN109314143A (zh) * 2016-06-14 2019-02-05 株式会社电装 半导体装置
CN109314141A (zh) * 2016-12-08 2019-02-05 富士电机株式会社 半导体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3410286B2 (ja) * 1996-04-01 2003-05-26 三菱電機株式会社 絶縁ゲート型半導体装置
JP2013026534A (ja) 2011-07-25 2013-02-04 Toyota Central R&D Labs Inc 半導体装置
DE112013007576B4 (de) 2013-11-05 2022-02-03 Denso Corporation Halbleitereinrichtung
JP6801324B2 (ja) 2016-09-15 2020-12-16 富士電機株式会社 半導体装置
JP6804379B2 (ja) 2017-04-24 2020-12-23 三菱電機株式会社 半導体装置

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10163482A (ja) * 1996-11-27 1998-06-19 Denso Corp 絶縁分離型半導体装置
JP2011134951A (ja) * 2009-12-25 2011-07-07 Toyota Motor Corp 半導体装置
CN102959705A (zh) * 2010-07-01 2013-03-06 株式会社电装 半导体器件
CN202796960U (zh) * 2012-07-12 2013-03-13 宁波比亚迪半导体有限公司 一种具有内置二极管的igbt结构
US20140167150A1 (en) * 2012-12-14 2014-06-19 Samsung Electro-Mechanics Co., Ltd. Power semiconductor device and method of manufacturing the same
US20170250269A1 (en) * 2014-07-14 2017-08-31 Denso Corporation Semiconductor device and manufacturing method of the same
CN106688083A (zh) * 2014-09-29 2017-05-17 丰田自动车株式会社 半导体装置
CN109314143A (zh) * 2016-06-14 2019-02-05 株式会社电装 半导体装置
CN109314141A (zh) * 2016-12-08 2019-02-05 富士电机株式会社 半导体装置
US20180294259A1 (en) * 2017-04-06 2018-10-11 Fuji Electric Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
US11973132B2 (en) 2024-04-30
DE112019007159T5 (de) 2021-12-16
US20220109062A1 (en) 2022-04-07
CN113632238B (zh) 2024-08-02
WO2020202430A1 (ja) 2020-10-08
JP7192968B2 (ja) 2022-12-20
JPWO2020202430A1 (ja) 2021-12-16

Similar Documents

Publication Publication Date Title
US9257543B2 (en) Reverse-conducting insulated gate bipolar transistor and diode with one structure semiconductor device
JP4185157B2 (ja) 半導体素子及び電気機器
JP4167294B2 (ja) 半導体素子及び電気機器
CN110391225B (zh) 半导体装置
CN113632238B (zh) 半导体装置
US11398769B2 (en) Semiconductor device comprising switching elements and capacitors
JP5135666B2 (ja) 電力変換装置
US20230106654A1 (en) Semiconductor device and method of manufacturing semiconductor device
JP6540563B2 (ja) 半導体装置
JP2021052078A (ja) 半導体装置及びその製造方法
CN115084255A (zh) 半导体装置
JP6843952B2 (ja) 半導体装置の製造方法
US11374091B2 (en) Semiconductor device
WO2022224840A1 (ja) 半導体装置及びそれを用いた電力変換装置、半導体装置の製造方法
US12002730B2 (en) Semiconductor module
JP7521620B2 (ja) 半導体装置
US11527449B2 (en) Semiconductor apparatus
JP2024071984A (ja) 半導体装置
CN110797404B (zh) 一种rc-igbt半导体器件
CN114284344B (zh) 一种优化电流分布的碳化硅结势垒肖特基二极管
CN116344619A (zh) 提高SiC MOSFET抗浪涌能力的半导体器件
CN118016705A (zh) 一种逆导型绝缘栅双极晶体管

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant