JP5641131B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP5641131B2 JP5641131B2 JP2013504780A JP2013504780A JP5641131B2 JP 5641131 B2 JP5641131 B2 JP 5641131B2 JP 2013504780 A JP2013504780 A JP 2013504780A JP 2013504780 A JP2013504780 A JP 2013504780A JP 5641131 B2 JP5641131 B2 JP 5641131B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 230000015556 catabolic process Effects 0.000 claims description 93
- 238000009792 diffusion process Methods 0.000 claims description 67
- 239000000758 substrate Substances 0.000 claims description 51
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- 238000000034 method Methods 0.000 claims description 11
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Description
図1は、本発明の半導体装置の実施の形態1にかかる縦型トレンチゲート型パワーICの要部断面図である。図1においては、本発明の複合半導体装置の実施の形態1として、縦型トレンチゲート型パワーIC100の要部断面図を示す。
図8は、本発明の半導体装置の実施の形態2にかかる縦型トレンチゲート型パワーICの変形例を示す要部断面図である。実施の形態2は、実施の形態1の変形例であり、実施の形態1との相違点は、外部からの電荷が耐圧に与える影響を抑える工夫として、図8に示すように、p型サステイン領域50とp-型拡散領域4bが重なる領域を増やしたことである。
図9は、本発明の半導体装置の実施の形態3にかかる縦型トレンチゲート型パワーICの変形例を示す要部断面図である。実施の形態3は実施例2の変形例であり、実施の形態2との相違点は、外部からの電荷が耐圧に与える影響を抑える工夫として、図9に示すように、p型サステイン領域50の表面に、p+型コンタクト領域10を追加で形成したことである。このようにすれば、活性領域の端部のトレンチからLOCOS酸化膜11cまでの区間におけるp型領域の表面濃度を、より一層増加させることができるので、耐圧に対する外部からの電荷の影響を防ぐことが可能となる。
図7は、本発明の半導体装置の実施の形態4にかかる縦型トレンチゲート型パワーICの変形例を示す平面図である。本発明の半導体装置の実施の形態4にかかる縦型トレンチゲート型パワーICは、縦型トレンチゲート型MOSFET素子部30を取り囲むように終端耐圧領域23が形成され、さらに半導体基板上に素子分離領域90としてのLOCOS酸化膜11aを介して、制御用の横型nチャネルMOSFET素子部22と併置されている。実施の形態1との相違点は、終端耐圧領域23は縦型トレンチゲート型MOSFET素子部30のみを取り囲むようにしていることである。制御用の横型nチャネルMOSFET素子部22の耐圧が、図2に示すような従来型の終端耐圧領域49で十分高い値を確保できる場合は、このように、縦型トレンチゲート型MOSFET素子部30のみ、終端耐圧領域23にて電界強度を緩和することも可能である。
図4に本発明の実施の形態5を示す。図4は前記図1の出力段半導体素子である縦型トレンチゲート型MOSFET素子部30のn+型基板2の裏面に、さらにp+型半導体層25(p+型コレクタ層)を追加することにより、出力段半導体素子を縦型トレンチゲート型IGBT24(絶縁ゲートバイポーラトランジスタ)としたものである。
2、32、52 n+型基板
3、33、53 n-型エピタキシャル層
4a、34 p-型ウェル拡散領域
4b、54 p-型拡散領域
5、35、55 p型ベース領域
50 p型サステイン領域
6a、6b、36、56 ゲート電極
7a、7b、37、57 ゲート酸化膜
8b、38b、58 n+型ソース領域
8a、38a n+型ドレイン領域
39 ベースコンタクト領域
9、10、60 p+型コンタクト領域
11a、11b、11c LOCOS酸化膜
41、61 LOCOS酸化膜
13、15、65 ソース電極
14 ベース電極
16、66 金属膜フィールドプレート
6c ポリシリコン膜フィールドプレート
17a、17b 層間絶縁膜
30 縦型トレンチゲート型MOSFET素子部
21、48、68 活性領域
22 制御用の横型nチャネルMOSFET素子部
23、49、69 終端耐圧領域
24 縦型トレンチゲート型IGBT
25 p+型半導体層
18、40 ウェル接合
19 主接合
70 p--型リサーフ領域
90 素子分離領域
100 縦型トレンチゲート型パワーIC
Claims (5)
- 第1導電型の半導体基板の第一の主面側に形成された第1導電型の主ドレイン領域と、 前記半導体基板の第二の主面側の表面に選択的に形成された第2導電型のベース領域と、前記ベース領域の表面に選択的に形成された第1導電型の主ソース領域と、前記ベース領域の表面から前記ベース領域と前記主ソース領域を貫通して前記半導体基板に到達するトレンチと、絶縁性の膜からなる第一絶縁膜を介して前記トレンチにゲート電極が埋め込まれたトレンチMOSゲートと、を有する縦型トレンチMOSゲート型半導体素子部と、
前記半導体基板の第二の主面側の表面に形成されて前記第一絶縁膜よりも厚い第二絶縁膜を備えた素子分離領域を介して前記縦型トレンチMOSゲート型半導体素子部に隣接し、前記半導体基板の第二の主面側の表面に前記半導体基板とpn接合を形成する第2導電型のウェル拡散領域を備え、前記ウェル拡散領域の表面上に前記第二絶縁膜よりも厚さの薄い第三絶縁膜を介して形成された制御用ゲート電極を備え、前記ウェル拡散領域の表面にて前記制御用ゲート電極を挟むように第1導電型制御ドレイン領域と第1導電型制御ソース領域が設けられ、前記縦型トレンチMOSゲート型半導体素子部を制御する制御用半導体素子部と、
前記半導体基板の第二の主面側の表面に前記第二絶縁膜を備え、前記縦型トレンチMOSゲート型半導体素子部を取り巻くか、もしくは前記縦型トレンチMOSゲート型半導体素子部と前記制御用半導体素子部の両素子部を共通に取り巻く終端耐圧領域と、を備える半導体装置において、
前記終端耐圧領域が、前記第二絶縁膜と、前記縦型トレンチMOSゲート型半導体素子部の端部のトレンチに外接する、前記ベース領域と同時に形成される第2導電型のサステイン領域と、前記サステイン領域の外側に接して配置される、前記ウェル拡散領域と同時に形成される第2導電型の第1領域と、を備え、
前記第1領域は、前記ベース領域より接合深さが深くて低不純物濃度であり、
前記サステイン領域は、前記第1領域より接合深さが浅くて高不純物濃度であり、
前記ウェル拡散領域は、前記ベース領域および前記サステイン領域よりも接合深さが深くて低不純物濃度であり、
前記終端耐圧領域および前記ウェル拡散領域のアバランシェ耐圧が、前記縦型トレンチMOSゲート型半導体素子部のアバランシェ耐圧よりも高いことを特徴とする半導体装置。 - 第1導電型の半導体基板の第一の主面側に形成された第1導電型の主ドレイン領域と、
前記半導体基板の第二の主面側の表面に選択的に形成された第2導電型のベース領域と、前記ベース領域の表面に選択的に形成された第1導電型の主ソース領域と、前記ベース領域の表面から前記ベース領域と前記主ソース領域を貫通して前記半導体基板に到達するトレンチと、絶縁性の膜からなる第一絶縁膜を介して前記トレンチにゲート電極が埋め込まれたトレンチMOSゲートと、を有する縦型トレンチMOSゲート型半導体素子部と、
前記半導体基板の第二の主面側の表面に形成されて前記第一絶縁膜よりも厚い第二絶縁膜を備えた素子分離領域を介して前記縦型トレンチMOSゲート型半導体素子部に隣接し、前記半導体基板の第二の主面側の表面に前記半導体基板とpn接合を形成する第2導電型のウェル拡散領域を備え、前記ウェル拡散領域の表面上に前記第二絶縁膜よりも厚さの薄い第三絶縁膜を介して形成された制御用ゲート電極を備え、前記ウェル拡散領域の表面にて前記制御用ゲート電極を挟むように第1導電型制御ドレイン領域と第1導電型制御ソース領域が設けられ、前記縦型トレンチMOSゲート型半導体素子部を制御する制御用半導体素子部と、
前記半導体基板の第二の主面側の表面に前記第二絶縁膜を備え、前記縦型トレンチMOSゲート型半導体素子部を取り巻くか、もしくは前記縦型トレンチMOSゲート型半導体素子部と前記制御用半導体素子部の両素子部を共通に取り巻く終端耐圧領域と、を備える半導体装置において、
前記終端耐圧領域が、前記第二絶縁膜と、前記縦型トレンチMOSゲート型半導体素子部の端部のトレンチに外接する第2導電型のサステイン領域と、前記サステイン領域の外側に接して配置される第2導電型の第1領域と、を備え、
前記第1領域は、前記ベース領域より接合深さが深くて低不純物濃度であり、
前記サステイン領域は、前記第1領域より接合深さが浅くて高不純物濃度であり、前記ベース領域と同じ接合深さおよび同じ不純物濃度を有し、
前記ウェル拡散領域は、前記ベース領域および前記サステイン領域よりも接合深さが深くて低不純物濃度であり、前記第1領域と同じ接合深さおよび同じ不純物濃度を有し、
前記終端耐圧領域および前記ウェル拡散領域のアバランシェ耐圧が、前記縦型トレンチMOSゲート型半導体素子部のアバランシェ耐圧よりも高いことを特徴とする半導体装置。 - 前記終端耐圧領域が、前記第二絶縁膜上に載置されるフィールドプレートを有することを特徴とする請求項1または2に記載の半導体装置。
- 前記縦型トレンチMOSゲート型半導体素子部が、前記第一の主面側にて前記主ドレイン領域と接する第2導電型コレクタ層を備えたIGBTであることを特徴とする請求項1〜3のいずれか一つに記載の半導体装置。
- 第1導電型の半導体基板の第一の主面側に形成された第1導電型の主ドレイン領域と、 前記半導体基板の第二の主面側の表面に選択的に形成された第2導電型のベース領域と、前記ベース領域の表面に選択的に形成された第1導電型の主ソース領域と、前記ベース領域の表面から前記ベース領域と前記主ソース領域を貫通して前記半導体基板に到達するトレンチと、絶縁性の膜からなる第一絶縁膜を介して前記トレンチにゲート電極が埋め込まれたトレンチMOSゲートと、を有する縦型トレンチMOSゲート型半導体素子部と、
前記半導体基板の第二の主面側の表面に形成されて前記第一絶縁膜よりも厚い第二絶縁膜を備えた素子分離領域を介して前記縦型トレンチMOSゲート型半導体素子部に隣接し、前記半導体基板の第二の主面側の表面に前記半導体基板とpn接合を形成する第2導電型のウェル拡散領域を備え、前記ウェル拡散領域の表面上に前記第二絶縁膜よりも厚さの薄い第三絶縁膜を介して形成された制御用ゲート電極を備え、前記ウェル拡散領域の表面にて前記制御用ゲート電極を挟むように第1導電型制御ドレイン領域と第1導電型制御ソース領域が設けられ、前記縦型トレンチMOSゲート型半導体素子部を制御する制御用半導体素子部と、
前記半導体基板の第二の主面側の表面に前記第二絶縁膜を備え、前記縦型トレンチMOSゲート型半導体素子部を取り巻くか、もしくは前記縦型トレンチMOSゲート型半導体素子部と前記制御用半導体素子部の両素子部を共通に取り巻く終端耐圧領域と、を備える半導体装置であって、
前記終端耐圧領域が、前記第二絶縁膜と、前記縦型トレンチMOSゲート型半導体素子部の端部のトレンチに外接する第2導電型のサステイン領域と、前記サステイン領域の外側に接して配置される第2導電型の第1領域と、を備え、
前記第1領域は、前記ベース領域より接合深さが深くて低不純物濃度であり、
前記サステイン領域は、前記第1領域より接合深さが浅くて高不純物濃度であり、
前記ウェル拡散領域は、前記ベース領域および前記サステイン領域よりも接合深さが深くて低不純物濃度であり、
前記終端耐圧領域および前記ウェル拡散領域のアバランシェ耐圧が、前記縦型トレンチMOSゲート型半導体素子部のアバランシェ耐圧よりも高い半導体装置を製造するにあたり、
前記半導体装置が備える第1領域を、当該半導体装置が備えるウェル拡散領域と同時に形成し、前記半導体装置が備えるサステイン領域を、当該半導体装置が備えるベース領域と同時に形成することを特徴とする半導体装置の製造方法。
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2012
- 2012-03-15 WO PCT/JP2012/056777 patent/WO2012124786A1/ja active Application Filing
- 2012-03-15 EP EP12757869.8A patent/EP2688102A4/en not_active Ceased
- 2012-03-15 JP JP2013504780A patent/JP5641131B2/ja active Active
- 2012-03-15 CN CN201280005804.XA patent/CN103329268B/zh not_active Expired - Fee Related
- 2012-03-15 US US13/980,046 patent/US9209296B2/en active Active
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2015
- 2015-10-21 US US14/919,084 patent/US9502496B2/en active Active
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US10418479B2 (en) | 2017-06-19 | 2019-09-17 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
US10916624B2 (en) | 2018-05-17 | 2021-02-09 | Fuji Electric Co., Ltd. | Semiconductor integrated circuit and method of manufacturing the same |
US11502164B2 (en) | 2018-05-17 | 2022-11-15 | Fuji Electric Co., Ltd. | Method of manufacturing semiconductor integrated circuit |
US11145552B2 (en) | 2019-02-15 | 2021-10-12 | Fuji Electric Co., Ltd. | Method of manufacturing semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
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WO2012124786A1 (ja) | 2012-09-20 |
EP2688102A4 (en) | 2014-09-03 |
JPWO2012124786A1 (ja) | 2014-07-24 |
US20140008718A1 (en) | 2014-01-09 |
CN103329268A (zh) | 2013-09-25 |
US20160043166A1 (en) | 2016-02-11 |
EP2688102A1 (en) | 2014-01-22 |
CN103329268B (zh) | 2016-06-29 |
US9209296B2 (en) | 2015-12-08 |
US9502496B2 (en) | 2016-11-22 |
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