KR910019200A - 반도체장치 및 그의 제조방법 - Google Patents

반도체장치 및 그의 제조방법 Download PDF

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Publication number
KR910019200A
KR910019200A KR1019910006767A KR910006767A KR910019200A KR 910019200 A KR910019200 A KR 910019200A KR 1019910006767 A KR1019910006767 A KR 1019910006767A KR 910006767 A KR910006767 A KR 910006767A KR 910019200 A KR910019200 A KR 910019200A
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South Korea
Prior art keywords
semiconductor device
memory
semiconductor
chip
chips
Prior art date
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KR1019910006767A
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English (en)
Other versions
KR100240321B1 (ko
Inventor
토시유키 사쿠다
마사미치 이사하라
카즈야 이토
사토시 오구치
가미 겐 무라
이치로 안죠오
야후노리 야마구치
야후히로 가사마
테츠 우다가와
에이지 미야모토
요오이치 마츠노
히로시 사토오
아츠시 노조에
Original Assignee
미타 가쓰시게
가부시키가이샤 하타찌세이사쿠쇼
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Publication date
Priority claimed from JP02108621A external-priority patent/JP3104795B2/ja
Priority claimed from JP03074530A external-priority patent/JP3080323B2/ja
Application filed by 미타 가쓰시게, 가부시키가이샤 하타찌세이사쿠쇼 filed Critical 미타 가쓰시게
Publication of KR910019200A publication Critical patent/KR910019200A/ko
Priority to KR1019990006234A priority Critical patent/KR100225968B1/ko
Application granted granted Critical
Publication of KR100240321B1 publication Critical patent/KR100240321B1/ko

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Abstract

내용 없음

Description

반도체장치 및 그의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명이 적용된 128메가 DRAM패키지의 제 1 의 실시예를 도시한 블럭도, 제 2 도는 제 1 도의 DRAM 패키지의 한 실시예을 도시하는 타이밍도, 제 3 도는 제 1 도의 DRAM 패키지를 구성하는 64메가 DRAM서브칩의 한 실시예을 도시하는 표준스펙.

Claims (37)

  1. 실질적으로 외부단자와 일체화되는 배선수단을 끼워 탑재되는 한쌍의 반도체 칩을 구비하는 것을 특징으로 하는 반도체 장치.
  2. 특허청구의 범위 제 1 항에 있어서, 상기 배선수단은, 리이드프레임인 것을 특징으로 하는 반도체 장치.
  3. 특허청구의 범위 제 2 항에 있어서, 쌍으로 되는 2개의 상기반도체 칩은, 본딩패드가 형성되는 표면이 상기 리이드프레임측에 오도록 서로 대향하여 탑재되는 것을 특징으로 하는 반도체 장치.
  4. 특허청구의 범위 제 3 항에 있어서, 쌍으로 되는 2개의 상기 반도체 칩의 본딩패드는, 서로 면대칭으로 배치되는 것을 특징으로 하는 반도체 장치.
  5. 특허청구의 범위 제 4 항에 있어서, 쌍으로 되는 2개의 상기 반도체 칩의 본딩패드는, 상기 반도체 칩의 표면의 X출 또는 Y측의 중앙부에 직선상으로 배치되는 것을 특징으로 하는 반도체 장치.
  6. 특허청구의 범위 제 5 항에 있어서, 쌍으로 되는 2개의 상기 반도체 칩의 본딩패드는, 와이어 본딩에 의하여 대응하는 상기 리이드프레임의 대응하는 리이드와 결합되는 것을 특징으로 하는 반도체 장치.
  7. 특허청구의 범위 제 5 항에 있어서, 쌍으로 되는 2개의 상기 반도체 칩의 본딩패드는, CCB 본딩에 의하여 대응하는 상기 리이드프레임의 대응하는 리이트와 결합되는 것을 특징으로 하는 반도체 장치.
  8. 특허청구의 범위 제 6 항에 있어서, 상기 리이드프레임은, 본딩 종료후에 접합되므로서 일체화되는 제 1 및 제 2 의 리이드프레임으로 되는 것을 특징으로 하는반도체 장치.
  9. 특허청구의 범위 제 8 항에 있어서, 상기 제 2 의 리이드프레임은, 소정의 위치에서 절단된후 상기 제 1 의 리이드프레임과 접합되는 것을 특징으로 하는 반도체 장치.
  10. 특허청구의 범위 제 9 항에 있어서, 상기 제 2 의 리이드프레임의 절단부분 및 상기 제1의 리이드프레임과의접합부분은, 봉지용 수지의 내부에 보호되는 것을 특징으로 하는 반도체 장치.
  11. 특허청구의 범위 제 6 항에 있어서, 상기 리이드프레임은, 쌍으로되는 2개의 상기 반도체 칩을 그 중심선을 끼워 동일 평면상에 탑재할 수 있는 것이고, 또 본딩종료후에 상기 중심선을 끼워 절곡함으로써 쌍으로 되는 2개의 상기 반도체 칩을 대향하여 탑재할 수 있는 것을 특징으로 하는 반도체 장치.
  12. 특허청구의 범위 제 2 항에 있어서, 상기 반도체 장치는, 대응하는 상기 리이드프레임을 끼워 탑재되는 복수개쌍의 반도체 칩을 구비하는 것으로서, 상기 복수개 쌍의 반도체 칩은, 그의 표면과 직각으로 되는 방향으로 겹쳐 맞추어지고, 또 상기 리이드프레임에 대응하는 리이드가 서로 공통결합되므로서 적층화 되는 것을 특징으로 하는 반도체 장치.
  13. 특허청구의 범위 제 12항에 있어서, 상기 반도체 칩의 각각은, 그 칩 사이즈에 있어서 최적 또는 최대의 기억용량을 가지는 메모리 칩으로서, 상기 반도체 장치는, 적어도 2개의 상기 메모리 칩을 구비하는 것으로 적어도 상기 메모리 칩의 적어도 2배의 기억 용량을 가지는 메모리 패키지인 것을 특징으로 하는 반도체 장치.
  14. 특허청구의 범위 제 1 항에 있어서, 상기 반도체 칩의 각각은, 그의 어드레스공간의 일부가 정상으로 기능할 수 있는 파살한 메모리칩으로서, 상기 반도체 장치는, 그의 어드레스공간의 모두가 정상으로 기능할 수 있는 1개의 메모리칩과 동일의 기억용량을 가진 메모리 패키지 인것을 특징으로 하는 반도체 장치.
  15. 특허청구의 범위 제 14항에 있어서, 상기 메모리 패키지는, 그 어드레스 공간의 모두가 정상으로 기능할 수 있는 1개의 메모리 칩을 탑재하는 메모리패키지와 동일의 인터페이스를 가지는 것인 것을 특징으로 하는 반도체 장치.
  16. 특허청구의 범위 제 13항에 있어서, 사의 메모리 패키지를 구성하는, 메모리칩의 각각은, 소정의 본딩이 선택적으로 행하여지므로써, 그 비트구성 및/ 또는 선택조건이 산택적으로 전환되는 것인 것을 특징으로 하는 반도체 장치.
  17. 특허청구의 범위 제 16항에 있어서, 상기 메모리 패키지를 구성하는 복수개의 메모리칩은, 동시에 활성상태로 되고, 또 기억데이터의 입력 및/ 또는 출력동작을 병행하여 실행하는 것인것을 특징으로 하는 반도체 장치.
  18. 특허청구의 범위 제 16항에 있어서, 상기 메모리 패키지를 구성하는 복수개의 메모리칩은 소정의 칩선택신호에 따라 선택적으로 지정되는 것인것을 특징으로 하는 반도체 장치.
  19. 특허청구의 범위 제 18항에 있어서, 상기 메모리 패키지 및 메모리 칩은, 로우어드레스 신호 및 컬럼어드레스신호가 공통의 어드레스 입력단자를 통하여 시분할적으로 입력되는 어드레스 멀티플렉서 방식을 채용하는 것인 것을 특징으로 하는 반도체 장치.
  20. 특허청구의 범위 제 18항에 있어서, 상기 칩 선택신호는 로우어드레스신호의 일부로서 공급되는 것이고, 상기 메모리 패키지를 구성하는 복수개의 메모리칩은, 실질적으로 그의 워드선 선택동작이 상기 칩 선택신호에 따라 선택적으로 실행되어서 선택적으로 활성화 되는 것인 것을 특징으로 하는 반도체 장치.
  21. 특허청구의 범위 제 20항에 있어서, 상기 메모리 패키지를 구성하는 복수개의 메모리 칩은, 그의 로우드레스신호의 디코더 동작이 상기 칩 선택신호에 따라 선택적으로 실행되는 것인 것을 특징으로 하는 반도체 장치.
  22. 특허청구의 범위 제 18항에 있어서, 상기 칩 선택신호는, 컬럼어드레스신호의 일부로서 공급되는 것이고, 상기 메모리 패키지를 구성하는 복수개의 메모리 칩은, 동시에 활성화되어 또 기억데이터의 입력 및/ 또는 출력동작을 상기 칩 선택신호에 따라 선택적으로 실행하는 것인 것을 특징으로 하는 반도체 장치.
  23. 특허청구의 범위 제 18항에 있어서, 상기 메모리 패키지는, 각각의 어드레스 공간이 i-K비트의 로우어드레스신호와 i비트의 컬럼어드레스 신호 혹은 i비트의 로우어드레스신호와 i-K비트의 컬럼어드레스 신호에 따라 선택적으로 지정되는 2의 K 승개의 메모리 칩을 포함하는 것이고, 상기 칩 선택신호는, 상기 로우 어드레스신호 및 컬럼어드레스 신호의 차분 K비트로서 공급되는 것인 것을 특징으로 하는반도체 장치.
  24. 특허청구의 범위 제 1 항에 있어서, 상기 반도체 장치는, 복수개의 블럭을 포함하는 것이고, 상기 반도체 칩의 각각은, 상기 복수개의 블럭이 그 기능 및/또는 제조프로세스에 의하여 분할, 조합되어 이루어진 서브칩인 것을 특징으로 하는 반도체 장치.
  25. 특허청구의 범위 제 24항에 있어서, 상기 반도체 장치는, 메모리 패키지이고, 메모리 어레이 및 그의 직접 주변 회로를 포함하며 또, 비교적 집적도가 높은 제 1 의 서브칩과, 제어부를 포함하며 또, 비교적 집적도가 낮은 제 2 의 서브칩과를 구비하는 것인것을 특징으로 하는 반도체 장치.
  26. 특허청구의 범위 제 24항에 있어서, 상기 반도체 장치는, 복수개 비트의 기억데이터를 동시에 입력 또는 출력하는 메모리패키지이고, 상기 기억데이터의 소정비트에 대응하여 설치되고 또, 비교적 집적도가 높은 제 3 의 서브칩과 상기 기억데이터의 다른 소정비트에 대응하여 설치되고 또, 비교적 집적도가 낮은 제 4 의 서브칩과를 구비하는 것인 것을 특징으로 하는 반도체 장치.
  27. 특허청구의 범위 제 24항에 있어서, 상기 반도체 장치는, 마이크로컴퓨터 패키지이고, 데이터 RAM을 포함하고 또, 비교적 집적도가 높은 제 5 의 서브칩과 산술논리연산 유닛을 포함하고 또 비교적 집적도가 낮은 제 6 의 서브칩을 구비하는 것인 것을 특징으로 하는 반도체 장치.
  28. (1) 그 표면의 X 축 또는 Y 축의 중앙부에 직선상으로 배치된 복수개의 본딩패드를 갖춘 제 1 및 제 2 의 반도체 칩과 각각 복수개의 리이드를 가진 제 1 및 제 2 의 리이드프레임을 준비하는 공정, (2) 상기 제 1 의 반도체 칩의 표면과 상기 제 1 의 리이드프레임과를 소정의 절연재료를 개재하여 접합하는 공정, (3) 상기 제 2 의 반도체 칩의 표면과 상기 제 2 의 리이드프레임과를 소정의 절연재료를 개재하여 접합하는 공정, (4) 상기 제1 의 반도체 칩의 본딩패드와 상기 제 1 의 리이드프레임에 대응하는 리이드와를 전기적으로 결합하는 공정, (5) 상기 제 2 의 반도체 칩의 본딩패드와 상기 제 2 의 리이드프레임에 대응하는 리이드와를 전기적으로 결합하는 공정, (6) 상기 제 1 및 제 2 의 리이드 프레임을 상기 제 1 및 제 2 의 반도체 칩의 표면이 서로 대향하도록 겹쳐 맞추는 공정, (7)상기 제 1 및 제 2 의 반도체 칩 그리고 상기 제 1 및 제 2 의 리이드프레임을 봉지용 수지에 의하여 봉지하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  29. 특허청구의 범위 제 28항에 있어서, 상기 제 2 의 리이드프레임의 절단부 및 상기 제 1 의 리이드프레임과의 접합부는, 상기 봉지용 수지의 내부에 보호되는 것을 특징으로 하는 제조방법.
  30. 특허청구의 범위 제 30항에 있어서, 상기 절연재료는, 그 실질적인 접합면적이 필요한 최소로 되게 절단되는 것을 특징으로 하는 제조방법.
  31. 특허청구의 범위 제 30항에 있어서, 상기 절연재료는, 상기 리이드프레임의 각 리이드의 접합부에 따라 절형으로 절단되는 것을 특징으로 하는 제조방법.
  32. 특허청구의 범위 제 30항에 있어서, 상기 절연재료는, 폴리아미드의 양측을 열가소성 폴리아미드로 끼운 3층 구조의 절연 필름인 것을 특징으로 하는 제조방법.
  33. (a) 그 주변의 중앙부에 일열로 배치된 복수개의 외부단자를 가진 제 1과, 제 2 의 반도체 칩과, (b) 상기 제 1 의 반도체 칩의 주면상에 위치하는 복수의 제 1 의 리이드와, 상기 제 2 의 반도체 칩의 주면상에 위치하는 복수개의 제 2 의 리이드와, (c) 상기 제 1 의 리이드와 상기 제 1 의 반도체 칩상의 외부단자와를 전기적으로 접속하는 제 1 의 접속수단과, 상기 제 2 의 리이드와 상기 제 2 의 반도체 칩상의 외부단자와를 전기적으로 접속하는 제 2 의 접속수단과, (d) 상기 제 1 및 제 2 의 반도체 칩과, 상기 제 1 및 제 2 의 리이드의 일부를 봉지하는 봉지체와를 구비하고, 상기 제 1 과 제 2 의 동일기능의 리이드는 서로 접속되어 있고, 상기 제 1과 제 2 의 반도체 칩의 주변은 대향하고 있는 것을 특징으로 하는 반도체 장치.
  34. 특허청구의 범위 제 33항에 있어서, 상기 제 1 과 제 2 의 반도체 칩은 서로 같은 기능을 가진 것을 특징으로 하는 반도체 장치.
  35. 특허청구의 범위 제 33항에 있어서, 상기 제 1 및 제 2 의 접속수단은 본딩와이어인 것을 특징으로 하는 반도체 장치.
  36. 특허청구의 범위 제 33항에 있어서, 상기 봉지체는 수지로 되어 있는 것을 특징으로 하는 반도체 장치.
  37. 특허청구의 범위 제 36항에 있어서, 상기 제 1 및 제 2 의 리이드의 한쪽은 그 양단이 상기 봉지체내에 위치하도록 한 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원내용에 의하여 공개하는 것임.
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