JPS5662350A - Semiconductor device for memory - Google Patents

Semiconductor device for memory

Info

Publication number
JPS5662350A
JPS5662350A JP13762279A JP13762279A JPS5662350A JP S5662350 A JPS5662350 A JP S5662350A JP 13762279 A JP13762279 A JP 13762279A JP 13762279 A JP13762279 A JP 13762279A JP S5662350 A JPS5662350 A JP S5662350A
Authority
JP
Japan
Prior art keywords
lead
frames
leads
bent
facing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13762279A
Other languages
Japanese (ja)
Inventor
Yuji Sano
Hajime Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13762279A priority Critical patent/JPS5662350A/en
Publication of JPS5662350A publication Critical patent/JPS5662350A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce occupation space while raising the heat dissipating effect by solidly molding two lightly U-shaped lead frames facing each other and two pellets so arranged that one is set into the frames and the other set thereon. CONSTITUTION:Two semiconductor pellets 10 and 11 are separately bonded on tabs 14 and 15 of lead frames 12 and 13 while wire bonding 18 and 19 made on respective inner leads 16 and 17. The lead frame 12 is so bent that the tab 14 is positioned above the lead section while the lead frame 13 is bent in the opposite manner. Then, the lead frames 12 and 13 are laid one upon another and the inner leads 16 and 17 of the leads facing each other are connected to the outer leads thereof by spot weldings 22 and 23 corresponding to each other. Thereafter, all the components are molded solidly with a resin 24.
JP13762279A 1979-10-26 1979-10-26 Semiconductor device for memory Pending JPS5662350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13762279A JPS5662350A (en) 1979-10-26 1979-10-26 Semiconductor device for memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13762279A JPS5662350A (en) 1979-10-26 1979-10-26 Semiconductor device for memory

Publications (1)

Publication Number Publication Date
JPS5662350A true JPS5662350A (en) 1981-05-28

Family

ID=15202966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13762279A Pending JPS5662350A (en) 1979-10-26 1979-10-26 Semiconductor device for memory

Country Status (1)

Country Link
JP (1) JPS5662350A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
US5147815A (en) * 1990-05-14 1992-09-15 Motorola, Inc. Method for fabricating a multichip semiconductor device having two interdigitated leadframes
US5332922A (en) * 1990-04-26 1994-07-26 Hitachi, Ltd. Multi-chip semiconductor package

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
US5332922A (en) * 1990-04-26 1994-07-26 Hitachi, Ltd. Multi-chip semiconductor package
US5701031A (en) * 1990-04-26 1997-12-23 Hitachi, Ltd. Sealed stacked arrangement of semiconductor devices
USRE37539E1 (en) 1990-04-26 2002-02-05 Hitachi, Ltd. Sealed stacked arrangement of semiconductor devices
US5147815A (en) * 1990-05-14 1992-09-15 Motorola, Inc. Method for fabricating a multichip semiconductor device having two interdigitated leadframes

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