JPS5681958A - Semiconductor lead frame - Google Patents

Semiconductor lead frame

Info

Publication number
JPS5681958A
JPS5681958A JP15949779A JP15949779A JPS5681958A JP S5681958 A JPS5681958 A JP S5681958A JP 15949779 A JP15949779 A JP 15949779A JP 15949779 A JP15949779 A JP 15949779A JP S5681958 A JPS5681958 A JP S5681958A
Authority
JP
Japan
Prior art keywords
strip
lead
resin
wires
lead wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15949779A
Other languages
Japanese (ja)
Inventor
Toshiaki Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15949779A priority Critical patent/JPS5681958A/en
Publication of JPS5681958A publication Critical patent/JPS5681958A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve the moisture resistance property of a semiconductor lead frame carried on a semiconductor pellet by providing a bent portion at the connecting strip of external lead wire forming the lead, thereby eliminating the gap to occur between the resin seal and the resin root of the external lead. CONSTITUTION:The lead frame 10 is formed of a mount pad 11 having an external lead wire 12 for carrying the semiconductor pellet and external lead wires 14 disposed at both sides thereof. When connecting strips 16, 17 for fixing the lead wires 12, 14 are spaced at the portion projected out of the resin seal for the wires, a bent portion 16a is disposed between the lead wires 12 and 14 at the strip 16. When the pad 11 is sealed with resin such as epoxy or the like while externally exposing the strip 16, no deformation occurs at the root of the resin between the lead wires 12 and 14, and the moisture resistance property can be improved. Thereafter, the lead wires 12, 14 are cut at the upper end of the strip 16 in an ordinary way including the strip.
JP15949779A 1979-12-08 1979-12-08 Semiconductor lead frame Pending JPS5681958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15949779A JPS5681958A (en) 1979-12-08 1979-12-08 Semiconductor lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15949779A JPS5681958A (en) 1979-12-08 1979-12-08 Semiconductor lead frame

Publications (1)

Publication Number Publication Date
JPS5681958A true JPS5681958A (en) 1981-07-04

Family

ID=15695052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15949779A Pending JPS5681958A (en) 1979-12-08 1979-12-08 Semiconductor lead frame

Country Status (1)

Country Link
JP (1) JPS5681958A (en)

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