JPS56137665A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56137665A
JPS56137665A JP4049680A JP4049680A JPS56137665A JP S56137665 A JPS56137665 A JP S56137665A JP 4049680 A JP4049680 A JP 4049680A JP 4049680 A JP4049680 A JP 4049680A JP S56137665 A JPS56137665 A JP S56137665A
Authority
JP
Japan
Prior art keywords
pellet
pieces
semiconductor device
integration
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4049680A
Other languages
Japanese (ja)
Inventor
Toshihisa Taniguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP4049680A priority Critical patent/JPS56137665A/en
Publication of JPS56137665A publication Critical patent/JPS56137665A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To arrange so that a large memory capacity may be obtained despite the same package and integration by arranging at least two pieces of pellet in opposite position with a lead frame coming in between and applying a bonding on the electrode part of each pellet. CONSTITUTION:Two pieces of pellet 18A, 19B are arranged in an upper and a lower direction opposed to each other inside a tightly sealed cavity 26. The electrode parts of pellets 18A, 18B are connected to the lead frame 16 through solder bumps 28, 30. In this way, two pieces of pellet 18A, 18B are mounted in a single package, thus providing the memory capacity two times as much of a semiconductor device despite the same package and same degree of integration.
JP4049680A 1980-03-31 1980-03-31 Semiconductor device Pending JPS56137665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4049680A JPS56137665A (en) 1980-03-31 1980-03-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4049680A JPS56137665A (en) 1980-03-31 1980-03-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS56137665A true JPS56137665A (en) 1981-10-27

Family

ID=12582168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4049680A Pending JPS56137665A (en) 1980-03-31 1980-03-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56137665A (en)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892230A (en) * 1981-11-27 1983-06-01 Mitsubishi Electric Corp Semiconductor device
JPS6028255A (en) * 1983-07-26 1985-02-13 Oki Electric Ind Co Ltd Semiconductor device
EP0221496A2 (en) * 1985-11-04 1987-05-13 International Business Machines Corporation Integrated circuit package
JPS62108534A (en) * 1985-11-06 1987-05-19 Nec Corp Semiconductor device
JPS62205636A (en) * 1986-03-06 1987-09-10 Fuji Electric Co Ltd Manufacture of semiconductor device
US4763188A (en) * 1986-08-08 1988-08-09 Thomas Johnson Packaging system for multiple semiconductor devices
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
JPH0232547A (en) * 1988-07-22 1990-02-02 Matsushita Electric Ind Co Ltd Semiconductor packaging device
JPH0357257A (en) * 1989-07-18 1991-03-12 Internatl Business Mach Corp <Ibm> Prearranged on surface of outer heat sink high density semiconductor memory module and forming method of the same
US5014112A (en) * 1985-11-12 1991-05-07 Texas Instruments Incorporated Semiconductor integrated circuit device having mirror image circuit bars bonded on opposite sides of a lead frame
WO1991014282A1 (en) * 1990-03-15 1991-09-19 Fujitsu Limited Semiconductor device having a plurality of chips
US5082802A (en) * 1985-11-12 1992-01-21 Texas Instruments Incorporated Method of making a memory device by packaging two integrated circuit dies in one package
DE4214102A1 (en) * 1991-06-01 1992-12-03 Gold Star Electronics Multi-chip semiconductor module e.g. of LOC-TSOP type - has two blank chips which are interconnected by solder, while several TAB strips have each inner and outer leads
US5332922A (en) * 1990-04-26 1994-07-26 Hitachi, Ltd. Multi-chip semiconductor package
US5530292A (en) * 1990-03-15 1996-06-25 Fujitsu Limited Semiconductor device having a plurality of chips
US5587341A (en) * 1987-06-24 1996-12-24 Hitachi, Ltd. Process for manufacturing a stacked integrated circuit package
US7227251B2 (en) 1997-09-29 2007-06-05 Elpida Memory, Inc. Semiconductor device and a memory system including a plurality of IC chips in a common package

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892230A (en) * 1981-11-27 1983-06-01 Mitsubishi Electric Corp Semiconductor device
JPS6347259B2 (en) * 1981-11-27 1988-09-21 Mitsubishi Electric Corp
JPS6028255A (en) * 1983-07-26 1985-02-13 Oki Electric Ind Co Ltd Semiconductor device
EP0221496A2 (en) * 1985-11-04 1987-05-13 International Business Machines Corporation Integrated circuit package
JPS62108534A (en) * 1985-11-06 1987-05-19 Nec Corp Semiconductor device
US5082802A (en) * 1985-11-12 1992-01-21 Texas Instruments Incorporated Method of making a memory device by packaging two integrated circuit dies in one package
US5014112A (en) * 1985-11-12 1991-05-07 Texas Instruments Incorporated Semiconductor integrated circuit device having mirror image circuit bars bonded on opposite sides of a lead frame
JPS62205636A (en) * 1986-03-06 1987-09-10 Fuji Electric Co Ltd Manufacture of semiconductor device
US4763188A (en) * 1986-08-08 1988-08-09 Thomas Johnson Packaging system for multiple semiconductor devices
US6693346B2 (en) 1987-06-24 2004-02-17 Hitachi, Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US6521993B2 (en) 1987-06-24 2003-02-18 Hitachi, Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US6424030B2 (en) 1987-06-24 2002-07-23 Hitachi, Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US5587341A (en) * 1987-06-24 1996-12-24 Hitachi, Ltd. Process for manufacturing a stacked integrated circuit package
US6262488B1 (en) 1987-06-24 2001-07-17 Hitachi Ltd. Semiconductor memory module having double-sided memory chip layout
US5910685A (en) * 1987-06-24 1999-06-08 Hitachi Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US5708298A (en) * 1987-06-24 1998-01-13 Hitachi Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
JPH0232547A (en) * 1988-07-22 1990-02-02 Matsushita Electric Ind Co Ltd Semiconductor packaging device
US5227995A (en) * 1989-07-18 1993-07-13 International Business Machines Corporation High density semiconductor memory module using split finger lead frame
JPH0357257A (en) * 1989-07-18 1991-03-12 Internatl Business Mach Corp <Ibm> Prearranged on surface of outer heat sink high density semiconductor memory module and forming method of the same
US5463253A (en) * 1990-03-15 1995-10-31 Fujitsu Limited Semiconductor device having a plurality of chips
US5530292A (en) * 1990-03-15 1996-06-25 Fujitsu Limited Semiconductor device having a plurality of chips
EP0473796A4 (en) * 1990-03-15 1994-05-25 Fujitsu Ltd Semiconductor device having a plurality of chips
WO1991014282A1 (en) * 1990-03-15 1991-09-19 Fujitsu Limited Semiconductor device having a plurality of chips
US5332922A (en) * 1990-04-26 1994-07-26 Hitachi, Ltd. Multi-chip semiconductor package
US5701031A (en) * 1990-04-26 1997-12-23 Hitachi, Ltd. Sealed stacked arrangement of semiconductor devices
USRE37539E1 (en) 1990-04-26 2002-02-05 Hitachi, Ltd. Sealed stacked arrangement of semiconductor devices
DE4214102A1 (en) * 1991-06-01 1992-12-03 Gold Star Electronics Multi-chip semiconductor module e.g. of LOC-TSOP type - has two blank chips which are interconnected by solder, while several TAB strips have each inner and outer leads
US7227251B2 (en) 1997-09-29 2007-06-05 Elpida Memory, Inc. Semiconductor device and a memory system including a plurality of IC chips in a common package

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