JPS54141565A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54141565A
JPS54141565A JP5031678A JP5031678A JPS54141565A JP S54141565 A JPS54141565 A JP S54141565A JP 5031678 A JP5031678 A JP 5031678A JP 5031678 A JP5031678 A JP 5031678A JP S54141565 A JPS54141565 A JP S54141565A
Authority
JP
Japan
Prior art keywords
pellet
lead frames
metal
mounting part
pellet mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5031678A
Other languages
Japanese (ja)
Inventor
Itsuro Adachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5031678A priority Critical patent/JPS54141565A/en
Publication of JPS54141565A publication Critical patent/JPS54141565A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To achieve the common use of lead frames and the increased degree of freedom of material selection by separately forming the lead frames to be formed with external frame and pellet mounting parts and integrating these.
CONSTITUTION: A lead frame in which external leads 11 are formed and a pellet mounting part 12 composed of good heat conductance and a coefficient expansion close to that of a pellet 13 are separately formed and a part of both of these are connected. A pellet 13 is then mounted on the pellet mounting part and the electrodes of the pellet 13 and external leads 11 are connected by means of metal wires 14. Owing to the conveniences of assembling processes such as mounting of the pellet on the pellet mounting part 12, connecting of the metal wires 14, etc., the central part of the metal piece 12 is formed in concave form so that the bottom of the metal piece 12 and the bottom of the lead frame 11 become flush. This enables the area of the pellet mounting parts to be optimized with the lead frames of one shape if the metal pieces 12 are individually prepared according to the shapes of the pellets 13.
COPYRIGHT: (C)1979,JPO&Japio
JP5031678A 1978-04-26 1978-04-26 Semiconductor device Pending JPS54141565A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5031678A JPS54141565A (en) 1978-04-26 1978-04-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5031678A JPS54141565A (en) 1978-04-26 1978-04-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54141565A true JPS54141565A (en) 1979-11-02

Family

ID=12855486

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5031678A Pending JPS54141565A (en) 1978-04-26 1978-04-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54141565A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61137334A (en) * 1984-12-07 1986-06-25 Mitsubishi Electric Corp Semiconductor device
JPS629656A (en) * 1985-07-08 1987-01-17 Shinko Electric Ind Co Ltd Lead frame
JPH04333276A (en) * 1991-05-08 1992-11-20 Matsushita Electron Corp Manufacture of semiconductor device
US5696029A (en) * 1993-08-31 1997-12-09 Texas Instruments Incorporated Process for manufacturing a lead frame

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61137334A (en) * 1984-12-07 1986-06-25 Mitsubishi Electric Corp Semiconductor device
JPH0334854B2 (en) * 1984-12-07 1991-05-24 Mitsubishi Electric Corp
JPS629656A (en) * 1985-07-08 1987-01-17 Shinko Electric Ind Co Ltd Lead frame
JPH04333276A (en) * 1991-05-08 1992-11-20 Matsushita Electron Corp Manufacture of semiconductor device
US5696029A (en) * 1993-08-31 1997-12-09 Texas Instruments Incorporated Process for manufacturing a lead frame

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