JPH04333276A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04333276A JPH04333276A JP3102415A JP10241591A JPH04333276A JP H04333276 A JPH04333276 A JP H04333276A JP 3102415 A JP3102415 A JP 3102415A JP 10241591 A JP10241591 A JP 10241591A JP H04333276 A JPH04333276 A JP H04333276A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- chip
- semiconductor device
- lead frame
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000725 suspension Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、リードフレームを用い
た半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using a lead frame.
【０００２】0002
【従来の技術】図２は従来の半導体チップのダイパット
部への装着をした上面図である。インナーリード部１と
チップ２を乗せるダイパット部３とそれを支えるつりリ
ード部４は同一リードフレーム基板に形成されている。
リードフレームを高温の装置上でチップ２をダイパット
部３に装着したり、その両者間に接着剤を使用して装着
した次の工程（ワイヤーボンディング）でインナーリー
ド部１とチップ２を電気的に配線する作業が実施されて
いた。2. Description of the Related Art FIG. 2 is a top view of a conventional semiconductor chip mounted on a die pad. The inner lead part 1, the die pad part 3 on which the chip 2 is placed, and the hanging lead part 4 supporting it are formed on the same lead frame substrate. The inner lead part 1 and the chip 2 are electrically connected in the next process (wire bonding) in which the chip 2 is attached to the die pad part 3 on the lead frame on a high-temperature device, or by using an adhesive between the two. Wiring work was being carried out.
【０００３】0003
【発明が解決しようとする課題】以上のような従来の方
法では、チップ２寸法を基準にダイパット部３寸法を求
めるため、汎用のリードフレームタイプの中から許容範
囲内の適性タイプを選んでいる。この場合、チップ２寸
法とダイパット部３寸法の差が大きい場合、配線５が長
くなり過ぎて形状が垂れ下ったり、製品完成後、実装時
に樹脂内部の水分が原因でパッケージクラックを誘発さ
せる確率も高くなってしまうという課題があった。[Problem to be Solved by the Invention] In the conventional method as described above, in order to obtain the third dimension of the die pad part based on the second dimension of the chip, an appropriate type within the allowable range is selected from among the general-purpose lead frame types. . In this case, if the difference between the chip 2 dimensions and the die pad part 3 dimensions is large, there is a possibility that the wiring 5 will become too long and the shape will sag, or that the moisture inside the resin will cause package cracks during mounting after the product is completed. The problem was that it was expensive.
【０００４】本発明はこのような課題を解決するために
なされたもので、ダイパット部寸法を適性化し問題発生
防止につながるチップの装着方法による半導体装置を提
供することを目的としている。The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device using a chip mounting method that optimizes the dimensions of the die pad portion and prevents problems from occurring.
【０００５】[0005]
【課題を解決するための手段】本発明は上記目的を達成
するために、チップを乗せるダイパット部とそれを支え
るつりリード部とをそれぞれに分割したものを用い、チ
ップ寸法に一番適した寸法のダイパット部を用いてイン
ナーリードに取り付け加工が施される状態に成立される
ものである。[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention uses a die pad section on which a chip is placed and a suspension lead section that supports it, each divided into two parts, each having a size that is most suitable for the chip size. The die pad section is used to attach the inner lead to the inner lead.
【０００６】[0006]
【作用】本発明は上記した構成により、ダイパット部を
独立，分割化させることによりリードフレーム基板全て
を専用化することなく、ダイパット部のみをチップ寸法
を適したものを用いることができる。その結果、配線の
垂れ下がり、パッケージクラック問題など半導体への悪
影響が極めて少なくなる。[Operation] According to the present invention, by making the die pad portion independent and divided, it is possible to use only the die pad portion suitable for the chip size without dedicating the entire lead frame substrate. As a result, adverse effects on semiconductors, such as sagging wiring and package cracking problems, are extremely reduced.
【０００７】[0007]
【実施例】図１（ａ）は通常のリードフレームからダイ
パット部３を分割させた状態である。図１（ｂ）はチッ
プ２寸法に一番適したダイパット部３を図１（ａ）のつ
りリード部４に取付け、その上にチップ２を乗せたもの
である。この場合比較的長目のインナーリード１が使わ
れてるリードフレームタイプを選び専用のダイパット部
３を取付けることで後でつける配線５の長さも短くなり
、チップ２とダイパット部３の寸法差も少なくなり、ダ
イパット部３への装着工程が完結する。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1(a) shows a state in which a die pad portion 3 is separated from an ordinary lead frame. In FIG. 1(b), a die pad part 3 most suitable for the dimensions of the chip 2 is attached to the hanging lead part 4 of FIG. 1(a), and the chip 2 is placed on top of the die pad part 3. In this case, by selecting a lead frame type that uses a relatively long inner lead 1 and attaching a dedicated die pad part 3, the length of the wiring 5 to be attached later will be shortened, and the dimensional difference between the chip 2 and the die pad part 3 will be reduced. This completes the installation process to the die pad portion 3.
【０００８】[0008]
【発明の効果】以上の実施例から明らかなように本発明
によれば、ダイパット部をリードフレーム基板から独立
，分割しチップサイズに一番適したダイパットサイズを
取付けることができ、配線の形状異常，パッケージクラ
ックの発生率の低下などを計った半導体装置を提供でき
る。[Effects of the Invention] As is clear from the above embodiments, according to the present invention, the die pad portion can be separated and separated from the lead frame substrate, and the die pad size most suitable for the chip size can be attached, and the wiring shape It is possible to provide a semiconductor device that reduces the incidence of abnormalities and package cracks.
【図１】（ａ）は本発明の一実施例の半導体装置の製造
方法を示すリードフレームのつりリード部とインナーリ
ードの上面図
（ｂ）は図１（ａ）のつりリード部とダイパット部をあ
とから接続し、チップを装着させた場合の上面図1(a) is a top view of a hanging lead portion and an inner lead of a lead frame showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 1(b) is a top view of the hanging lead portion and die pad portion of FIG. 1(a); Top view after connecting and installing the chip
【図２
】従来の半導体装置の上面図[Figure 2
]Top view of conventional semiconductor device
１ インナーリード ２ チップ ３ ダイパット部 ４ つりリード部 ５ 配線 1 Inner lead 2 Chip 3 Die pad part 4 Hanging lead part 5 Wiring
Claims (1)
イパット部とそのダイパット部を支えるつりリード部と
をそれぞれに分割したものを用い、後で前記ダイパット
部とつりリード部を接続する工程を少なくとも有するこ
とを特徴とする半導体装置の製造方法。1. A die pad section for mounting a chip of a lead frame and a suspension lead section for supporting the die pad section are each divided into two parts, and the method includes at least the step of later connecting the die pad section and the suspension lead section. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3102415A JPH04333276A (en) | 1991-05-08 | 1991-05-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3102415A JPH04333276A (en) | 1991-05-08 | 1991-05-08 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04333276A true JPH04333276A (en) | 1992-11-20 |
Family
ID=14326818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3102415A Pending JPH04333276A (en) | 1991-05-08 | 1991-05-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04333276A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5466968A (en) * | 1993-11-02 | 1995-11-14 | Rohm Co. Ltd. | Leadframe for making semiconductor devices |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54141565A (en) * | 1978-04-26 | 1979-11-02 | Nec Corp | Semiconductor device |
| JPS629656A (en) * | 1985-07-08 | 1987-01-17 | Shinko Electric Ind Co Ltd | Lead frame |
-
1991
- 1991-05-08 JP JP3102415A patent/JPH04333276A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54141565A (en) * | 1978-04-26 | 1979-11-02 | Nec Corp | Semiconductor device |
| JPS629656A (en) * | 1985-07-08 | 1987-01-17 | Shinko Electric Ind Co Ltd | Lead frame |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5466968A (en) * | 1993-11-02 | 1995-11-14 | Rohm Co. Ltd. | Leadframe for making semiconductor devices |
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