JPH05299568A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH05299568A
JPH05299568A JP10507392A JP10507392A JPH05299568A JP H05299568 A JPH05299568 A JP H05299568A JP 10507392 A JP10507392 A JP 10507392A JP 10507392 A JP10507392 A JP 10507392A JP H05299568 A JPH05299568 A JP H05299568A
Authority
JP
Japan
Prior art keywords
semiconductor chip
die stage
central portion
lead frame
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10507392A
Other languages
Japanese (ja)
Inventor
Yusuke Suzuki
裕介 鈴木
Koichi Shibazaki
浩一 柴崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Miyagi Electronics Ltd
Original Assignee
Fujitsu Miyagi Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Miyagi Electronics Ltd filed Critical Fujitsu Miyagi Electronics Ltd
Priority to JP10507392A priority Critical patent/JPH05299568A/en
Publication of JPH05299568A publication Critical patent/JPH05299568A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To lessen a semiconductor chip mounting process in man-hour so as to easily set a semiconductor chip mounting process and a wire bonding process in-line when a semiconductor device is manufactured, where the semiconductor device is sealed up with resin by the use of a lead frame. CONSTITUTION:A lead frame 1 is provided with a die stage 3 and leads 2 arranged surrounding the die stage 3, where the die stage 3 is composed of a center 5 provided with an opening 4, a pair of clampers 6 which pinch the opposed sides of a semiconductor chip, tensile springs 7 spanned between the center 5 and the clampers 6, and a process where a semiconductor chip C is mounted on the center 5 and pinched by the clampers 6 is provided. Furthermore, a wire bonding (wire 8) process is carried out as the semiconductor chip C is vacuum-sucked (V) through the opening 4 from the underside of the center 5, and a resin sealing process (formation of sealing resin 9) is carried out excluding a path for a vacuum suction V as the semiconductor chip C is vacuum- sucked (V).

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、リードフレームを用い
て樹脂封止する半導体装置の製造方法及びその製造方法
を採用した半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device which is resin-sealed using a lead frame and a semiconductor device employing the manufacturing method.

【０００２】上記半導体装置は、半導体チップをリード
フレームのダイステージに搭載し、リードの先端部との
間をワイヤボンディングし、半導体チップとワイヤとリ
ード先端部とを樹脂封止して製造する。The above semiconductor device is manufactured by mounting a semiconductor chip on a die stage of a lead frame, wire-bonding the ends of the leads to each other, and sealing the semiconductor chip, the wires, and the ends of the leads with a resin.

【０００３】従来は半導体チップの搭載からワイヤボン
ディングまでの手番が長いので、本発明はその手番の短
縮を図ろうとするものである。Conventionally, since it takes a long time from mounting a semiconductor chip to wire bonding, the present invention seeks to shorten the time.

【０００４】[0004]

【従来の技術】リードフレームを用いて樹脂封止する半
導体装置の製造は、ダイステージとその周囲に先端部を
配列した複数のリードを有するリードフレームを用い、 ダイステージに半導体チップを搭載する。2. Description of the Related Art A semiconductor device which is resin-sealed with a lead frame is manufactured by using a die stage and a lead frame having a plurality of leads around which tips are arranged, and a semiconductor chip is mounted on the die stage.

【０００５】 半導体チップとリード先端部との間を
ワイヤボンディングする。 トランスファ成形により、ダイステージと半導体チ
ップとワイヤとリード先端部とを樹脂封止する。Wire bonding is performed between the semiconductor chip and the tip of the lead. By die transfer molding, the die stage, the semiconductor chip, the wires, and the tips of the leads are resin-sealed.

【０００６】 リード切断その他の後工程を経て完成
する。 を順次に行う方法によっている。この製造方法の従来例
は、ダイステージが平板であり、上記の工程では銀ペ
ーストを用いて半導体チップをダイステージに貼着し、
１５０℃程度の加熱により銀ペーストを硬化させて半導
体チップを固定している。The process is completed after cutting the leads and other post-processes. It is based on the method of sequentially performing. In the conventional example of this manufacturing method, the die stage is a flat plate, and in the above step, a semiconductor chip is attached to the die stage using silver paste,
The semiconductor chip is fixed by heating the silver paste by heating at about 150 ° C.

【０００７】[0007]

【発明が解決しようとする課題】しかしながらこの従来
例では、上記貼着が短時間で行われても上記加熱に３時
間程度の時間を要するため上記の手番が長くなり、
の半導体チップ搭載工程と上記のワイヤボンディング
工程のインライン化を困難にさせている問題がある。However, in this conventional example, even if the above-mentioned pasting is carried out in a short time, it takes about 3 hours for the above-mentioned heating, so that the above-mentioned turn becomes long,
There is a problem that it is difficult to put the semiconductor chip mounting process and the wire bonding process in-line.

【０００８】そこで本発明は、リードフレームを用いて
樹脂封止する半導体装置の製造方法に関し、半導体チッ
プ搭載工程とワイヤボンディング工程のインライン化が
容易となるように、半導体チップ搭載工程の手番短縮を
図ることを目的とし、また、その製造方法を採用した半
導体装置の提供を目的とする。Therefore, the present invention relates to a method of manufacturing a semiconductor device in which a lead frame is used for resin encapsulation, and shortens the number of steps in the semiconductor chip mounting process so that the semiconductor chip mounting process and the wire bonding process can be easily made inline. It is an object of the present invention to provide a semiconductor device adopting the manufacturing method.

【０００９】[0009]

【課題を解決するための手段】上記目的を達成するため
に、本発明による半導体装置の製造方法は、半導体チッ
プを搭載するダイステージとその周囲に先端部を配列し
た複数のリードとを有し、該ダイステージは開孔を有す
る中央部と搭載する半導体チップの対向側面を挟持する
対のクランパと該中央部から該クランパに渡設の引張バ
ネとを具えてなるリードフレームを用い、半導体チップ
の該ダイステージへの搭載として該半導体チップを該中
央部上に載せ該クランパにより挟持させる工程と、該ダ
イステージに搭載した半導体チップを該中央部の下側か
ら該開孔を通して真空吸引しながら、該半導体チップと
該リード先端部との間をワイヤボンディングする工程
と、しかる後、該半導体チップを該中央部の下側から該
開孔を通して真空吸引しながら、該ダイステージと該半
導体チップとワイヤボンディングのワイヤと該リード先
端部とを、該真空吸引の通路部分を残して樹脂封止する
工程とを有することを特徴としている。In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a die stage on which a semiconductor chip is mounted and a plurality of leads around which a tip portion is arranged. The die stage uses a lead frame including a central portion having an opening and a pair of clampers for sandwiching opposite side surfaces of a semiconductor chip to be mounted, and a lead frame extending from the central portion to the clamper. The step of mounting the semiconductor chip on the central part and sandwiching it by the clamper as mounting on the die stage, while vacuum suctioning the semiconductor chip mounted on the die stage from the lower side of the central part through the opening. Wire bonding between the semiconductor chip and the tip of the lead, and then vacuum sucking the semiconductor chip from the lower side of the central portion through the opening. While, the wire and the lead tip of the die stage and the semiconductor chip and wire bonding, is characterized by a step of resin-sealing while leaving a passage portion of the vacuum suction.

【００１０】また半導体装置は、半導体チップをリード
フレームのダイステージに搭載し樹脂封止して製造され
た半導体装置であって、該ダイステージは開孔を有する
中央部と該半導体チップの対向側面を挟持した対のクラ
ンパと該中央部から該クランパに渡設の引張バネとを具
えていることを特徴としている。Further, the semiconductor device is a semiconductor device manufactured by mounting a semiconductor chip on a die stage of a lead frame and sealing it with a resin, and the die stage has a central portion having an opening and opposite side surfaces of the semiconductor chip. It is characterized in that it is provided with a pair of clampers sandwiching the clamps and a tension spring extending from the central portion to the clamper.

【００１１】[0011]

【作用】半導体チップのダイステージへの搭載は、上記
クランパが半導体チップを支持するので従来例で用いた
銀ペーストを必要としない。従って、銀ペーストを硬化
させる加熱が不要となり、半導体チップ搭載工程の手番
が大幅に短縮される。これにより、半導体チップ搭載工
程とワイヤボンディング工程のインライン化が可能とな
る。The mounting of the semiconductor chip on the die stage does not require the silver paste used in the conventional example because the clamper supports the semiconductor chip. Therefore, it is not necessary to heat the silver paste to harden it, and the number of steps in the semiconductor chip mounting process is greatly shortened. This allows the semiconductor chip mounting process and the wire bonding process to be in-line.

【００１２】そして、ワイヤボンディング及び樹脂封止
の際には、上記クランパによる支持のみでは半導体チッ
プの固定強度が不足するが、その不足は上記真空吸引に
より補われるので支障を起こさない。In the wire bonding and the resin sealing, the fixing strength of the semiconductor chip is insufficient only by the support by the clamper, but the shortage is compensated by the vacuum suction, so that no trouble occurs.

【００１３】本製造方法によれば、従来例の樹脂封止さ
れる部材の中から銀ペーストが削除されて、温度膨張差
により封止樹脂が割れる恐れが少なくなる。また、半導
体装置は、本製造方法を採用するので、ダイステージが
上記のようになる。According to this manufacturing method, the silver paste is removed from the resin-sealed member of the conventional example, and the sealing resin is less likely to crack due to the difference in temperature expansion. Further, since the semiconductor device adopts this manufacturing method, the die stage is as described above.

【００１４】[0014]

【実施例】以下本発明の実施例について図１〜図３を用
いて説明する。図１は実施例のリードフレーム平面図と
製造工程順側面図、図２は半導体チップ搭載工程を説明
するための斜視図、図３は半導体チップ搭載工程とワイ
ヤボンディング工程のインライン化構成図、である。Embodiments of the present invention will be described below with reference to FIGS. 1 is a plan view of a lead frame of the embodiment and a side view in order of manufacturing steps, FIG. 2 is a perspective view for explaining a semiconductor chip mounting step, and FIG. 3 is an in-line configuration diagram of the semiconductor chip mounting step and wire bonding step. is there.

【００１５】図１において、使用するリードフレーム１
は（ａ）の平面図に示され、従来例のリードフレームと
同じく金属平板の加工によるものであり、２はリード、
３はダイステージ、である。In FIG. 1, the lead frame 1 to be used
Is shown in the plan view of (a), which is obtained by processing a metal flat plate like the lead frame of the conventional example, 2 is a lead,
3 is a die stage.

【００１６】リード２は、従来例のリードフレームと同
様に、先端部がダイステージ３の周囲に配列されてい
る。ダイステージ３は、半導体チップを搭載するところ
であるが従来例のリードフレームと大きく異なり、平板
のままで開孔４を有する中央部５と、曲げ起こし部６ａ
を設けた４個のクランパ６と、平板のままジグザク状の
パターンにされて中央部５から各クランパ６に渡設の引
張バネ７とを具えている。クランパ６は図の左右方向と
上下方向のそれぞれで対をなし、対向する曲げ起こし部
６ａの間隔を搭載する半導体チップの対向側面の間隔よ
り小さくしてある。Like the lead frame of the conventional example, the leads 2 have their tip portions arranged around the die stage 3. The die stage 3 is where a semiconductor chip is to be mounted, but is largely different from the lead frame of the conventional example, and the center portion 5 having the opening 4 as a flat plate and the bent and raised portion 6a.
And four tension springs 7 which are arranged in a zigzag pattern as a flat plate and are provided from the central portion 5 to each clamper 6. The clampers 6 are paired in the left-right direction and the up-down direction in the figure, and the distance between the bent and raised portions 6a facing each other is smaller than the distance between the facing side surfaces of the mounted semiconductor chip.

【００１７】そして、このリードフレーム１を使用した
実施例の製造工程の要部は（ｂ１）〜（ｂ３）の側面図
に示される。先ず、半導体チップＣのダイステージ３へ
の搭載として（ｂ１）のように、半導体チップＣを中央
部５上に載せクランパ６の曲げ起こし部６ａで半導体チ
ップＣの対向側面を挟持させる。その挟持の方法は、図
２に示され、同図（ａ）のように各クランパ６を爪１０
により外側に移動させ、同（ｂ）のように半導体チップ
Ｃを載せた後に爪１０をクランパ６から外して行う。ク
ランパ６が挟持する力は引張バネ７の張力による。ここ
では銀ペーストを使用しない。半導体チップＣはクラン
パ６による挟持により中央部５上に支持される。The essential parts of the manufacturing process of the embodiment using the lead frame 1 are shown in side views of (b1) to (b3). First, as for mounting the semiconductor chip C on the die stage 3, as shown in (b1), the semiconductor chip C is placed on the central portion 5 and the opposite side surface of the semiconductor chip C is sandwiched between the bent and raised portions 6a of the clamper 6. The pinching method is shown in FIG. 2, and each clamper 6 is attached to the claw 10 as shown in FIG.
Then, the claw 10 is removed from the clamper 6 after the semiconductor chip C is placed as shown in FIG. The force clamped by the clamper 6 depends on the tension of the tension spring 7. No silver paste is used here. The semiconductor chip C is supported on the central portion 5 by being clamped by the clamper 6.

【００１８】次いで（ｂ２）のように、半導体チップＣ
を中央部５の下側から開孔４を通して真空吸引（図示
Ｖ）しながら、半導体チップＣとリード２先端部との間
をワイヤボンディングする。８はワイヤボンディングの
ワイヤである。ここではクランパ６による支持のみでは
半導体チップＣの固定強度が不足するが、真空吸引Ｖが
その不足を補う。Then, as shown in (b2), the semiconductor chip C
While performing vacuum suction (V in the drawing) from below the central portion 5 through the opening 4, wire bonding is performed between the semiconductor chip C and the tip portion of the lead 2. Reference numeral 8 is a wire for wire bonding. Here, the fixing strength of the semiconductor chip C is insufficient only by the support by the clamper 6, but the vacuum suction V compensates for the lack.

【００１９】次いで（ｂ３）のように、半導体チップＣ
を中央部５の下側から開孔４を通して真空吸引（図示
Ｖ）しながら、トランスファ成形により、ダイステージ
３と半導体チップＣとワイヤ８とリード２先端部とを、
真空吸引Ｖの通路部分を残して樹脂封止し、パッケージ
となる封止樹脂９を形成する。ここでもクランパ６によ
る支持のみでは半導体チップＣの固定強度が不足する
が、真空吸引Ｖがその不足を補う。この真空吸引Ｖは、
トランスファ成形機に真空吸引装置を付加し、成形金型
の構造を適合させることにより容易に可能である。Then, as shown in (b3), the semiconductor chip C
While vacuum suction (V in the figure) from the lower side of the central portion 5 through the opening 4, the die stage 3, the semiconductor chip C, the wire 8 and the tip of the lead 2 are transferred by transfer molding.
Resin sealing is performed while leaving the passage portion of the vacuum suction V to form a sealing resin 9 that becomes a package. Here too, the fixing strength of the semiconductor chip C is insufficient only by the support by the clamper 6, but the vacuum suction V compensates for the lack. This vacuum suction V is
This is easily possible by adding a vacuum suction device to the transfer molding machine and adapting the structure of the molding die.

【００２０】これまでを従来例の工程に対応させると、
従来例のの工程までが終わったことになる。封止樹脂
９は、開孔４を通して半導体チップＣの底面を露出させ
ているが、半導体装置の特性を低下させることは稀であ
る。若しその特性低下の恐れがある場合は、上記露出部
分を別途の樹脂で埋めれば良い。When the process up to now is applied to the conventional process,
The steps up to the conventional example have been completed. The sealing resin 9 exposes the bottom surface of the semiconductor chip C through the opening 4, but rarely deteriorates the characteristics of the semiconductor device. If there is a possibility that the characteristics may deteriorate, the exposed portion may be filled with a separate resin.

【００２１】この後は、従来例のの工程と同様にして
半導体装置を完成させる。完成時点のダイステージ３は
半導体チップＣを搭載した時の状態のままとなってい
る。After that, the semiconductor device is completed in the same manner as the process of the conventional example. The die stage 3 at the time of completion remains in the state in which the semiconductor chip C was mounted.

【００２２】上述の方法によれば、従来例のの工程で
ある半導体チップＣの搭載が、従来例の場合より大幅に
手番短縮さるので、半導体チップ搭載工程とワイヤボン
ディング工程のインライン化が容易となる。そのインラ
イン化の構成は図３に示される。図中、１１はインロー
ダ、１２は半導体チップ搭載部、１３はワイヤボンディ
ング部、１４はアンローダ、である。インローダ１１に
リードフレーム１と半導体チップＣを供給することによ
り、半導体チップ搭載工程とワイヤボンディング工程を
自動的に進めることができて、ワイヤボンディング工程
を済ませた状態のものをアンローダ１４から取り出すこ
とができる。According to the above-described method, the mounting of the semiconductor chip C, which is the process of the conventional example, is significantly shortened compared to the case of the conventional example, so that the inline process of the semiconductor chip mounting process and the wire bonding process is easy. Becomes The inline configuration is shown in FIG. In the figure, 11 is an in-loader, 12 is a semiconductor chip mounting portion, 13 is a wire bonding portion, and 14 is an unloader. By supplying the lead frame 1 and the semiconductor chip C to the inloader 11, the semiconductor chip mounting process and the wire bonding process can be automatically advanced, and the wire bonding process-completed product can be taken out from the unloader 14. it can.

【００２３】[0023]

【発明の効果】以上説明したように本発明によれば、リ
ードフレームを用いて樹脂封止する半導体装置の製造方
法及びその製造方法を採用した半導体装置に関し、半導
体チップ搭載工程の手番を短縮させることができて、半
導体チップ搭載工程とそれに続くワイヤボンディング工
程のインライン化を容易にさせる効果があり、また、半
導体チップ搭載工程で銀ペーストを不要にさせることが
できて、温度膨張差により封止樹脂が割れる恐れを少な
くさせる効果がある。As described above, according to the present invention, a method of manufacturing a semiconductor device in which a lead frame is used for resin encapsulation and a semiconductor device adopting the manufacturing method are shortened. This has the effect of facilitating the inline operation of the semiconductor chip mounting process and the subsequent wire bonding process. Moreover, the silver paste can be made unnecessary in the semiconductor chip mounting process, and due to the difference in temperature expansion This has the effect of reducing the risk of the resin breaking.

【図面の簡単な説明】[Brief description of drawings]

【図１】 実施例のリードフレーム平面図と製造工程順
側面図FIG. 1 is a plan view of a lead frame and a side view in order of manufacturing steps according to an embodiment.

【図２】 半導体チップの挟持方法を説明するための斜
視図FIG. 2 is a perspective view for explaining a method of holding a semiconductor chip.

【図３】 半導体チップ搭載工程とワイヤボンディング
工程のインライン化構成図[FIG. 3] In-line configuration diagram of semiconductor chip mounting process and wire bonding process

【符号の説明】[Explanation of symbols]

１ リードフレーム ２ リード ３ ダイステージ ４ 開孔 ５ 中央部 ６ クランパ ６ａ クランパの曲げ起こし部 ７ 引張バネ ８ ワイヤ ９ 封止樹脂 １０ 爪 １１ インローダ １２ 半導体チップ搭載部 １３ ワイヤボンディング部 １４ アンローダ Ｃ 半導体チップ Ｖ 真空吸引 1 Lead Frame 2 Lead 3 Die Stage 4 Opening Hole 5 Central Part 6 Clamper 6a Bending and Raising Part of Clamper 7 Tensile Spring 8 Wire 9 Sealing Resin 10 Claw 11 Inloader 12 Semiconductor Chip Mounting Part 13 Wire Bonding Part 14 Unloader C Semiconductor Chip V Vacuum suction

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップを搭載するダイステージと
その周囲に先端部を配列した複数のリードとを有し、該
ダイステージは開孔を有する中央部と搭載する半導体チ
ップの対向側面を挟持する対のクランパと該中央部から
該クランパに渡設の引張バネとを具えてなるリードフレ
ームを用い、 半導体チップの該ダイステージへの搭載として該半導体
チップを該中央部上に載せ該クランパにより挟持させる
工程と、 該ダイステージに搭載した半導体チップを該中央部の下
側から該開孔を通して真空吸引しながら、該半導体チッ
プと該リード先端部との間をワイヤボンディングする工
程と、 しかる後、該半導体チップを該中央部の下側から該開孔
を通して真空吸引しながら、該ダイステージと該半導体
チップとワイヤボンディングのワイヤと該リード先端部
とを、該真空吸引の通路部分を残して樹脂封止する工程
とを有することを特徴とする半導体装置の製造方法。1. A die stage on which a semiconductor chip is mounted, and a plurality of leads having tip portions arranged around the die stage. The die stage sandwiches a central portion having an opening and opposite side surfaces of the semiconductor chip to be mounted. A lead frame comprising a pair of clampers and a tension spring extending from the central portion to the clamper is used, and the semiconductor chip is mounted on the central portion and clamped by the clamper for mounting the semiconductor chip on the die stage. And a step of wire-bonding the semiconductor chip mounted on the die stage between the semiconductor chip and the tip of the lead while vacuum-sucking the semiconductor chip from the lower side of the central portion through the opening. While vacuum-sucking the semiconductor chip from the lower side of the central portion through the opening, the die stage, the semiconductor chip, the wire for wire bonding, and the wire And a step of resin-sealing the leading end of the card while leaving the passage portion for vacuum suction. 【請求項２】 半導体チップをリードフレームのダイス
テージに搭載し樹脂封止して製造された半導体装置であ
って、 該ダイステージは開孔を有する中央部と該半導体チップ
の対向側面を挟持した対のクランパと該中央部から該ク
ランパに渡設の引張バネとを具えていることを特徴とす
る半導体装置。2. A semiconductor device manufactured by mounting a semiconductor chip on a die stage of a lead frame and sealing with a resin, wherein the die stage sandwiches a central portion having an opening and an opposite side surface of the semiconductor chip. A semiconductor device comprising a pair of clampers and a tension spring extending from the central portion to the clampers.
JP10507392A 1992-04-24 1992-04-24 Semiconductor device and manufacture thereof Pending JPH05299568A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10507392A JPH05299568A (en) 1992-04-24 1992-04-24 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10507392A JPH05299568A (en) 1992-04-24 1992-04-24 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH05299568A true JPH05299568A (en) 1993-11-12

Family

ID=14397772

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10507392A Pending JPH05299568A (en) 1992-04-24 1992-04-24 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH05299568A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009146951A (en) * 2007-12-11 2009-07-02 Denso Corp Resin-molded package type electronic device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009146951A (en) * 2007-12-11 2009-07-02 Denso Corp Resin-molded package type electronic device and manufacturing method thereof

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