DE4214102A1 - Multi-chip semiconductor module e.g. of LOC-TSOP type - has two blank chips which are interconnected by solder, while several TAB strips have each inner and outer leads - Google Patents

Abstract

The blank chips belong to chip group and are interconnected by intermediate solder. There are several TAB strips, each with an inner and an outer lead. The chips are fitted with solder pips on facing sides, with the inner leads bonded between them. To the outer leads is bonded a system support. The chip group is pref. coupled to a second one of identical design such that the respective blank chips of one group are adjacent to those of the other one. The outer leads of the groups are interconnected to corresponding points of the system support. USE/ADVANTAGE - For vertically stacked semicondutor chips with improved integration in tape automated bonding (TAB).

Description

The invention relates to a multichip semiconductor device an improved degree of integration by stacking several Has semiconductor chips, and in particular on a multichip half lead terbausstein, which uses a TAB (Tape Automated Bonding Technology) and a CA bonding technology the thinnest Has structure.

The trend towards semiconductor components has recently started to move in the right direction miniaturization, d. H. to light and thin building blocks, while the bare chip is dimensionally larger, so that Area or volume ratio of the bare chip to the semiconductor device velvet building block increases. Accordingly, the technology is changing Manufacture of semiconductor devices gradually from the conventional Plastic packaging technology in which the chip is placed on a paddle is to LOC technology (lead-on-chip), with the leads on the chip be attached. Furthermore, the semiconductor module is usually included equipped with a single bare chip, of course it is known that a multichip semiconductor device by stacking several Chips forming a piggyback building block, or by matching different set of several chips within a semiconductor device (disclosed in Nikkei Micro Devices, April 1991).  

In Fig. 1 is a perspective view for showing a typical embodiment of a conventional multi-chip semiconductor device with piggy-back structure shown. Referring to FIG. 1, a plurality of semiconductor devices 2 is above the other mounted on the lowermost semiconductor package 1, wherein outer leads 2 a, the terbaustein with the upper semiconducting are connected 2 are bonded with outer leads 1 a, with the lowermost semiconductor package 1 in conventional Are connected in such a way that the outer leads 1 a and 2 a are electrically connected to each other. The outer leads 1 a of the lowermost semiconductor component 1 are designed as an SOP type (Small Outline Package) and fitted into a memory module or a circuit board level. In this way, the conventional piggyback type of semiconductor device achieves an improved degree of integration in three dimensions.

However, since the conventional semiconductor device is such that the separately manufactured semiconductor device 1 is stacked on top of one another, the conventional semiconductor package has the disadvantage that each semiconductor device increases in thickness due to the wire bonding and the mold thickness of the epoxy resin encapsulation by a wire loop height. This inevitably increases the thickness of the entire semiconductor package.

FIG. 2 shows a cross-sectional view to illustrate the structure of a conventional multichip semiconductor module, in which an upper and a lower bare chip are arranged longitudinally parallel to one another in a single semiconductor module.

The method for producing the multichip semiconductor module is described below with reference to FIG. 2. First, two bare chips 3 and 4 are connected together. Inner leads of TAB tapes 5 and 6 are bonded to bumps 8 using the TAB technique, which are provided on the connection sections of the bare chips 3 and 4 . The outer leads of the TAB tapes 5 and 6 are each connected to the system supports 9 and 9 '. Finally, a casting 10 , which envelops the resulting chip arrangement, is formed by attaching an epoxy resin. Accordingly, a single semiconductor device contains two bare chips 3 and 4 , which improves the degree of integration of the elements and miniaturizes the device, ie it becomes light and thin.

Next 3 is a sectional view showing a wide ren embodiment of the conventional multi-chip semiconductor devices is illustrated in FIG., In which four bare chips 11, 12, 11 a and 12 a are incorporated.

The multichip semiconductor device shown in FIG. 3 is manufactured in a similar manner to that described with reference to FIG. 2. An upper and a lower bare chip 11 and 12 are connected to one another in the upper half of the multichip semiconductor module. Inner leads of TAB tapes 15 and 16 are bonded to bumps 13 and 14 of chips 11 and 12, respectively. The bumps 13 and 14 are provided on the opposite sides of the upper and lower upper surface of the chips 11 and 12 , respectively. Outer supply lines of the TAB tapes 15 and 16 are bonded to the system carriers 17 and 17 ', respectively. At the same time, an upper bare chip 11 a and a lower bare chip 12 a are connected to one another in the lower half of the multichip semiconductor component. Inner leads of the TAB tapes 21 and 22 are bonded to the bumps 18 and 19 , which are attached to ent opposite sides of the upper and lower surfaces of the upper and lower bare chips 11 a and 12 a, respectively. Outer re leads of the TAB tapes 20 and 21 are bonded to the system carriers 17 and 17 ', respectively. Finally, a casting 22 that envelops the resulting chip assembly is formed by attaching the epoxy resin encapsulation. Accordingly, a single semiconductor component contains four bare chips 11 , 12 , 11 a and 12 a, whereby its degree of integration is improved and an even greater miniaturization of the block is achieved than in the case of FIG. 2.

However, since in the case of the multichip semiconductor components shown in FIGS . 2 and 3 and described above, the inner leads of the TAB bands 6 and 15 , 16 , 20 , 21 are bonded to the bumps 7 , 8 and 13 , 14 , 18 , 19 are attached to the top and bottom surfaces of the blan ken chips 3 , 4 and 11 , 12 , 11 a, 12 a, take the heights H and H 'between the upper TAB band 5 and the lower TAB band 6 or between the upper TAB band 15 and the lower TAB band 21 , so that the thickness of the entire semiconductor package increases.

As the number of TAB tapes 5 , 6 and 15 , 16 , 20 , 21 continues to increase, the manufacturing cost of the multichip semiconductor device also increases, and moreover, the manufacturing of the device necessitates a complex process.

Furthermore, since each inner lead bond (ILB) between the bare chips 3 , 4 , 11 , 12 , 11 a and 12 a and the TAB bands 5 , 6 , 15 , 16 , 20 and 21 on an outer surface of the bare chips 3 , 4 , 11 , 12 , 11 a and 12 a 'are executed, the multichip semiconductor devices are not suitable for LOC technology. Due to the relatively short lengths of the TAB tapes 5 , 6 , 15 and 16 , the method for bonding the inner leads is complicated and not easy to carry out.

It is therefore an object of the invention to provide a multichip semiconductor device to create the one with the help of a TAB technique and one for the Flip-chip method suitable C-4 bonding technology in the thinnest Structure is made to: miniaturize the semiconductor device, the LOC technique according to the increasing size of a bare To use chips and two or four bare chips at the same time encapsulate.

In order to achieve this goal, the multichip semiconductor device according to the present invention on: a first chip group with a first bare chip and a second bare chip others are connected by an inserted solder, and a plurality of TAB tapes, each with an inner lead and an outer one Has supply line, the first and the second bare chip with a variety of solder bumps on opposite sides of each other facing surfaces are provided, the inner leads between corresponding solder bumps of the first and second bare Chips are bonded, and a leadframe attached to the outer lead TAB tapes are bonded.

These and other objectives, features and advantages of the present Invention go from the description below in conjunction with the drawings clearly, the essential subject brief is described.

Fig. 1 is a perspective view illustrating a piggyback type of the multi-chip semiconductor device according to the state of the art;

FIG. 2 shows a cross-sectional view of a TSOP type in accordance with a further embodiment of the multichip semiconductor module shown in FIG. 1, in which two semiconductor chips are arranged one above the other;

Fig. 3 is a cross-sectional view of a TSOJ type according to yet another embodiment of the multi-chip semiconductor device shown in Figure 1 represents, in which four chips are arranged in line on the other.

Fig. 4 is a cross-sectional view of a LOC-TSOP type showing an embodiment of the multichip semiconductor device according to the present invention, in which TAB feeders are placed between two chips;

Fig. 5 is a cross-sectional view of a LOC-TSOP type showing another embodiment of the multichip semiconductor device according to the present invention, in which TAB leads are extended to the center of the chip;

Fig. 6 is a cross-sectional view of a LOC-TSOJ type, which in turn shows another embodiment of the multichip semiconductor device shown in Fig. 4;

FIG. 7 illustrates a cross-sectional view of a pressure-type multichip semiconductor device constituting another embodiment of the multichip semiconductor device shown in FIG. 4; and

FIG. 8 illustrates a cross-sectional view of a LOC-TSOP type that represents yet another embodiment of the multichip semiconductor device shown in FIG. 4.

The following are the preferred embodiments of the invention described in detail.

Referring to FIG. 4, a LOC-TSOP-block (thin small outline package) is illustrated which forms an embodiment of the multi-chip semiconductor device according to the present invention. The multichip semiconductor device shown in the drawing comprises an upper and a lower bare chip 32 and 34 . The upper bare chip 32 is provided with solder bumps 33 on opposite sides of the lower upper surface. Accordingly, the lower bare chip 34 is provided with bumps 35 on opposite sides of the upper surface. Between the upper and lower bare chip 32 and 34, a solder is inserted 36, so that the chips 32 and 34 are connected to each other. The inner leads of the TAB tapes 31 are bonded between the solder bumps 33 of the upper bare chip 32 and the solder bumps 35 of the lower bare chip 34 on opposite sides of the bare chips 32 and 34 . The outer leads of the TAB tapes 31 are each connected to a system carrier 37 (right in Fig. 4), 37 '(left in Fig. 4) (whereby for easier understanding of the structure of the module, only two TAB tapes 31 with the associated Components are shown). The chip group constructed as described is surrounded by a casting section 38 .

Below is the process for making the described Multichip semiconductor device according to the present invention explained.  

First, the inner leads of the TAB tapes 31 are connected to the opposite sides of the lower surface of the upper bare chip 32 by the C-4 bonding technique. The inner feed lines of the strip 31 are initially approximately aligned with the solder bumps 33 of the chip 32 . Thereafter, the chip 32 and the tape 31 are heated in an oven, whereby the inner leads of the tape 31 align themselves relative to the solder bumps 33 of the chip 32 . In contrast to the prior art, the inner leads of the strip 31 do not have to be exactly aligned with the solder bumps 33 .

The separated lower bare chip 34 is then turned over. Then it is aligned with the inner leads of the tape 31 which has been connected to the solder pads 33 of the upper chip 32 . It is then heated so that it is bonded to the inner leads of the tape 31 by C-4 bonding. The lower chip 34 can thereby self-align with respect to the inner leads of the tape 31 , so that an exact alignment of the upper chip 34 is not necessary, as described above. The solder 36 is then inserted between the upper bare chip 32 and the lower bare chip 34 .

In this case, since the TAB tape 31 is provided with an adhesive on both of its surfaces, the tape acts as a damping polyimide intermediate layer for the LOC component. After the inner leads of the TAB tape 31 have been bonded to the solder bumps 33 and 35 , the chips 32 and 34 are connected to one another by thermal compression.

The upper and lower chips 32 and 34 , which have been firmly connected to one another as described above, and the TAB bands 31 form a chip group C. After the chip group C on a system carrier for a SOP (Small Outline Package) or an SOJ ( Small Outline J-Lead Package) has been attached, the outer leads of TAB tape 31 of chip group C are bonded by thermocompression to system carriers 37 and 37 ', respectively. The resulting chip arrangement is then subjected to a casting encapsulation, as a result of which a casting 38 surrounding the chip arrangement is formed.

If desired, the encapsulation costs for the multichip semiconductor device can be reduced by testing the chip arrangement before bonding the outer leads of the TAB tape 31 with the system carriers 37 and 37 '.

Since the multichip semiconductor device according to the above-described embodiment of the present invention is constructed such that the single TAB band 31 is bonded to the upper bare chip 32 and the lower bare chip 34 simultaneously, the thinnest LOC packaging can be achieved and doubled Packing capacity can be achieved.

Although in this specification, the present invention in the case of LOC-TSOP version focuses on certain special features, it is natural Lich not limited to such a specific embodiment, son can be applied to all types of semiconductor devices, such as on LOC-SOJ type, LOC-SOI type and of the LOC-SOP type.  

Fig. 5 illustrates a further embodiment of the invention. The multichip semiconductor device comprises an upper and a lower bare chip 32 and 34 . Between the bare chips 32 and 34 system carriers 37 and 37 'are inserted and attached. The inner sides of the system carriers 37 and 37 'are bonded to TAB tapes 34 so that the feeds of the TAB tapes 34 are connected to solder bumps 33 and 35 which are attached to the connections of the upper and lower bare chips 32 and 34 . The bare chips 32 and 34 are cast encapsulated so that the other sides of the system carrier 37 and 37 'are exposed to the outside.

In this embodiment of the invention, the leads of the TAB tapes 31 connected to the sides of the lead frames 37 and 37 'are connected by C-4 bonding to the respective terminals of the upper and lower bare chips 32 and 34 using the Solder bumps 33 and 35 bonded. Then the upper and lower chips 32 and 34 and the system carriers 37 and 37 'inserted between them are bonded to one another, so that a chip group C is produced. Then the chip group C is encapsulated with polyimide.

The gap between the bare chips 32 and 34 is thus maintained by the system carrier 37 and 37 ', so that two bare chips can be stacked firmly and stably one above the other and a separate solder is not required. Since the system carrier 37 and 37 'are further fixed between two bare chips 32 and 34 , the connections of the bare chips can be formed not only on the peripheral sections of the bare chips, but also in the middle or in any section of the bare chips Crisps.

Accordingly, the connections can be designed as desired of the bare chip are included.

In the event that a multiple number of bare chips are stacked system stack can also be branched into the casting and then inserted between the two bare chips and there be attached.

Referring to Figure, the. 6 to 8 are there multichip Halbleiterbaustei ne in accordance with another embodiment of the invention, in which four bare chips are superposed one upon another.

The multichip semiconductor device comprises an upper and a lower chip group C and C '. In the same way as shown in FIG. 4, the upper chip group C has an upper bare chip 32 and a lower bare chip 34 . The upper bare chip 32 is provided with bumps 33 on the opposite sides of the lower surface of the chip, while the lower bare chip 34 is provided with solder bumps 35 on opposite sides of its upper surface. Inner leads of the TAB tape 31 are bonded between the solder bumps 33 and 35 . The upper bare chip 32 and the lower bare chip 34 are firmly connected to one another by a solder 36 inserted between the chips. Here too, only two TAB bands 31 with the associated components are shown for easier understanding of the structure of the module. In the same way, the lower chip group C 'comprises an upper bare chip 42 and a lower bare chip 44th The upper bare chip 42 is provided with solder bumps 43 on opposite sides of its lower surface, while the lower bare chip 44 is provided with solder bumps 45 on opposite sides of its upper surface. Inner leads of the TAB tape 41 are bonded between the solder bumps 43 and 45 . The upper bare chip 42 and the lower bare chip 44 are firmly connected to one another by a solder 46 inserted between the chips. The system carrier 47 , 47 ', 48 , 48 ', 49 and 49 'are bonded between the outer leads of the TAB tapes 31 and the outer leads of the TAB tapes 41 . The lower chip group C adheres to the lower chip group C 'by applying an adhesive 51 between the lower bare chip 34 of the upper chip group C and the upper bare chip 42 of the lower chip group C'. The chip arrangement constructed in this way is encased in a casting 50 .

The method for producing the aforementioned multi-chip semiconductor module according to a further embodiment of the present invention is described below, in which the module has four bare chips 32 , 34 , 42 and 44 .

First, according to the manner shown in Fig. 4, the inner leads of the TAB tapes 31 become between the solder bumps 33 attached on opposite sides of the lower surface of the upper bare chip 32 and those on opposite sides on the upper surface of the lower bare chip 34 attached solder core 35 attached, by C-4 bonding. A solder 36 is inserted between the upper bare chip 32 and the lower bare chip 34 , so that the upper bare chip 32 is firmly connected to the lower bare chip 34 . The upper and lower bare chips 32 and 34 , which have been firmly connected to one another as described above, and the TAB band 31 form an upper chip group C.

As with the upper chip group C, the inner leads of the TAB tapes 41 are bonded by C-4 bonding between the solder bumps 33 on the opposite sides of the lower surface of the upper bare chip 42 , and the solder bumps 45 on the opposite sides of the upper surface of the lower bare chips 44 attached. A solder 46 is inserted between the upper bare chip 42 and the lower bare chip 44 , so that the upper bare chip 42 is firmly connected to the lower bare chip 44 . In this way, the lower chip group C 'is formed.

Then the outer feeds of the TAB tapes 41 of the lower chip group C 'are connected to the lower surfaces of the system carriers 47 , 47 ', 48 , 48 ', 49 and 49 '. The adhesive 51 is applied to an upper surface of the upper bare chip 42 of the lower chip group C '. Then the upper chip group C is placed on the upper bare chip 42 of the lower chip group C ', and the lower feeds of the TAB tapes 31 of the upper chip group C are with the upper surface of the system carrier 47 , 47 ', 48 , 48 ', 49 and 49 'bonded by thermal compression. The chip arrangement formed from four bare chips 32 , 34 , 42 and 44 is subjected to a mold encapsulation, whereby a casting 50 enclosing the chip arrangement is formed. The system carrier protruding from the casting 50 can be one of the following types: LOC-SOJ type 47 , 47 '( FIG. 5), LOC-SOI type 48 , 48 ' ( FIG. 6) or LOC-SOP type 49 , 49 '( Fig. 7).

As can be seen from the above description, the number of for the packaging required TAB tapes are reduced by half, since the multichip semiconductor device is constructed in accordance with the invention is that two bare chips on a single TAB tape or four bare Chips are bonded to two TAB tapes. Accordingly, the thinnest possible multichip semiconductor device is manufactured,  which simplifies the manufacturing process of packaging and the Manufacturing costs can be reduced.

It is further assumed that various changes and Variants of the invention lie within the scope of the expert ability, without deviating from the nature and scope of the invention.

Claims (9)

1. Multi-chip semiconductor device comprising:
a first chip group having a first bare chip and a second bare chip connected by an inserted solder, and a plurality of TAB tapes, each having an inner lead and an outer lead, the first and the second bare Chip are provided with a plurality of solder bumps on opposite sides of the facing surfaces, wherein the inner leads are bonded between corresponding solder bumps of the first and second bare chips, and a lead frame which is bonded to the outer leads of the TAB tapes. 2. Multi-chip semiconductor device according to claim 1, wherein the chip group with another chip group that has the same structure as that has the first chip group, are interconnected so that each of the two bare chips of one chip group each of the two bare chips are adjacent to the other chip group, and each external supply of the other chip group with each associated one Point of the system carrier is bonded to each corresponding one outer lead of a chip group is bonded.   3. Multichip semiconductor device according to claim 2, wherein an adhesive is attached between the bare chips of the chip groups that are adjacent to each other. 4. Multichip semiconductor device according to claim 2, wherein the outer Feeds of the TAB tape with the SOJ type of the system carrier are bonded. 5. Multichip semiconductor device according to claim 2, wherein the outer Feeds of the TAB tape with the SOI type of the system carrier are bonded. 6. Multichip semiconductor device according to claim 2, wherein the outer Feeds of the TAB tape with the SOP type of the system carrier are bonded. 7. Multichip semiconductor device comprising:
a chip group with an upper bare chip and a lower bare chip; a first and a second leadframe, one end of which is inserted and fixed between the upper and lower bare chips, while the other end is exposed to the outside; first and second solder bumps, which were cut on Anschlussab each of the upper and lower bare chips are introduced; and first and second TAB tapes, each having one end connected to an inner end of each of the lead frames and the other end to the solder bumps, the die set being encapsulated and the outer sides of the lead frames exposed to the outside. 8. Multichip semiconductor device according to claim 7, wherein the insertion length of the leadframe from the position of the connecting part of the top and bottom bare chips depends. 9. Multi-chip semiconductor device according to claim 7, wherein a plurality is formed by chip groups of the same shape, each of the System carrier of the chip groups with the corresponding system carriers are bonded to the left and right sides, and the Chip groups are encapsulated in such a way that only one of the left and right system carrier is exposed.