KR880013223A - 웨이퍼 스케일 및 그 내장 방법과 그것에 사용하는 웨이퍼 제조방법 - Google Patents

웨이퍼 스케일 및 그 내장 방법과 그것에 사용하는 웨이퍼 제조방법 Download PDF

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Publication number
KR880013223A
KR880013223A KR1019880003425A KR880003425A KR880013223A KR 880013223 A KR880013223 A KR 880013223A KR 1019880003425 A KR1019880003425 A KR 1019880003425A KR 880003425 A KR880003425 A KR 880003425A KR 880013223 A KR880013223 A KR 880013223A
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South Korea
Prior art keywords
semiconductor
integrated circuit
substrate
circuit
semiconductor integrated
Prior art date
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KR1019880003425A
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English (en)
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KR960012649B1 (en
Inventor
마사노리 다즈노끼
히로미쯔 미시마기
마꼬또 혼마
도시유끼 사꾸따
히사시 나까무라
게이지 사사끼
미노루 에노모또
도시히꼬 사도우
구니조우 사하라
시게오 구로다
간지 오오쯔까
마사오 가와무라
히노꼬 구로사와
가즈야 이도우
Original Assignee
미다 가쓰시게
가부시기가이샤 히다찌세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority claimed from JP62097331A external-priority patent/JPS63263735A/ja
Priority claimed from JP62097329A external-priority patent/JPS63263736A/ja
Priority claimed from JP62097326A external-priority patent/JPS63263747A/ja
Priority claimed from JP62097330A external-priority patent/JPS63263734A/ja
Priority claimed from JP62099779A external-priority patent/JPS63266700A/ja
Application filed by 미다 가쓰시게, 가부시기가이샤 히다찌세이사꾸쇼 filed Critical 미다 가쓰시게
Publication of KR880013223A publication Critical patent/KR880013223A/ko
Priority to KR93004115A priority Critical patent/KR970001885B1/ko
Application granted granted Critical
Publication of KR960012649B1 publication Critical patent/KR960012649B1/ko

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Abstract

내용 없음

Description

웨이퍼 스케일 및 그 내장 방법과 그것에 사용하는 웨이퍼 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 4 도 A는 본 발명이 적용된 메모리 시스템의 하나의 실시예를 도시한 블럭도. 제 4 도 B는 그 메모리 블럭의 하나의 실시예를 도시한 개략 블럭도. 제 5 도 A 내지 제 5 도 C는 본 발명의 하나의 실시예에 의한 내장 기판의 제조방법을 공정 순으로 설명하기 위한 단면도. 제 5 도 D는 제 5 도 A 내지 제 5 도 C에 도시한 내장 기판의 제조방법에 의해 제조된 내장 기판을 사용하여 LSI칩을 내장한 멀티 칩 모듈을 도시한 단면도.제 5 도 E는 제 5 도 A 내지 제 5 도 C에 도시한 내장 기판의 제조방법에 있어서 CVD법에 의해 접속 배선을 형성하는 방법을 도시한 단면도.

Claims (21)

  1. 소정의 표면에 집적 회로를 구성한 반도체 웨이퍼등의 대형의 반도체 기판을 그 중앙부에서 지지하도록 구성한 것을 특징으로 하는 반도체 집적 회로의 내장장치.
  2. 특허청구의 범위 제 1 항에 있어서, 상기 반도체 기판은 그 중앙부에서 신호의 입출력이 행하여지는 것을 특징으로 하는 반도체 집적 회로의 내장장치.
  3. 특허청구의 범위 제 1 항에 있어서, 상기 내장장치는 여러매의 반도체 기판을 소정 간격마다 겹쳐 쌓고, 각각의 반도체 기판의 사이를 전기적으로 접속하도록 되어 있는 것을 특징으로 하는 반도체 집적 회로의 내장장치.
  4. 특허청구의 범위 제 1 항에 있어서, 상기 내장장치는 기둥 형상을 하고, 이것에 대응해서 반도체 기판의 중앙부에 열림구멍을 형성하여 이 열림구멍에 상기 내장 장치가 통하게 되는 것을 특징으로 하는 반도체 집적 회로의 내장장치.
  5. 특허청구의 범위 제 1 항에 있어서, 상기 기둥 형상의 내장장치는 그 측면에 반도체 기판을 사이에 끼우고, 또 전기적 접속하는 지지구가 마련되는 것을 특징으로 하는 반도체 집적 회로의 내장장치.
  6. 집적 회로를 구성한 반도체 웨이퍼등의 대형의 반도체 기판의 주변에 세워지는 여러개의 기둥, 상기 각각의 기둥에 마련한 반도체 기판 지지구, 상기 각각의 기둥 사이를 접속한 기둥 접속 기판으로 되는 반도체 집적 회로의 내장장치.
  7. 특허청구의 범위 제 6 항에 있어서, 상기 기둥 접속 기판의 바닥에 여러개의 커넥터 핀을 마련한 것을 특징으로 하는 반도체 집적 회로의 내장장치.
  8. 특허청구의 범위 제 6 항에 있어서, 상기 반도체 기판 지지구는 반도체 기판에 접속하는 전극을 갖고 있는 것을 특징으로 하는 반도체 집적 회로의 내장장치.
  9. 특허청구의 범위 제 6 항에 있어서, 상기 반도체 기판 지지구의 전극은 스프링 전극인 것을 특징으로 하는 반도체 집적 회로의 내장장치.
  10. 특허청구의 범위 제 6 항에 있어서, 상기 기둥 중의 몇 개인가는 쓰러뜨릴 수 있도록 기둥 접속 기판에 마련되고, 기둥과 기둥 접속 기판의 사이에 스프링을 마련하는 것에 의해서 세워지는 것을 특징으로 하는 반도체 집적 회로의 내장장치.
  11. 탑재 기판에 여러개의 반도체 칩을 탑재하고, 상기 탑재 기판상에 배선을 연장시키고 있는 상기 반도체 칩 사이를 전기적으로 접속한 반도체 장치로써, 상기 반도체 칩과 탑재 기판상의 배선의 사이를 본딩 와이어로 접속한 것을 특징으로 하는 반도체 집적 회로의 내장장치.
  12. 특허청구의 범위 제 11 항에 있어서, 상기 반도체 칩 및 탑재 기판은 동일한 패키지내에 봉하여 막히게 되는 것을 특징으로 하는 반도체 집적 회로의 내장장치.
  13. 특허청구의 범위 제 11 항에 있어서, 상기 반도체 칩은 본딩 패드가 마련되어 있는 쪽의 면과 반대쪽의 면이 상기 탑재 기판에 접착되는 것을 특징으로 하는 반도체 집적 회로의 내장장치.
  14. 특정의 회로 기능을 갖는 여러개의 회로 블럭을 구비하고, 각각의 회로 블럭을 지정하는 블럭 어드레스를 할당하는 것을 특징으로 하는 스케일 반도체 집적회호 장치.
  15. 특허청구의 범위 제14항에 있어서, 상기 웨이퍼 스케일 반도체 집적회로 장치는 상기 회로 블럭으로써의 디코더 회로와 그것에 의해 선택되는 메모리 어레이를 포함하는 반도체 기억 회로가 여러개 마련됨과 동시에, 상기 개개의 반도체 기억 회로에 할당되어 블럭 어드레스에 의해 선택 동작으로 행하는 제어 회로를 포함하는 것을 특징으로 하는 웨이퍼 스케일 반도체 집적회로 장치.
  16. 특허청구의 범위 제14항 또는 제15항에 있어서, 상기 반도체 기억 회로는 결함의 존재에 의해 상기 블럭어드레스에 의해 그 선택이 금지되는 것을 특징으로 하는 웨이퍼 스케일 반도체 집적회로 장치.
  17. 특허청구의 범위 제15항에 있어서, 상기 웨이퍼 스케일 반도체 집적회로 장치는 반도체 기억 회로의 메모리 어레이부가 분할된 여러개의 메모리 매트로 구성되고, 이 메모리 매트에 대응한 디코더 회로를 구비한 예비 기억 회로가 웨이퍼의 주변부에 배치됨과 동시에, 상기 결함의 존재에 의해 그 선택이 금지되는 반도체 기억 회로 대신에 예비 기억 회로의 선택이 행하여 지는 것을 특징으로 하는 웨이퍼 스케일 반도체 집적회로 장치.
  18. 특허청구의 범위 제15항에 있어서, 상기 제어회로는 결함이 존재하는 반도체 기억 회로의 블럭 어드레스를 리부로 출력하는 기능을 갖는 것을 특징으로 하는 웨이퍼 스케일 반도체 기억장치.
  19. 반도체 기판에 빔을 조사하는 것에 의해 스루홀을 형성하는 공정, 상기 반도체 기판을 열산화 하는 것에 의해 그 표면에 절연막을 형성하는 공정, 상기 스루홀의 내부에 금속을 충진하는 공정을 구비한 것을 특징으로 하는 내장 기판의 제조방법.
  20. 특허청구의 범위 제19항에 있어서, 상기 빔이 전자 빔 또는 이온 빔인 것을 특징으로 하는 내장 기판의 제조방법.
  21. 특허청구의 범위 제19항 또는 제20항에 있어서,CVD법에 의해 상기 스루 홀에 상기 금속을 충진하도록 한 것을 특징으로 하는 내장 기판의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR88003425A 1987-04-22 1988-03-29 Wafer scale or full wafer memory system, package, method thereof and wafer processing method employed therein KR960012649B1 (en)

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JP62-97330 1987-04-22
JP62097331A JPS63263735A (ja) 1987-04-22 1987-04-22 半導体集積回路の実装装置
JP62097329A JPS63263736A (ja) 1987-04-22 1987-04-22 半導体装置
JP62-97326 1987-04-22
JP62097326A JPS63263747A (ja) 1987-04-22 1987-04-22 実装基板の製造方法
JP62-97331 1987-04-22
JP62-97329 1987-04-22
JP62097330A JPS63263734A (ja) 1987-04-22 1987-04-22 半導体集積回路の実装装置
JP62-99779 1987-04-24
JP62099779A JPS63266700A (ja) 1987-04-24 1987-04-24 ウエハ大半導体集積回路装置

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US5598031A (en) * 1993-06-23 1997-01-28 Vlsi Technology, Inc. Electrically and thermally enhanced package using a separate silicon substrate
WO1995000973A1 (en) * 1993-06-23 1995-01-05 Vlsi Technology, Inc. Electrically and thermally enhanced package using a separate silicon substrate
EP0849738A3 (en) * 1996-12-19 1999-04-21 Texas Instruments Incorporated Improvements in or relating to electronic systems
JP2001102523A (ja) * 1999-09-28 2001-04-13 Sony Corp 薄膜デバイスおよびその製造方法
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US3908155A (en) * 1974-04-19 1975-09-23 Ibm Wafer circuit package
DE2611749C3 (de) * 1976-03-19 1980-11-13 Siemens Ag, 1000 Berlin Und 8000 Muenchen Halbleiteranordnung mit einem über Spannbolzen durch Druck kontaktierbaren Halbleiterbauelement
JPS5618439A (en) * 1979-07-25 1981-02-21 Fujitsu Ltd Semiconductor device consisting of different ic
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DE3882074T2 (de) 1993-10-07
EP0516185A3 (en) 1993-03-17
DE3856019D1 (de) 1997-10-09

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