KR960039305A - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법 Download PDF

Info

Publication number
KR960039305A
KR960039305A KR1019960011934A KR19960011934A KR960039305A KR 960039305 A KR960039305 A KR 960039305A KR 1019960011934 A KR1019960011934 A KR 1019960011934A KR 19960011934 A KR19960011934 A KR 19960011934A KR 960039305 A KR960039305 A KR 960039305A
Authority
KR
South Korea
Prior art keywords
pads
concave portion
semiconductor device
semiconductor chip
concave
Prior art date
Application number
KR1019960011934A
Other languages
English (en)
Other versions
KR100200254B1 (ko
Inventor
히데아끼 마에까와
Original Assignee
사또 후미오
가부시끼가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 사또 후미오, 가부시끼가이샤 도시바 filed Critical 사또 후미오
Publication of KR960039305A publication Critical patent/KR960039305A/ko
Application granted granted Critical
Publication of KR100200254B1 publication Critical patent/KR100200254B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/54—Providing fillings in containers, e.g. gas fillings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

본 발명의 반도체 장치는, 중앙이 오목형으로 소정 깊이로 홈파기 가공된 유리 에폭시 재료(3)와, 유리 에폭시 재료(3)의 오목형 부재에 배열된 다수의 본딩패드(5)와, 유리 에폭시 재료(3)의 오목형부 내에, 소자 영역이 본딩 패드(5)의 열에 대향하도록 배치되며, 본딩 패드(5)에 구형 금속(12)을 통해 전기적으로 접속된 콘택트 패드(1)를 갖는 반도체 소자(6)와, 반도체 소자(6)를 완전히 피복하도록 오목형부 내에 유입된 포팅제(2)를 구비한다. 본 발명을 사용함으로써, 외위기의 외형 치수의 축소, 제조 공정 감소 및 포팅제의 미충전 방지에 의한 신뢰성의 향상 등의 효과를 얻을 수 있다.

Description

반도체 장치 및 그 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예를 도시한 반도체 장치의 평면도 및 단면도.

Claims (5)

  1. 반도체 장치에 있어서, 중앙이 오목형으로 소정 깊이로 홈파기 가공된 외위기(3)와, 상기 외위기의 오목형부 내에 배열된 다수의 제1패드(5)와, 상기 외위기(3)의 오목형부 내에, 소자 영역이 상기 제1패드(5)의 열에 대향하도록 배치되며 상기 제1패드(5)에 금속 볼(12)을 통해 전기적으로 접속된 제2패드(1)를 갖는 반도체 칩(6)과, 상기 반도체 칩(6)을 완전히 피복하도록 상기 오목형부 내에 유입된 포팅 부재(2)를 구비하는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 외위기(2)는 유리 에폭시 재료로 구성되어 있는 것을 특징으로 하는 반도체 장치.
  3. 반도체 장치의 제조 방법에 있어서, 중앙이 오목형으로 소정 깊이로 홈파기 가공되며 이 오목형부 내에 다수의 패드가 형성된 외위기의 상기 오목형부 내에, 반도체 칩을 이 소자 영역이 상기 패드의 열에 대향하도록 배치하면서 상기 패드에 금속 볼을 통해 전기적으로 접속하는 공정과, 상기 오목형부 내에 포팅 부재를 유입함과 동시에 상기 외위기의 중앙에 형성된 관통 구멍에서 흡인함으로써 상기 반도체 칩을 상기 포팅 부재로 완전히 피복하는 공정을 구비하는 것을 특징으로 하는 반도체 장치의 제조 방법.
  4. 반도체 장치의 제조 방법에 있어서, 유리 에폭시판을 중앙이 오목형으로 소정 깊이가 되도록 홈파기 가공함으로써 외위기를 형성하는 공정과, 상기 외위기의 오목형부 내에 다수의 패드를 형성하는 공정과, 상기 외위기의 오목형부 내에 소정 높이의 절연 부재를 배치하는 공정과, 반도체 칩의 다수의 콘택트 패드상에 금속 볼을 배치하는 공정과, 상기 절연 부재상에 상기 반도체 칩을 탑재시키면서 상기 다수의 패드와 상기 콘택트 패드를 서로 대향시켜 상기 금속 볼을 통해 전기적으로 접속하는 공정과, 상기 오목형부 내에 포팅 부재를 유입함과 동시에 상기 외위기의 중앙에 형성된 관통 구멍에서 흡인함으로써 상기 반도체 칩을 상기 포팅 부재로 완전히 피복하는 공정을 구비하는 것을 특징으로 하는 반도체 장치의 제조 방법.
  5. 제4항에 있어서, 상기 절연 부내는 폴리이미드 테이프로 구성되어 있는 것을 특징으로 하는 반도체 장치의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960011934A 1995-04-21 1996-04-19 반도체 장치 및 그 제조 방법 KR100200254B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7096367A JPH08293524A (ja) 1995-04-21 1995-04-21 半導体装置およびその製造方法
JP95-096367 1995-04-21

Publications (2)

Publication Number Publication Date
KR960039305A true KR960039305A (ko) 1996-11-25
KR100200254B1 KR100200254B1 (ko) 1999-06-15

Family

ID=14163012

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960011934A KR100200254B1 (ko) 1995-04-21 1996-04-19 반도체 장치 및 그 제조 방법

Country Status (4)

Country Link
US (1) US5834835A (ko)
JP (1) JPH08293524A (ko)
KR (1) KR100200254B1 (ko)
TW (1) TW390004B (ko)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335183A (ja) * 1992-05-28 1993-12-17 Murata Mfg Co Ltd 多層基板を備えた電子部品及びその製造方法
FR2748156B1 (fr) * 1996-04-26 1998-08-07 Suisse Electronique Microtech Dispositif comprenant deux substrats destines a former un microsysteme ou une partie d'un microsysteme et procede d'assemblage de deux substrats micro-usines
JPH1064956A (ja) * 1996-08-20 1998-03-06 Fujitsu Ltd フェースダウンボンディング半導体装置
US6124546A (en) * 1997-12-03 2000-09-26 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
US6057175A (en) * 1997-12-04 2000-05-02 Medtronic, Inc. Method of making encapsulated package
US6586829B1 (en) * 1997-12-18 2003-07-01 Si Diamond Technology, Inc. Ball grid array package
US6150724A (en) * 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
JP3610787B2 (ja) * 1998-03-24 2005-01-19 セイコーエプソン株式会社 半導体チップの実装構造体、液晶装置及び電子機器
GB2340996B (en) * 1998-08-26 2003-07-09 Lsi Logic Corp Low skew signal distribution circuits
JP2000223657A (ja) * 1999-02-03 2000-08-11 Rohm Co Ltd 半導体装置およびそれに用いる半導体チップ
JP2000260912A (ja) * 1999-03-05 2000-09-22 Fujitsu Ltd 半導体装置の実装構造及び半導体装置の実装方法
US6392289B1 (en) * 1999-04-15 2002-05-21 Micron Technology, Inc. Integrated circuit substrate having through hole markings to indicate defective/non-defective status of same
FR2805410B1 (fr) * 2000-02-23 2002-09-06 Andre Rene Georges Gennesseaux Systeme autonome de cogeneration d'electricite et de chaleur comportant un stockage d'energie par volant d'inertie
TW521555B (en) * 2000-08-25 2003-02-21 Hitachi Aic Inc Electronic device sealing electronic element therein and manufacturing method thereof, and printed wiring board suitable for such electronic device
US6486561B1 (en) * 2000-09-12 2002-11-26 Luminary Logic, Ltd. Semiconductor light emitting element formed on a clear or translucent substrate
JP3866033B2 (ja) * 2000-12-14 2007-01-10 シャープ株式会社 半導体装置の製造方法
US6762509B2 (en) * 2001-12-11 2004-07-13 Celerity Research Pte. Ltd. Flip-chip packaging method that treats an interconnect substrate to control stress created at edges of fill material
US6987034B1 (en) 2002-01-09 2006-01-17 Bridge Semiconductor Corporation Method of making a semiconductor package device that includes singulating and trimming a lead
US7190060B1 (en) 2002-01-09 2007-03-13 Bridge Semiconductor Corporation Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same
US6936495B1 (en) 2002-01-09 2005-08-30 Bridge Semiconductor Corporation Method of making an optoelectronic semiconductor package device
US6891276B1 (en) 2002-01-09 2005-05-10 Bridge Semiconductor Corporation Semiconductor package device
KR100506035B1 (ko) * 2003-08-22 2005-08-03 삼성전자주식회사 반도체 패키지 및 그 제조방법
TWI241696B (en) * 2004-11-26 2005-10-11 Delta Electronics Inc Chip package structure
US8138027B2 (en) * 2008-03-07 2012-03-20 Stats Chippac, Ltd. Optical semiconductor device having pre-molded leadframe with window and method therefor
CN103050416B (zh) * 2012-12-07 2015-07-15 中国电子科技集团公司第十一研究所 用于百万像素碲镉汞混成芯片的底部填充方法及装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6489544A (en) * 1987-09-30 1989-04-04 Nec Corp Cap for photosemiconductor device case
CA2092165C (en) * 1992-03-23 2001-05-15 Tuyosi Nagano Chip carrier for optical device
US5491362A (en) * 1992-04-30 1996-02-13 Vlsi Technology, Inc. Package structure having accessible chip
JP2856647B2 (ja) * 1993-09-20 1999-02-10 株式会社東芝 半導体チップバーンイン用ソケット
US5498906A (en) * 1993-11-17 1996-03-12 Staktek Corporation Capacitive coupling configuration for an intergrated circuit package
US5721450A (en) * 1995-06-12 1998-02-24 Motorola, Inc. Moisture relief for chip carriers
US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device

Also Published As

Publication number Publication date
TW390004B (en) 2000-05-11
JPH08293524A (ja) 1996-11-05
US5834835A (en) 1998-11-10
KR100200254B1 (ko) 1999-06-15

Similar Documents

Publication Publication Date Title
KR960039305A (ko) 반도체 장치 및 그 제조 방법
KR100611880B1 (ko) 측면 높이가 낮은 볼 격자 배열 반도체 패키지 및 이를 반도체 소자에 장착하는 방법
US6856013B1 (en) Integrated circuit packages, ball-grid array integrated circuit packages and methods of packaging an integrated circuit
US5739581A (en) High density integrated circuit package assembly with a heatsink between stacked dies
US6452278B1 (en) Low profile package for plural semiconductor dies
JP3432982B2 (ja) 表面実装型半導体装置の製造方法
US6677663B1 (en) End grid array semiconductor package
KR970008514A (ko) 반도체장치, 반도체장치용 인터포우저(interposer) 및 그 제조방법
KR930024140A (ko) 반도체장치 및 그 제조방법
US6166435A (en) Flip-chip ball grid array package with a heat slug
KR20010049663A (ko) 반도체장치
JPS59107551A (ja) 半導体装置
JPH0829628B2 (ja) Ｉｃカ−ド
JPH10214933A (ja) 半導体装置とその製造方法
KR100218335B1 (ko) 칩 사이즈 패키지
KR960005965A (ko) 반도체 장치
KR970053660A (ko) 솔더 레지스트에 개방부가 형성되어 있는 반도체 칩 패키지
KR100384080B1 (ko) 반도체 패키지
JP2734684B2 (ja) 半導体素子パッケージ
KR100337451B1 (ko) 반도체패키지
KR200278535Y1 (ko) 칩 크기 패키지
US20030064542A1 (en) Methods of packaging an integrated circuit
JPH0669384A (ja) 絶縁物封止型半導体装置
KR930005147A (ko) 반도체칩모듈 및 그 제조방법
JPH0513624A (ja) 半導体装置

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090302

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee