TW390004B - Device for storing semiconductor chip and method for making the same - Google Patents

Device for storing semiconductor chip and method for making the same Download PDF

Info

Publication number
TW390004B
TW390004B TW085104384A TW85104384A TW390004B TW 390004 B TW390004 B TW 390004B TW 085104384 A TW085104384 A TW 085104384A TW 85104384 A TW85104384 A TW 85104384A TW 390004 B TW390004 B TW 390004B
Authority
TW
Taiwan
Prior art keywords
semiconductor
metal
electrodes
wafer
gold
Prior art date
Application number
TW085104384A
Other languages
English (en)
Inventor
Hideaki Maekawa
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of TW390004B publication Critical patent/TW390004B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/54—Providing fillings in containers, e.g. gas fillings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dispersion Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

A7 ____B7__··_ 五、發明説明（丨） 〔產業上之利用領域〕 本發明係關於半導髖覆晶裝置及其製造方法·特別是 關於有利於髙密度，髙集成化之半導體覆晶裝置的外圍器 〔先前之技術〕 對於一習知之半導體覆晶裝置的外圍裝置而言，一般 爲具備有金雇導線架構之SCTP (small outline ...... .· . package) ，S ◦ J ( small outline J-leaded)等之外 圍裝置，但是如此之構造通常要比實際的半導體元件的外 形尺寸來得大，因此便成爲妨礙追求髙密度化及髙集成化 之主因所在。甚至將上述半導髏覆晶裝置安裝於印刷配線 板上時，會因爲所使用之半導體覆晶裝置的熱硬化樹脂及 金屬導線的熱膨脹係數與印刷配線板的熱膨脹係數有所差 異之故，使得長期在髙溫/低溫的循環作用之下而產生應 力，導致熔接接合部發生龜裂而無法進行導電· 另一方面就追求高密度化及高集成化的方面而言，係 使用直接將半導體元件安裝於印刷配線板之所謂覆晶或 C Ο B ( chip on board)等之構造·但是像這樣的構造 係因直接將半導體元·件安裝於印刷配線板上•所以和樹脂 密封型半導體覆晶裝置比較之下，會較弱於承受機械性的 街擊，同時有必要導入新的製造裝置及技術* 習知對於用以作爲防止熔接接合部產生龜裂之對策而 言，並不是使用熱硬化樹脂來當作保護半導體元件的材料 (請先閱讀背面之注f項 再 fir • J·. 訂 線 經濟部智慧財產局貝工消費合作社印製 經濟部智慧財農局員工消費合作社印製 A7 B7五、發明説明（2 ) ，而是採用與印刷配線板的熱膨脹係數相近之同一材料的 環氧樹脂材料•另外，也不是使用金靥導線來使半導體覆 晶裝置與外部進行電氣性接觸，而是使用如_4(a)所 示之半導《元件的構造之平面圖樣*在半導髖覆晶裝置的 側面設置有半圖柱狀之金屬接觸部1 0 ·此外，圖4的元 件係爲了追求高密度化及髙集成化，而藉由金羼接觸部 1 0使複數個半導體覆晶裝置可以進行重叠之接合，促使 多段安裝成爲可能· ~ 第4圖（b)係表示圖4 (a)的A _A<線之斷面 圖，施以點面加工（spot facing)，藉由固定劑7將設 置在環氧樹脂材3上之金羼電極5與半導體元件6進行物 理性的連接，並利用金靥導線4將半導體元件6上的接觸 電極1與金屬電極5予以進行電氣性的連接•另外，爲了 防止半導髖元件6與外部接觸而利用密封用樹脂2予以密 封•並且，爲了確認藉由密封用樹脂2來進行密封後是否 有通道，而將導通確認用電極1 1設置於環氧樹脂材3上 藉由圈5(a)， （b)，（c)，（d)，（e) ，（f)來說明根據習知之技術所進行之樹脂密封型半導 體覆晶裝置的製作工程。此斷面圓係取自圖4 ( a )的A 一 A >線之斷面。圇5 ( a )係表示於實施黏面加工後， 將設置有金屬電極5友電氣導通確認用電極1 1之環氧樹 脂材3上塗佈固定劑，並在固定劑7上載置半導體元件6 。圖5 ( b )係表示爲了使載置於固定劑7上之半導體元 (請先Μ讀背面之注f項再填
訂 -線. 本纸浪尺度逋用t國國家揉準（CNS ) A4规格（210X297公釐） / A7 ____B7 五、發明説明（3 ) 件6固定起來，而施以加熱使固定劑硬化•圖5(c)係 表示半導體元件6上之各接觸電極1與各金屬電極5之間 藉由金屬導線4予以連接起來•圖5(d) ，（e)，（ f )係表示爲了保護半導髖元件，而在塗佈一層密封用樹 脂2後之低壓中進行脫泡，並予以加熱使其硬化* 但是·以上所述之半導體元件的外園裝置的構造*係 具有將在以下敘述之問題點· .第1點，如圖4 ·( b )矿示那樣，在環氧樹脂材3與 半導髖元件6之間係利用金屬導線4予以進行電氣性的接 合*如此藉由金屬導線4來進行電氣性的接合時，必定使 得金屬電極5形成於比半導體元件6更外側之環氧樹脂材 3上•如此一來，便使得樹脂密封型半導體覆晶裝置的外 形尺寸更趨於增大，而有礙於追求髙密度化及高集成化· 第2點，如圖5(a) ， (b) ， （c)所示，藉由 金羼導線4來進行電氣性連接，及使用固定劑7將半導髖 元件6接著於環氧樹脂材3等之製程，將會使整個製造工 程數的增加•亦即，會增加其製造成本。 〔發明所欲解決之課題〕 如上所述，習知之半導體覆晶裝置，係其外形尺寸比 較大，因此其製造程序之工程數將會有增加等之問題存在 〇 本發明係有鑑於上述之問題，而以一種外形尺寸較小 ，削減製造工程數，進而減低製造成本之半導髖覆晶裝置 本纸張尺度適用中β國家輮率（C^S > A4规格（210X297公釐） / 請先聞讀背*之注$項再填寫 訂 線 經濟部智慧財產局員工消費合作社印製 五、發明説明（ 4 A7 B7 經濟部智慧財產局貝工消費合作社印製 及其製造方法爲其主要之目的· 〔用以解決課題之手段〕 爲了達成上述之目的，本發明之半導體覆晶裝置的特 徵係具備有： 於中央位置以一定深度經由黏面加工而形成凹陷狀之 外圍裝置（—3 );及 被配列於上述外圔裝置的~凹狀部內之複數個第1金屬 電極（5 ):及 於上述外圍裝置的凹狀部內，與第1金屬電極（5 ) 成對向配置，且具有第2金屬電極（1)，經由球狀金屬 構件（12)與上述第1金屬電極進行電氣性連接之半導 體晶片（6 );及 流入上述凹狀部內而使可以完全覆羞上述半導體晶片 之密封用樹脂構件（2 )而構成者· 此半導體的外圍裝置，係由環氧樹脂所構成· 本發明爲了達成上述之目的，而提供一種半導體（覆 晶filp chip)的製造方法，其特徵係具有： 於中央位置以一定的深度經由黏面加工所形成之設置 有複數個金羼電極的外圍裝置之凹狀部內，將半導體晶片 與上述金屬電極形成對向配置，且經由球狀金屬構件與上 述金屬電極進行電氣性的連接之工程；及 將密封用樹脂流入上述凹狀部內的同時，藉由形成於 外圍裝置的中央位置之貫通穴所產生的吸引作用，使得上 請 先 Μ 面 之 注
I η 訂 線 本纸張尺度適用中國國家揉丰（C^S > Α4规格（210X297公釐） 7 A7 B7 五、發明説明（5 ) 述密封用樹脂可以完全覆蓋上述半導體晶片之工程· 更進一步的來說明的話·本發明之半導«覆晶裝置之 製造方法的特徽爲具有： 藉由點面加工在環氧樹脂板的中央位置以一定的深度 加工成凹狀而來形成外圍裝置之工程；及 在上述外園裝置的凹狀部內形成複數個金屬電極之工 程，及 在上述外園裝置的凹狀部"內配置有一定高度的絕緣構 件之工程：及 在半導體晶片之複數個接觸電極上配置球狀金屬構件 之工程；及 將上述半導體晶片配置於上述絕緣構件上，同時使上 述複數個金屬電極與上述接觸電極形成對向配置，並經由 上述球狀金属構件來進行電氣性連接之工程；及 將密封用樹脂流入上述凹狀部內的同時，藉由形成於 外園裝置的中央位置之貫通穴所產生的吸引作用，使得上 述密封用樹脂可以完全覆蓋上述半導體晶片之工程· 〔作用〕 使用本發明所提供之手段，則可以將第1金屬電極直 接形成於半導體晶片的下面*如此一來便可以有助於使半 導體覆晶裝置的外形穴寸縮小•並且，因爲未使用金屬連 接線之故，所以能夠使外圍裝置的高度降低*以上所述之 這類的優點正是最逋合於追求半導《的高密度化及高集成 本纸張尺度適用中國困家揉率（C^S > A4规格（210X297公兼) {請先明讀背面之注$項再填寫'^ 訂 線- 經濟部智慧財產局員工消費含作社印製 -8 - 經濟部智慧財產局員工消费合作社印製 A7 _B7_五、發明説明（6 ) 化· 此外，本發明係使用球狀金属，所以能夠一次完成半 導體元件之密封作業，同時因利用絕緣構件來進行半導髖 晶片與外園裝置之間的接著工作，所以可以減少製造半導 髖覆晶裝置之工程數，亦即可以削減製造成本· 〔實施例〕 第1圖（a )係表示本麥*明之實施例的平面圖*本發 明之樹脂密封用半導«覆晶裝置，係在經過黏面加工後之 環氧樹脂材料3的上面設置與半導髖元件6的接觸電極同 一位置之金屬電極5，並在此金觸電極5的內側貼附有爲 了接著半導體元件6的絕緣接著帶8 *此外，爲了保護半 導體覆晶裝置6而在塗佈密封用樹脂2時，藉由設置在環 氧樹脂材3的底部中央之吸引口 9的吸引力來使得密封用 樹脂2能夠完全地覆蓋在半導髗元件6上· 第lffl(a)及第1圖（b)中顯示有，爲了能確保 範圔廣的吸引面稹，而在絕緣接著帶8的內側設置有比半 導體元件6的長度大之凹部2 0的構造。 其次，利用圖 2(3)，（15)，（（；），（£1)及 (e )來說明本發明之樹脂密封型半導體覆晶裝置的製造 工程•此製造工程之斷面圖係取自圖1 (a)之B — B< 線之斷面。圈2 ( a )，係顯示在進行點面加工及在底部 中央部形成吸引口 9後，位於金屬電極5及導通確認用電 極1 1的上面，及爲了接著半導髓元件6，而貼附有絕緣 請 先 Η 面 之 注
I 訂 線 本紙張尺度適用中國國家榡準（CNS > A4规格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 A7 _____B7____五、發明説明（7 ) 接著带8之環氧樹脂材8上，載置有將球狀金屬1 2安裝 於接觸電極1之半導髖元件6的工程*圓2 (b)係表示 同時進行環氧樹脂材3與半導體元件6之電氣的接合與絕 緣接著帶8之加熱硬化之工程· 圖2(c) ， （d)， （e)係顯示爲了保護半導體 元件6而塗佈上一層密封用樹脂2 *同時藉由來自吸引口 9的吸引力而使得可以完全覆盖半導髖元件6的全髏，然 後進行脫泡，加熱使其硬化等之工程· ' * . · - .·：♦ 對於習知之技術p言，如圚4 ( b )所示爲了要使環 氧樹脂材3與半導體元件6進行電氣性的接合而使用金羼 線4，因此金羼電極5不得不形成於半導髖元件6的外側 ，導致半導體覆晶裝置的外形尺寸更趨於增大· 相對的，如圖1 (b)所示，本發明係使用可進行電 氣性接合的球狀金屬1 2，所以能夠將金屬電極5直接形 成於半導體元件6的下部，如圖3所示本發明之半導體覆 晶裝置的外形尺寸要比習知者來得小•並且，本發明係使 用球狀金屬來取代習知者所使用之金屬導線來進行電氣性 接合，因此電氣性接觸部的高度係可藉由球狀金屬1 2的 直徑變更，促使能夠將半導髓覆晶裝置的厚度變薄•如此 一來，便可以比習知之技術者更容易達成半導體覆晶裝置 之髙密度化及高集成化。 另外，藉由金屬導線4來進行電氣接合的情況時，則 必須分別地將金屬電極1予以接合，相對的若利用球狀金 牖1 2的話，則可以一次完成接合之作業，並且如圆2 ( 請 先 聞 面 之 注
I
訂 線 私紙張尺度逍用中國國家揉率（CNS ) A4规格（210X297公釐） 10 A7 B7 ___ 五、發明説明（8 ) b)所示也可以同時藉由絕緣接著帶8來進行半導髗元件 6之接著作業，因此可以削減製造工程，亦即能夠降低製 造成本· ^ 另一方面，如上述習知之構成因爲藉由球狀金屬1 2 來調整電氣接觸部的高度.，所以環氧樹脂材3下部與半導 體元件之間變得非常狹窄，導致密封用樹脂2很難進入· 但是，如圖1 ( a )所示，本發明之半導體覆晶裝置之構 造係設置有環氧樹脂材3的ίΤ部中央吸引口 9 ;及爲了確 保較廣的吸引面積而於絕緣接著帶8的內側設置有比半導 體元件6的長度大的凹陷部20。因此，如騙2 (c)所 示，在塗佈密封用樹脂2的同時藉由來自吸引口 9的吸引 力，促使密封樹脂2可以順利地被吸引入環氧樹脂材3的 下部和半導髖元件6之間，進而能夠完全地將半導體元件 6覆蓋。此時，亦會有密封樹脂2從吸引口 9溢出之虞， 但是只要對於密封樹脂2的黏度及吸引力，吸引時間等之 條件詳加考慮，便能夠防止溢出之情況發生* 以上所述之本發明的構成並不只局限於此，只要不脫 離本發明之主旨也是可以進行種種之變形· 另外，在本案之申請專利範圍的各構成要件添記圖面 參照圖號之目的是爲了能夠容易地理解本發明，而不是將 本發明之技術的範圔限定於圖面所示之實施例》 〔發明之效果〕 如以上說明，利用本發明的話，則可以將金属電極直 本紙張尺友逍用中國國家樣率（CNS > Α4规格（210X297公釐）
I (請先聞讀背面之注$項再填寫'% 訂 線 經濟部智慧財產局員工消費合作社印製 •Ί·. -11 - 經濟部智慧財產局員工消费合作社印製 A7 ____B7___ 五、發明説明（9 ) 接形成於半導體晶片的下面，有助於縮小半導髖覆晶裝置 的外形尺寸•並且，因爲不使用接合用金屬導線之故，所 以能夠降低外園裝置的髙度•以上所述之優點正是合適於 追求半導體覆晶裝置之高密度化及髙集成化等之條件· 另外，本發明係使用球狀金屬，因此可以一次完成接 合之作業，同時藉由絕緣構件來進行半導體晶片與外圍裝 置之接著作業，所以可減少製造工程數，亦即可以降低製 造成本。 〜 -'" -.. ,. · - 甚至可以防止密封用樹脂之未充填滿的情況發生，而 連到獲取其信賴性的提升等之效果· 〔圖面之簡單說明〕 第1圖係表示本發明之實施例的半導體覆晶裝置之平 面圈及斷面圖· 第2圖係表示本發明的製造工程之半導體覆晶裝置的 斷面圇· 第3圖係表示本發明與習知例之半導體覆晶裝置的比 較斷面圖· 第4圖係表示習知之半導體覆晶裝置的平面園與斷面 圖· 第5騙係表示習知之半導體覆晶裝置的製造工程之斷 面圓。 ' 〔圖號之說明〕 本紙張尺度適用中國國家揉準（> Α4规格（210X297公釐） 1^---Γ-----^------ir-------痒 (請先《讀背面之注f項再球寫ί) -12 - A7 B7 五、發明説明（1〇 ) 1 :接觸電極 2 :密封用樹脂 3 :環氣樹脂材料 4 :金屬導線 5 :接合用金靥電極 6 :半導體元件 7 :固定劑 8 :絕緣帶 ~ 9 :吸引口 1 0 :金羼接觸部 1 1 :導通確認用電極 1 2 :球狀金屬構件 2 0 :爲了確保吸引面積的凹陷部 (請先閏讀背面之注$項再填寫^.? - 線 經濟部智慧財產局員工消費合作社印製 本紙張尺度逋用中國國家標率（CNS > A4规格（210X297公釐） . / -13 -

Claims (1)

  1. 經濟部智慧財產局貝工消费合作社印製 A8 B8 C8 D8 六、申請專利範圍 1 . 一種半導體覆晶裝置，其特擞係具備有： 於中央位置以一定深度經由點面加工（spot facing )而形成凹陷狀之外園裝置；及 被配列於上述外園裝置的凹狀部內之複數個第1金屬 電極；及 設置於上述外園裝置的凹狀部內之吸引口；及 於上述外圍裝置的凹狀部內，與第1金靥電®成對向 配置，且具有第2金屬電極〜經由球狀金屬構件與上述第 +-+· ·.· ' . - *：> 1金屬電極進行電氣性連接之半導餿晶片；及 接著上述外園裝置與上述半導髓晶片之絕緣構件；及 流入上述凹狀部內而使可以完全覆蓋上述半導體晶片 之密封用樹脂構件而構成者· 2.如申請專利範圍第1項之半導體覆晶裝置，其中 上述外園裝置係由環氧樹脂所構成。 3 . —種半導體覆晶裝置之製造方法，其特徵係具有 於中央位置以一定的深度經由點面加工所形成之設置 有複數個金颶電極的外圔裝置之凹狀部內，將半導體晶片 與上述金靥電極形成對向配置，且經由球狀金羼構件與上 述金屬電極進行電氣性的連接之工程；及 將密封用樹脂流入上述凹狀部內的同時，藉由形成於 外園裝置的中央位置之貫通穴所產生的吸引作用，使得上 述密封用樹脂可以完全覆蓋上述半導體晶片之工程· 4.一種半導體覆晶裝置之製造方法，其特擞爲具有 * 1·1 I 1^—— — — — II— - — — It— — — · I I I I (請先Μ讀背面之注$項再缜寫本贾) 線1 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） _ 14 - A8明C8D6 六、申請專利範園 藉由黏面加工在環氧樹脂板的中央位置以一定的深度 加工成凹狀而來形成外圍裝罝之工程；及 在上述外園裝置的凹狀部內形成複數個金靥電極之工 程；及 在上述外圏裝置的凹狀部內配置有一定髙度的絕緣構 件之工程；及 在半導镰晶片之複數個接觸電極上配置球狀金屬構件 · .* ·· .. . - 之工程；及 將上述半導體晶片配置於上述絕緣構件上，同時使上 述複數個金屬電極與上述接觸電極形成對向配置*並經由 上述球狀金屬構件來進行電氣性連接之工程；及 將密封用樹脂流入上述凹狀部內的同時，藉由形成於 外圍裝置的中央位置之貫通穴所產生的吸引作用，使得上 述密封用樹脂可以完全覆盖上述半導體晶片之工程· 5.如申請專利範圔第4項之半導體覆晶裝置之製造 方法，其中上述絕緣構件係由聚酰亞胺所構成· (請先«讀背面之注f項再填X本頁) -ύ— •I 1_ ϋ 訂---------線· 經濟部智慧財產局員‘工汍费+作杜印製 本紙張尺度適用中國困家標準（CNS)A4規格（210x297公釐） -15 -
TW085104384A 1995-04-21 1996-04-12 Device for storing semiconductor chip and method for making the same TW390004B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7096367A JPH08293524A (ja) 1995-04-21 1995-04-21 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
TW390004B true TW390004B (en) 2000-05-11

Family

ID=14163012

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085104384A TW390004B (en) 1995-04-21 1996-04-12 Device for storing semiconductor chip and method for making the same

Country Status (4)

Country Link
US (1) US5834835A (zh)
JP (1) JPH08293524A (zh)
KR (1) KR100200254B1 (zh)
TW (1) TW390004B (zh)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335183A (ja) * 1992-05-28 1993-12-17 Murata Mfg Co Ltd 多層基板を備えた電子部品及びその製造方法
FR2748156B1 (fr) * 1996-04-26 1998-08-07 Suisse Electronique Microtech Dispositif comprenant deux substrats destines a former un microsysteme ou une partie d'un microsysteme et procede d'assemblage de deux substrats micro-usines
JPH1064956A (ja) * 1996-08-20 1998-03-06 Fujitsu Ltd フェースダウンボンディング半導体装置
US6124546A (en) * 1997-12-03 2000-09-26 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
US6057175A (en) * 1997-12-04 2000-05-02 Medtronic, Inc. Method of making encapsulated package
US6586829B1 (en) * 1997-12-18 2003-07-01 Si Diamond Technology, Inc. Ball grid array package
US6150724A (en) * 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
JP3610787B2 (ja) * 1998-03-24 2005-01-19 セイコーエプソン株式会社 半導体チップの実装構造体、液晶装置及び電子機器
GB2340996B (en) * 1998-08-26 2003-07-09 Lsi Logic Corp Low skew signal distribution circuits
JP2000223657A (ja) * 1999-02-03 2000-08-11 Rohm Co Ltd 半導体装置およびそれに用いる半導体チップ
JP2000260912A (ja) * 1999-03-05 2000-09-22 Fujitsu Ltd 半導体装置の実装構造及び半導体装置の実装方法
US6392289B1 (en) 1999-04-15 2002-05-21 Micron Technology, Inc. Integrated circuit substrate having through hole markings to indicate defective/non-defective status of same
FR2805410B1 (fr) * 2000-02-23 2002-09-06 Andre Rene Georges Gennesseaux Systeme autonome de cogeneration d'electricite et de chaleur comportant un stockage d'energie par volant d'inertie
TW521555B (en) * 2000-08-25 2003-02-21 Hitachi Aic Inc Electronic device sealing electronic element therein and manufacturing method thereof, and printed wiring board suitable for such electronic device
US6486561B1 (en) * 2000-09-12 2002-11-26 Luminary Logic, Ltd. Semiconductor light emitting element formed on a clear or translucent substrate
JP3866033B2 (ja) * 2000-12-14 2007-01-10 シャープ株式会社 半導体装置の製造方法
US6762509B2 (en) * 2001-12-11 2004-07-13 Celerity Research Pte. Ltd. Flip-chip packaging method that treats an interconnect substrate to control stress created at edges of fill material
US7190060B1 (en) 2002-01-09 2007-03-13 Bridge Semiconductor Corporation Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same
US6987034B1 (en) 2002-01-09 2006-01-17 Bridge Semiconductor Corporation Method of making a semiconductor package device that includes singulating and trimming a lead
US6936495B1 (en) 2002-01-09 2005-08-30 Bridge Semiconductor Corporation Method of making an optoelectronic semiconductor package device
US6891276B1 (en) 2002-01-09 2005-05-10 Bridge Semiconductor Corporation Semiconductor package device
KR100506035B1 (ko) * 2003-08-22 2005-08-03 삼성전자주식회사 반도체 패키지 및 그 제조방법
TWI241696B (en) * 2004-11-26 2005-10-11 Delta Electronics Inc Chip package structure
US8138027B2 (en) * 2008-03-07 2012-03-20 Stats Chippac, Ltd. Optical semiconductor device having pre-molded leadframe with window and method therefor
CN103050416B (zh) * 2012-12-07 2015-07-15 中国电子科技集团公司第十一研究所 用于百万像素碲镉汞混成芯片的底部填充方法及装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6489544A (en) * 1987-09-30 1989-04-04 Nec Corp Cap for photosemiconductor device case
CA2092165C (en) * 1992-03-23 2001-05-15 Tuyosi Nagano Chip carrier for optical device
US5491362A (en) * 1992-04-30 1996-02-13 Vlsi Technology, Inc. Package structure having accessible chip
JP2856647B2 (ja) * 1993-09-20 1999-02-10 株式会社東芝 半導体チップバーンイン用ソケット
US5498906A (en) * 1993-11-17 1996-03-12 Staktek Corporation Capacitive coupling configuration for an intergrated circuit package
US5721450A (en) * 1995-06-12 1998-02-24 Motorola, Inc. Moisture relief for chip carriers
US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device

Also Published As

Publication number Publication date
JPH08293524A (ja) 1996-11-05
KR960039305A (ko) 1996-11-25
US5834835A (en) 1998-11-10
KR100200254B1 (ko) 1999-06-15

Similar Documents

Publication Publication Date Title
TW390004B (en) Device for storing semiconductor chip and method for making the same
TW586201B (en) Semiconductor device and the manufacturing method thereof
TW512498B (en) Semiconductor device, method of manufacture thereof, circuit board, and electronic device
TW436997B (en) Ball grid array semiconductor package and method for making the same
JP3619773B2 (ja) 半導体装置の製造方法
US7064425B2 (en) Semiconductor device circuit board, and electronic equipment
TWI419287B (zh) 用於四面扁平無引線封裝之方法及裝置
US20050258214A1 (en) Method for forming bump, semiconductor element having bumps and method of manufacturing the same, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
US6921016B2 (en) Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
JP2006060128A (ja) 半導体装置
JP2009105334A (ja) 半導体装置及びその製造方法
CN106158785A (zh) 散热型封装结构及其散热件
US9258890B2 (en) Support structure for stacked integrated circuit dies
KR20120031132A (ko) 반도체 디바이스용 높은 접착 라인 두께
US20100181675A1 (en) Semiconductor package with wedge bonded chip
CN102412225A (zh) Bga半导体封装及其制造方法
TWI231026B (en) Planarized plastic package modules for integrated circuits
JP2005079590A (ja) 半導体素子用パッケージおよびその製造方法
US7180185B2 (en) Semiconductor device with connections for bump electrodes
US10049966B2 (en) Semiconductor device and corresponding method
TW529137B (en) Semiconductor device
US9786626B2 (en) Semiconductor device with a wire bonding and a sintered region, and manufacturing process thereof
TW558810B (en) Semiconductor package with lead frame as chip carrier and fabrication method thereof
US7015585B2 (en) Packaged integrated circuit having wire bonds and method therefor
JPS60120543A (ja) 半導体装置およびそれに用いるリ−ドフレ−ム

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees