JP2009105334A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2009105334A JP2009105334A JP2007277998A JP2007277998A JP2009105334A JP 2009105334 A JP2009105334 A JP 2009105334A JP 2007277998 A JP2007277998 A JP 2007277998A JP 2007277998 A JP2007277998 A JP 2007277998A JP 2009105334 A JP2009105334 A JP 2009105334A
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- semiconductor device
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- semiconductor chip
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Abstract
【解決手段】本発明は、半導体チップ30と、半導体チップ30と電気的に接続され、上面または下面の少なくとも一方に凹部12が設けられたリードフレーム10と、半導体チップ30及びリードフレーム10を封止し、凹部12の上方向に開口部22が設けられた樹脂部20と、を具備することを特徴とする半導体装置100である。開口部22から凹部12に導電性ピン(不図示)を差し込むことで、複数の半導体装置を機械的及び電気的に接続することができる。
【選択図】図6
Description
12、14 凹部
15、17 領域
16 穴
20 樹脂部
22、24 開口部
30 半導体チップ
32 ワイヤ
34 接着剤
36 金属板
50 テープ
52 金型
54、55 クランプピン
56 封止剤
58 試験電極
60 導電性ピン
62 半田ボール
72 中継基板
74 外部接続端子
76 貫通孔
77 電極パッド
78 再配線層
79 半田ボール
80 半導体チップ
82 接着剤
84 中継基板
86 ワイヤ
88 半田ボール
89 樹脂部
90 第1の半導体パッケージ
92 第2の半導体パッケージ
94 第1の半田ボール
96 第2の半田ボール
100〜109 半導体装置
Claims (13)
- 半導体チップと、
上記半導体チップと電気的に接続され、上面または下面の少なくとも一方に凹部が設けられたリードフレームと、
上記半導体チップ及び上記リードフレームを封止し、前記凹部の上方向に開口部が設けられた樹脂部と、
を具備することを特徴とする半導体装置。 - 前記凹部は、前記リードフレームの上面に設けられていることを特徴とする請求項1に記載の半導体装置。
- 前記凹部は、前記リードフレームの下面に設けられていることを特徴とする請求項1に記載の半導体装置。
- 前記凹部の一部に、前記リードフレームを貫通する穴が設けられていることを特徴とする請求項1から3のうちいずれか1項に記載の半導体装置。
- 前記半導体チップの下面は前記樹脂部から露出していることを特徴とする請求項1から4のうちいずれか1項に記載の半導体装置。
- 前記半導体チップの下面は絶縁性樹脂で覆われており、前記絶縁性樹脂の下面は前記樹脂部から露出していることを特徴とする請求項1から4のうちいずれか1項に記載の半導体装置。
- 前記半導体チップの下面は絶縁性樹脂で覆われており、前記絶縁性樹脂の下面は金属板で覆われており、前記金属板の下面は前記樹脂部から露出していることを特徴とする請求項1から4のうちいずれか1項に記載の半導体装置。
- 前記樹脂部は、前記リードフレームの上面及び下面に形成され、前記凹部の上下方向に開口部が設けられていることを特徴とする請求項1から7のうちいずれか1項に記載の半導体装置。
- 請求項1から8のうちいずれか1項に記載の半導体装置が複数積層され、
前記複数の半導体装置における、前記リードフレームに設けられた前記凹部及び前記樹脂部に設けられた前記開口部を貫通し、前記複数の半導体装置を電気的に接続する導電性ピンを具備することを特徴とする半導体装置。 - 前記導電性ピンの先端に半田ボールが設けられていることを特徴とする請求項9に記載の半導体装置。
- 請求項9に記載の半導体装置が実装された中継基板と、
前記中継基板における、請求項9に記載の半導体装置が実装された面と反対側の面に設けられた外部接続端子と、
請求項9に記載の半導体装置と前記外部接続端子とを電気的に接続する再配線層と、
を具備することを特徴とする半導体装置。 - リードフレームの上面または下面に凹部を形成する工程と、
前記リードフレーム及び半導体チップを電気的に接続する工程と、
前記凹部の上方向に開口部が形成されるように、前記リードフレーム及び前記半導体チップを封止する樹脂部を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 請求項1から8のうちいずれか1項に記載の半導体装置を複数積層する工程と、
前記複数の半導体装置における、前記リードフレームに設けられた前記凹部及び前記樹脂部に設けられた前記開口部を導電性ピンにより貫通し、前記複数の半導体装置を機械的及び電気的に接続する工程と、
を有することを特徴とする半導体装置の製造方法。
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JP2007277998A JP5341337B2 (ja) | 2007-10-25 | 2007-10-25 | 半導体装置及びその製造方法 |
US12/259,100 US8421241B2 (en) | 2007-10-25 | 2008-10-27 | System and method for stacking a plurality of electrically coupled semiconductor chips with a conductive pin |
US13/725,637 US9397025B2 (en) | 2007-10-25 | 2012-12-21 | Semiconductor device and method for manufacturing thereof |
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US10727168B2 (en) * | 2014-09-15 | 2020-07-28 | Nxp B.V. | Inter-connection of a lead frame with a passive component intermediate structure |
DE102015000063A1 (de) * | 2015-01-12 | 2016-07-14 | Micronas Gmbh | IC-Gehäuse |
US20160240457A1 (en) * | 2015-02-18 | 2016-08-18 | Altera Corporation | Integrated circuit packages with dual-sided stacking structure |
CN106653724B (zh) * | 2015-10-30 | 2020-04-10 | 恩智浦有限公司 | 一种封装组件结构 |
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JP6782175B2 (ja) | 2017-01-16 | 2020-11-11 | ラピスセミコンダクタ株式会社 | 半導体装置及び半導体装置の製造方法 |
KR102509052B1 (ko) * | 2018-08-31 | 2023-03-10 | 에스케이하이닉스 주식회사 | 브리지 다이를 포함하는 스택 패키지 |
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