KR930020560A - 웨이퍼 스케일 반도체집적회로장치 - Google Patents

웨이퍼 스케일 반도체집적회로장치 Download PDF

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Publication number
KR930020560A
KR930020560A KR1019930004115A KR930004115A KR930020560A KR 930020560 A KR930020560 A KR 930020560A KR 1019930004115 A KR1019930004115 A KR 1019930004115A KR 930004115 A KR930004115 A KR 930004115A KR 930020560 A KR930020560 A KR 930020560A
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South Korea
Prior art keywords
memory
scale semiconductor
wafer scale
main surface
semiconductor integrated
Prior art date
Application number
KR1019930004115A
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English (en)
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KR970001885B1 (en
Inventor
마사노리 다즈노끼
히로미쯔 미시마기
마꾜또 혼마
도시유끼 사꾸다
히사시 나까무라
게이지 사사끼
미노루 에노모또
도시유끼 사또
구니조 사하라
시게오 구로다
간지 오쯔까
마사오 가와무라
히노꼬 구로사와
가즈야 이또
Original Assignee
미다 가쓰시게
가부시끼가이샤 히다찌세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from JP62097330A external-priority patent/JPS63263734A/ja
Priority claimed from JP62097331A external-priority patent/JPS63263735A/ja
Priority claimed from JP62097326A external-priority patent/JPS63263747A/ja
Priority claimed from JP62097329A external-priority patent/JPS63263736A/ja
Priority claimed from JP62099779A external-priority patent/JPS63266700A/ja
Application filed by 미다 가쓰시게, 가부시끼가이샤 히다찌세이사꾸쇼 filed Critical 미다 가쓰시게
Publication of KR930020560A publication Critical patent/KR930020560A/ko
Application granted granted Critical
Publication of KR970001885B1 publication Critical patent/KR970001885B1/ko

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Abstract

웨이퍼등의 웨이퍼스케일 반도체기판을 사용한 반도체집적히로의 실장기술로서, 반도체웨이퍼등의 웨이퍼스케일 반도체기판을 사용한 반도체집적회로를 실장기판에 안정한 상태로 실장하고, 합리적인 결함구제를 실현하도록, 중심부와 주변부로 이루어지며, 또한 원형상의 주면을 갖는 웨이퍼 스케일 반도체기판, 웨이퍼 스케일 반도체기판의 주면상에 형성되고, 주면상에 동일한 면적크기를 갖는 여러개의 메모리 블럭, 웨이퍼 스케일 반도체기판의 주면의 주변부에 형성된 여러개의 예비메모리회로(RM)을 포함하고, 메로리블럭이 주면의 중심부에 마련되어 있고, 예비메모리 회로의 각각이 메로리 블럭의 점유면적보다 작은 점유면적을 갖는 구성으로 한다.
이러한 웨이퍼스케일 반도체집적회로장치를 사용하는 것에 의해, 특정한 회로기능을 갖는 여러개의 회로블럭을 구비하고, 각각의 회로블럭을 지정하는 블럭어드레스를 할당하도록 하는 것에 의해 웨이퍼상에 시스템을 완성 할수 있고, 블럭어드레스의 지정에 의해서 개개의 회로블럭의 기능시험이 가능하게 되어 불량블럭에 대한 실질적인 분리도 상기 블럭어드레스를 사용해서 실행할수가 있고, 따라서, 종래와 같이 불량블럭에 대해서 차례로 레이저광선이 조사등에 의해서 결선의 분리등을 실행하는 공정 및 양품에 대해서 결선을 실행하는 공정을 생략할 수 있다.

Description

웨이퍼 스케일 반도체집적회로장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도A는 반도체웨이퍼로 이루어지는 웨이퍼스케일 반도체기판을 여러매 지지하는 실장장치의 전체를 도시한 사시도, 제1도B는 제1도A에 도시한 실장장치에 마련되어 있는 지지부재를 확대한 사시도.

Claims (13)

  1. 중심부와 주변부로 이루어지며, 또한 원형상의 주면을 갖는 웨이퍼 스케일 반도체기판, 상기 웨이퍼 스케일 반도체기판의 주면상에 형성되고, 상기 주면상에 동일한 면적크기를 갖는 여러개의 메모리블럭(MO~M29), 상기 웨이퍼 스케일 반도체기판의 주면의 주변부에 형성된 여러개의 예비메모리회로 (RM)을 포함하고, 상기 메모베블럭은 상기 주면의 주심부에 마련되어 있고, 상기 예비메모리회로의 각각은 상기 메모리블럭의 점유면적보다 작은 점유면적을 갖는 웨이퍼스케일 반도체집적회로장치.
  2. 특허청구의 범위 제1항에 있어서, 상기 예비메모리회로의 각각은 상기 주면상에서 직사각형의 정유면적을 가지며, 상기 메모리블럭의 각각은 상기 주면상에서 직사각형의 정유면적을 갖는 웨이퍼스케일 반도체 집적회로 장치.
  3. 특허청구의 범위 제1항에 있어서, 상기 예비메모리회로는 메모리블럭의 결함을 구제하기 위해 사용되는 웨이퍼스케일 반도체집적회로장치.
  4. 특허청구의 범위 제1항에서 있어서, 상기 메모리 블럭의 각각은 여러개의 메모리 매트(MAT)로 이루어지고, 상기 예비메모리회로의 기억용량은 상기 메모리 매트의 기억용량과 동일한 웨이퍼스케일 반도체집적회로장치.
  5. 특허청구의 범위 제4항에 있어서, 상기 예비메모리회로는 상기 메로리매트의 결함을 구제하기 위해 사용되는 웨이퍼스케일 반도체집적회로장치
  6. 특허청구의 범위 제5항에 있어서, 상기 메모리블럭의 기억용량은 소정수의 예비메모리호로의 기억용량과 동일하며, 결함이 있는 메모리블럭은 상기 소정수의 예비메모리회로로 변경되는 웨이퍼스케일 반도체집적회로장치
  7. 특허청구의 범위 제5항에 있어서, 메모리 매트의 결함이 있을때에는 결함이 있는 메모리 매트대신에 예비메모리회로가 선택되는 웨이퍼스케일 반도체집적회로 장치.
  8. 특허청구의 범위 제1항에 있어서, 각각의 메모리 블럭을 지정하기 위한 블럭 어드레스(BA)는 각각의 메모리 블럭에 할당되어 있는 웨이퍼스케일 반도체집적회로장치.
  9. 특허청구의 범위 제8항에 있어서, 상기 예비메모리회로의 선택동작은 블럭 어드레스를 사용하는 것에 의해 실행되는 웨이퍼스케일 반도체집적회로장치.
  10. 특허청구의 범위 제1항에 있어서, 또 결함이 있는 메모리블럭에 대응하는 블럭 어드레스의 신호를 외부로 송출하는 수단을 포함하는 웨이퍼스케일 반도체 집적회로장치.
  11. 특허청구의 범위 제1항에 있어서, 상기 메모리블럭의 각각은 메모리 어레이와 디코더회로(RDCR,CDCR)을 포함하는 웨이퍼스케일 반도체집적회로장치.
  12. 특허청구의 범위 제1항에 있어서, 상기 예비메모리회로의 각각은 메모리 어레이와 디코더회로를 포함한 웨이퍼스케일 반도체집적회로장치.
  13. 중심부와 주변부로 이루어지며, 또한 원형상인 주면을 갖는 웨이퍼스케일 반도체기판, 상기 웨이퍼스케일 반도체기판의 주면상에 형성된 여러개의 메모리블럭(MO~M29), 상기 웨이퍼스케일 반도체기판의 주면의 주변부에 각각 형성된 여러개의 메모리회로(RM)을 가지며, 또한 메모리블럭의 결함을 구제하는 수단을 포함하고, 상기 메모리블럭의 각각은 상기 주면상에 직사각형의 점유면적을 갖고, 상기 메모리블럭은 상기 주면상에 동일한 면적크기를 가지며, 또한 상기 주면의 중심부에 마련되어 있고, 상기 메모리회로는 상기 주면상에 직사각형의 점유면적을 가지며, 상기 메모리회로는 상기 메모블럭의 점유면적보다 작은 점유면적을 갖는 웨이퍼스케일 반도체집적회로장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR93004115A 1987-04-22 1993-03-18 Wafer scale semiconductor device KR970001885B1 (en)

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JP62097330A JPS63263734A (ja) 1987-04-22 1987-04-22 半導体集積回路の実装装置
JP62097331A JPS63263735A (ja) 1987-04-22 1987-04-22 半導体集積回路の実装装置
JP62097326A JPS63263747A (ja) 1987-04-22 1987-04-22 実装基板の製造方法
JP62097329A JPS63263736A (ja) 1987-04-22 1987-04-22 半導体装置
JP89-97,326 1987-04-22
JP62099779A JPS63266700A (ja) 1987-04-24 1987-04-24 ウエハ大半導体集積回路装置
KR88003425A KR960012649B1 (en) 1987-04-22 1988-03-29 Wafer scale or full wafer memory system, package, method thereof and wafer processing method employed therein

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US5598031A (en) * 1993-06-23 1997-01-28 Vlsi Technology, Inc. Electrically and thermally enhanced package using a separate silicon substrate
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KR19980064369A (ko) * 1996-12-19 1998-10-07 윌리엄비.켐플러 메모리 모듈, 메모리 탑 및 메모리 모듈 구성 방법
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US3908155A (en) * 1974-04-19 1975-09-23 Ibm Wafer circuit package
DE2611749C3 (de) * 1976-03-19 1980-11-13 Siemens Ag, 1000 Berlin Und 8000 Muenchen Halbleiteranordnung mit einem über Spannbolzen durch Druck kontaktierbaren Halbleiterbauelement
JPS5618439A (en) * 1979-07-25 1981-02-21 Fujitsu Ltd Semiconductor device consisting of different ic
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EP0288186A2 (en) 1988-10-26
DE3882074T2 (de) 1993-10-07
EP0288186B1 (en) 1993-06-30

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