WO1995035573A1

WO1995035573A1 - Process for matching partial memory devices

Info

Publication number: WO1995035573A1
Application number: PCT/GB1995/001391
Authority: WO
Inventors: Alexander Roger Deas
Original assignee: Alexander Roger Deas
Priority date: 1994-06-18
Filing date: 1995-06-15
Publication date: 1995-12-28
Also published as: GB9412291D0

Abstract

A process for automatically populating module sets for use in a partial memory system which involves testing a memory device, recording the current faulty addresses relating to row and/or column drivers, comparing the current faulty addresses with faulty addresses of other chips in a first set of memory devices, if there are not more than a predetermined number of defective row or columns with the same address in the first set as the current faulty addresses then the memory device is stored in that set, if there are more than a predetermined number of defective row or columns with the same address, then the next set is accessed and the current faulty addresses are compared with the faulty addresses of other chips in that next set. This process continues until all of the memory devices have been sorted into sets or all of the sets have been used.

Description

Process for matching partial memory devices

The present invention relates to a process for automatically populating module sets for use in a partial memory system. The process relates to sorting partially working memory devices according to the addresses of the defects contained in those partially working memory devices. The process provides for an automatic system for ensuring that memory devices can be included in modules that use a plurality of partial memory devices yet work perfectly. The present invention is applicable in particular, though not exclusively, to sorting partially good Random Access Memories (RAM) for inclusion in Single In-line Memory Modules (SIMMs) or PCMCIA modules which use memory recovery, redundancy or replacement schemes. In the semiconductor industry, solid state memory devices are fabricated as multiple memory circuits on semiconductor (usually silicon) wafers, each memory circuit containing a memory array and bond pads. The wafers are processed in batches and at the end of the fabrication process the memory circuits on the wafers are tested and scribed into individual die. Those die which work perfectly or which can be made to work perfectly are packaged and sold: those die with one or more uncorrectable errors are classified (parametrically graded) and. if suitable, sold as partially working chips. Faulty die (partially working chips) may be functionally graded; those die with comparatively few defective cells may be sold as partially working devices. The die which have a very large number of defective cells or which have a considerable number of defective cells in each of the planes on the memory circuit are usually discarded. The partially working devices which can be sold have a value considerably lower than the value of perfectly working devices, yet in many cases they contain only a few defective memory locations. For this reason a number of schemes have been developed which use partially working die in memory replacement systems. One such memory replacement system is described in international patent application PCT/GB94/00577. Conventionally, solid state memory devices such as DRAMs (Dynamic Random Access

Memories) are organised in planes, with each plane consisting of row and column drivers and memory cells. For example, a four bit wide 16Mbit memory die comprises four planes of 2048 rows by 2048 columns, or 4096 rows by 1024 columns. When an address is received by the four bit chip, one bit is read form the appropriate row and column of each plane, thus giving four data bits. Some partially working chips have perfect row and column drivers but contain single bit errors in the memory array, whereas other partially working memory chips have faulty row and/or column drivers and/or single bit errors. If memory chips with faulty row or column drivers are to be used in a memory replacement scheme then the most efficient scheme for providing full memory function is to replace an entire row for each faulty row, and an entire column for each column that is faulty. One scheme for replacing faulty rows and/or columns is described in UK patent application number 9411274.5.

In any memory replacement scheme there is only a limited number of defects which can be tolerated. This number depends greatly on the type of memory replacement scheme that is being used. If a plane replacement scheme is being used then a memory circuit may have every location in any one plane faulty and still be usable, whereas if it has just two faulty cells but in two different planes it may be useless. If a row or column replacement scheme, such as UK patent application number 9411274.5, is to be used then the replacement system will fail to function if more than a certain number of chips have the same faulty row or column driver. These examples show that the location of defective cells is as important as the number of defective cells.

For many memory replacement schemes it is not sufficient merely to note the total number of defective cells, the locations of these defective cells is also important. Thus, the memory devices must be tested prior to packaging into modules to ensure that the memory replacement apparatus can cope with the number and location of faults on the memory devices.

When memory devices are to be packaged into SIMMs or PCMCIA modules then it may be imperative to ensure that no more than a certain number of row or column drivers with the same address in the memory devices on that SIMM are faulty. The predetermined number of faulty row and/or column drivers with the same address that can be defective without adversely affecting the memory operation will be governed by the particular configuration of the memory replacement system used and the particular philosophy underlying the memory replacement (for example cell replacement, row replacement or plane replacement). One advantage of the present invention is that it facilitates grouping of partially working memory devices into sets so that each set can be incorporated into a module which has no more than a predetermined number of faulty coincident rows and columns.

Another advantage of the present invention is that it is suitable for automated assembly of chips onto SIMMs. This is because the sets can be used to supply a pick-and-place machine which picks up the chips and locates them onto a SIMM.

It is an object of the present invention to provide a process that ensures that the number of coincident defective rows and/or columns is less than a certain predetermined threshold. It is another object of the present invention to provide a process which is compatible with automated placement of memory chips.

It is another object of the present invention to provide working memory modules that are composed of partially working memory chips.

It is a further object of the present invention to provide a system for grouping memory chips into sets without having to label or mark the chips in any way. The substance of the present invention is a process for sorting chips into groups such that each group contains no more than a predetermined number of defective row and/or column drivers with coincident faulty addresses.

The present invention accordingly provides a process for automatically sorting memory chips for use in a partial memory system which involves testing a memory device, recording the current faulty addresses relating to row and/or column drivers, comparing the current faulty addresses with faulty addresses of other chips in a first set of memory devices, if there are not more than a predetermined number of defective row or columns with the same address in the first set as the current faulty addresses then the memory device is stored in that first set, if there are more than a predetermined number of defective row or columns with the same address then the next set is accessed and the current faulty addresses are compared with the faulty addresses of other chips in that next set. This process continues until all of the memory devices have been sorted into sets or all of the sets have been used. The sorting of chips into sets means that the chips can be connected to a SIMM by an automated process which picks the chips from the set and places them on the SIMM. The sets that hold the chips can be tubes, each tube holding a single column of chips. Each tube may hold a number of sets, where a set consists of the number of chips which are to be connected to a particular SIMM. Thus, a pick-and-place machine could select the chip at the bottom of one of the tubes, place it on a module, select the next chip (which has fallen to the bottom of the tube under the action of the force of gravity) from the same tube as before, place that chip on the module, and repeat the process until the module has been populated. If one of the chips is dropped then the rest of the chips from that set would be placed in a receptacle to ensure that the sequence is not disturbed and the sets are not mixed. For a better understanding of the present invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which:

Figure 1 shows a flowchart for the sorting process; and Figure 2 shows in diagrammatical form equipment for sorting chips.

Figure 1 shows a flowchart which details the process flow. In this embodiment of the invention the maximum number of coincident faulty addresses of row or column drivers is one: no coincident faulty row or column driver addresses are allowed. Initially, chips 3 are loaded into the test machine 1. The test machine is a standard test machine for exercising memory chips, for example a Eureka tester from CST. This loading step could be accomplished by having a tube 2 at the input of the test device; the tube 2 presents one of the chips 3 to the entrance 4 of the test device 1 at all times. The machine 1 loads one of the chips 3 for testing. The loading of the chip could be performed by the action of gravity or it could be the result of a conveyor belt system, as is common in the field of automated testing of memory chips.

A first chip 3 A is tested using a test pattern which will record faulty row and/or column drivers. A number of different test patterns could be used, for example a march C test. It is very important that all defective rows and columns are found, otherwise the memory replacement system would not work perfectly, which would render the system useless for most memory applications. Once the faulty rows and/or columns have been detected they are stored in a record for that device. In this embodiment of the invention the record is in the form of a database 5. Although the database 5 is shown as external to the device 1 in this embodiment, it is only shown as external for clarity. The database 5 may be included within the test device 1. The database 5 contains one entry for each chip that has been tested. Each entry contains information on the addresses of row and/or column drivers that are defective, which set the chip is stored in, and how many chips are needed to make one complete set. The number of chips needed to make one complete set will be determined by the number of chips which are to be included in each SIMM. Since different SIMMs have different numbers of chips on them (for example, some SIMMs have three chips others have nine), the number of chips needed to make one complete set will vary with the type of module being fabricated. The database may be in the form of a computer generated and stored database. If the database is a computer database then the database would be integrated with but distinct from the controlling software for the test apparatus. Each entry in the database may have some form of an index to facilitate faster searching of the database. Alternatively, there may be one database entry for each set of memory devices rather than one entry for each memory device.

The first chip 3 A to be tested is stored in the first set 6; unless it fails the usefulness test, i.e. it has more than a predetermined number of faulty rows and/or columns, in which case it may be discarded in a set 7 reserved for chips 3 which fail the usefulness test. Thus, any chip tested which has greater than the predetermined number of row and/or column driver failures is discarded. The criterion used in the usefulness test may vary depending on which memory replacement scheme is being adopted. Once the first chip 3 A has been tested and the test information has been entered into the database 5 (in this example the first chip 3 A is stored in the first set 6) then the next (second) chip 3B is loaded into the test machine 1. Once the second chip 3B has been tested and the chip has passed the usefulness test successfully, the test information is then entered into the database 5. If it (the second chip 3B) fails the usefulness test then it is stored in the set 7 for discarded chips. The addresses of faulty row and/or column drivers in the second chip are compared with the addresses of faulty row and/or column drivers in the first chip 3 A. In this embodiment the second chip 3B is also stored in the first set 6, unless it has a faulty row or column driver coincident with the first chip 3 A. If it (the second chip 3B) has a faulty row or column driver at the same address as the first chip 3A then the second chip 3B is placed in the second set 8. For this example the second chip has a faulty row or column driver coincident with the first chip 3 A, so the second chip is stored in the second set 8. A third chip 3C is then loaded and tested. The results of the test on the third chip 3C are entered into the database in a separate entry for the third chip 3C. The addresses of any faulty row or column drivers in the third chip 3C are then compared with all of the entries in the database for a particular set in turn If the third chip 3C does not have a faulty row or column driver at the same address as the first chip 3 A then the third chip 3C will be stored in the first set 6. If the third chip 3 C has a faulty row or column driver at the same address as the first chip 3A then the first set 6 cannot be used, and the results of the test on the third chip 3C will be compared with the entries for the second set 8. This process continues until the third chip is placed.

The fourth chip 3D is then loaded into the test machine 1 and tested. Thus the process continues until all of the chips 3 have been sorted, or all of the sets are full and so no more chips 3 can be sorted, in which case a message is displayed by the test machine 1 to indicate that the sorting process cannot proceed until one of the sets is removed and replaced. The database may be organised in a number of different ways. It may be organised into sets, with a record of each faulty row and/or column driver address and the number of occurrences of that address in that set.

One or more tubes may also be provided for chips that contain no faults, that is, neither row or column drivers nor single bit errors.

Each tube at the output of the test machine 1 may contain a number of sets. Provided the chips 3 are extracted in the order they appear in the tube then there is no problem with having multiple sets in each tube.

In this embodiment of the invention there are eight tubes at the exit of the device: however, more or less tubes could be used without changing the concept underlying the invention. Thus, it will be appreciated that various modifications may be made to the above described embodiment within the scope of the present invention. For example, the chips may be placed directly onto memory modules rather than into sets. Thus, the exit tubes may be memory modules (such as SIMMs). The memory modules would be removed when they were fully populated and replaced with unpopulated memory modules.

Claims

1. A process for automatically sorting memory devices for use in a partial memory system which involves testing a memory device, recording the current faulty addresses relating to row and/or column drivers, comparing the current faulty addresses with faulty addresses of other devices in a first set of memory devices, if there are not more than a predetermined number of defective rows or columns with the same address in the first set as the current faulty addresses then the memory device is stored in that first set, if there are more than a predetermined number of defective row or columns with the same address then the next set is accessed and the current faulty addresses are compared with the faulty addresses of other devices in that next set. This process continues until all of the said memory devices have been sorted into sets or all of the sets have been used.

2. A process for automatically sorting memory devices according to claim 1, wherein a separate sorting area is provided for each set of memory devices.

3. A process for automatically sorting memory devices according to claim 1, wherein a plurality of sets are stored in each sorting area.

4. A process for automatically sorting memory devices according to claim 2, wherein the separate sorting area is a memory module.

5. A process for automatically sorting memory devices according to claim 2 or 3, wherein the sorting area is provided by containers which store the said memory devices in a single column.

6. A process for automatically sorting memory devices according to any preceding claim wherein the faulty addresses of each memory device is stored in a database.

7. A process for automatically sorting memory devices according to any of claims 1 to 4 wherein the faulty addresses of each set of memory devices is stored in a database entry.

8. A process for automatically populating memory modules with partially working memory devices where the partially working devices are to be used in a partial memory system which involves testing a memory device, recording the current faulty addresses relating to row and/or column drivers, comparing the current faulty addresses with faulty addresses of other devices in a first set of memory devices, if there are not more than a predetermined number of defective rows or columns with the same address in the first set as the current faulty addresses then the memory device is stored in that first set, if there are more than a predetermined number of defective row or columns with the same address then the next set is accessed and the current faulty addresses are compared with the faulty addresses of other devices in that next set. This process continues until all of the memory devices have been sorted into sets or all of the sets have been used.

9. A process for automatically populating memory modules according to claim 7 where the said memory modules are Single In-Line Memory Modules.