KR20060105042A - 기판의 이방성 에칭용 비정질 에칭 정지를 위한 방법,구조체 및 트랜지스터 - Google Patents
기판의 이방성 에칭용 비정질 에칭 정지를 위한 방법,구조체 및 트랜지스터 Download PDFInfo
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Abstract
Description
Claims (30)
- 기판 내로 리세스를 에칭하는 단계 -상기 리세스는 하부(bottom)를 가짐- 와,상기 리세스의 하부에 이온 종을 주입하여 비정질 에칭 정지 영역을 형성하는 단계 -상기 이온 종은 상기 기판 내에서 전기적으로 중성임- 와,이방성 습식 에칭으로 상기 기판을 에칭하는 단계를 포함하는 방법.
- 제 1 항에 있어서,상기 이온 종은 상기 기판과 동일한 성분인 방법.
- 제 2 항에 있어서,상기 기판은 실리콘이고, 상기 성분은 실리콘인 방법.
- 제 1 항에 있어서,상기 이온 종은 상기 기판에서 낮은 용해도를 갖는 방법.
- 제 4 항에 있어서,상기 이온 종은 그 이온 반경이 130pm보다 크거나 또는 이온 반경이 80pm 미만인 방법.
- 제 4 항에 있어서,상기 이온 종은 비활성 성분(noble element)인 방법.
- 제 1 항에 있어서,상기 기판은 수직 [100] 결정면 , 수평 [110] 결정면 및 대각선 [111] 결정면을 갖는 단결정이고, 상기 알칼린 이방성 습식 에칭으로 단결정을 에칭하는 것은 [100] 결정면에 대하여 [111] 결정면을 따라 패싯팅(faceting)을 야기시키는 방법.
- 제 7 항에 있어서,상기 알칼린 이방성 습식 에칭 용액은 대략 10 또는 그 이상의 pH를 갖는 방법.
- 제 7 항에 있어서,상기 알칼린 이방성 습식 에칭은 산화제를 포함하지 않는 방법.
- 제 1 항에 있어서,비정질 에칭 정지 영역을 형성하기 위해서 기판 내로 성분을 주입하는 단계는 대략 5×e14원자/㎠ 내지 1×e15원자/㎠ 범위의 도우즈(dose) 성분을 포함하는 방법.
- 제 1 항에 있어서,비정질 에칭 정지 영역을 형성하기 위해서 기판 내로 이온 종을 주입하는 단계는 대략 1KeV 내지 20 KeV의 범위 내의 주입 에너지를 포함하는 방법.
- 제 1 항에 있어서,상기 기판에 상기 리세스를 에칭하는 단계는 이방성 건식 플라즈마 에칭을 포함하는 방법.
- 기판 내에 이온 종을 주입하여 비정질 에칭 정지 영역을 형성하는 단계 -상기 이온 종은 상기 기판 내에서 전기적으로 중성임- 와,기판내에 리세스를 에칭하는 단계와,이방성 습식 에칭으로 상기 기판을 에칭하는 단계를 포함하는 방법.
- 제 13 항에 있어서,상기 이온 종을 상기 리세스에 주입하는 단계는 대략 1×e15원자/㎠ 내지 1×e16원자/㎠ 범위의 이온 종의 도우즈(dose)를 포함하는 방법.
- 제 13 항에 있어서,상기 이온 종으로 상기 리세스를 주입하는 단계는 대략 10KeV 내지 40KeV 범위의 주입 에너지를 포함하는 방법.
- 수직 [100] 결정면, 수평 [110] 결정면 및 대각선 [111] 결정면을 갖는 단결정 실리콘 기판 위에 게이트 및 상기 게이트의 양 측면에 한 쌍의 측벽 스페이서를 형성하는 단계와,이방성 건식 플라즈마 에칭으로 상기 수직 결정면 [100]을 따라 상기 단결정 실리콘 기판내에 리세스를 에칭하는 단계와,상기 리세스의 하부 내로 실리콘을 주입하여 비정질 에칭 정지를 형성하는 단계와,대략 적어도 10 pH를 갖고 산화제 없는 이방성 습식 에칭으로 대각선 결정면 [111]을 따라 상기 리세스를 에칭하는 단계와,전기적으로 도핑된 실리콘 게르마늄 물질로 상기 리세스를 충진하여 소스/드레인 영역을 형성하는 단계를 포함하는 방법.
- 제 16 항에 있어서,상기 측벽 스페이서 아래로 소스/드레인 팁 주입 영역을 더 포함하는 방법.
- 제 16 항에 있어서,얕은 트렌치 절연 영역은 산화물을 포함하며, 상기 이방성 습식 에칭은 상기 얕은 트렌치 절연 영역 또는 게이트를 보호하는 하드마스크를 에칭하지 않는 방법.
- 제 16 항에 있어서,상기 전기적으로 도핑된 실리콘 게르마늄 물질로 상기 리세스를 충진하는 단계는 상기 게이트 아래에 에피택셜 소스/드레인 팁 확장 영역을 형성하는 방법.
- 결정 격자를 갖는 기판을 제공하는 단계와,기판 내에서 전기적으로 중성인 이온 종으로 상기 기판의 결정 격자를 파괴하여 에칭 정지 영역을 형성하는 단계를 포함하는 방법.
- 제 20 항에 있어서,상기 기판의 결정 격자를 파괴하는 단계는 상기 결정 격자의 결정면 내에서 화학 결합을 파괴하는 단계를 포함하는 방법.
- 제 20 항에 있어서,상기 결정 격자를 파괴하는 단계는 상기 결정 격자의 화학적 결합을 파괴하기에 충분한 가속 에너지, 이온 반경 및 성분의 질량의 조합을 포함하는 방법.
- 다수의 수직 [100] 결정면, 다수의 수평 [110] 결정면 및 다수의 대각선 [111] 결정면을 갖고, 4개의 대각선 [111] 면에 따른 4개의 벽 및 수평 [110] 면에 따른 평탄한 하부를 갖는 역 절단된 원추(inverse truncated pyramid) 모양의 리세스를 갖는 기판과,상기 리세스의 평탄한 하부에서 상기 기판 내에 전기적으로 중성인 성분을 포함하고, 상기 기판의 표면을 보호하기 위해서 마스크로서 작용하는 비정질 에칭 정지 영역을 포함하는 구조체.
- 제 23 항에 있어서,상기 기판은 단결정 실리콘인 구조체.
- 제 24 항에 있어서,상기 성분은 실리콘인 구조체.
- 제 23 항에 있어서,상기 리세스는 대략 1:1 내지 1:5 범위 내의 종횡비를 갖는 구조체.
- 제 23 항에 있어서,상기 리세스 위로 돌출하는 캔틸레버를 더 포함하는 구조체.
- 다수의 수직 [100] 결정면, 다수의 수평 [110] 결정면 및 다수의 대각선 [111] 결정면을 갖는 결정질 반도체 기판과,상기 결정질 반도체 기판 위로 형성된 게이트 전극과,상기 게이트 전극의 양 측면의 한 쌍의 측벽 스페이서와,상기 각각의 측벽 스페이서 아래에 존재하며, 상기 스페이서의 하부에 의해 그리고 상기 대각선 [111] 결정면에 의해 규정되는 한 쌍의 소스/드레인 영역을 포함하는 트랜지스터.
- 제 28 항에 있어서,상기 한 쌍의 소스/드레인 영역은 상기 한 쌍의 측벽 스페이서 중 하나의 폭까지의 거리 만큼 상기 한 쌍의 측벽 스페이서 아래로 확장하는 트랜지스터.
- 제 28 항에 있어서,상기 한 쌍의 소스/드레인 영역은 상기 게이트 전극의 폭의 대략 10% 내지 20%의 범위의 거리 만큼 상기 게이트 전극 아래로 확장하는 트랜지스터.
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KR101237664B1 (ko) * | 2007-03-28 | 2013-02-26 | 인텔 코포레이션 | 자기 정렬된 소스 확장부 및 드레인 확장부를 갖는 트랜지스터 |
KR20140063702A (ko) * | 2011-08-15 | 2014-05-27 | 킹 압둘라 유니버시티 오브 사이언스 앤드 테크놀로지 | 기계적 가요성 실리콘 기판 제조 방법 |
US8883651B2 (en) | 2011-08-19 | 2014-11-11 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
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TWI250576B (en) | 2006-03-01 |
DE112004002611B4 (de) | 2009-12-31 |
TW200522196A (en) | 2005-07-01 |
WO2005067021A1 (en) | 2005-07-21 |
DE112004002611T5 (de) | 2006-11-09 |
CN1902736A (zh) | 2007-01-24 |
US20050148147A1 (en) | 2005-07-07 |
CN100499028C (zh) | 2009-06-10 |
KR100810774B1 (ko) | 2008-03-06 |
US7045407B2 (en) | 2006-05-16 |
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