CN102810480B - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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CN102810480B
CN102810480B CN201110147173.2A CN201110147173A CN102810480B CN 102810480 B CN102810480 B CN 102810480B CN 201110147173 A CN201110147173 A CN 201110147173A CN 102810480 B CN102810480 B CN 102810480B
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substrate
wet etching
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CN102810480A (zh
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张翼英
何其旸
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Semiconductor Manufacturing International Beijing Corp
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Abstract

本公开实施例提供了一种半导体器件制造方法，包括以下步骤：在衬底上形成栅极，栅极上形成有顶部掩模层；形成位于所述栅极两侧侧壁上的侧壁间隔件；以所述顶部掩模层和所述侧壁间隔件为掩模，改变在相邻的侧壁间隔件之间的衬底的一部分的特性；利用各向同性湿法刻蚀，去除具有改变的特性的衬底部分，以在衬底中形成凹槽；以及对所述凹槽进行晶向选择性的湿法刻蚀，以将所述凹槽的内壁形成为具有∑形状。本公开实施例的方法通过采用改变衬底特性的工艺与各向同性湿法刻蚀处理相结合来代替使用干法刻蚀，由此避免了对衬底的损伤，从而能够获得良好的外延生长性能。

Description

半导体器件的制造方法
技术领域
本公开涉及制造半导体器件的方法，尤其是涉及制造包括具有嵌入式SiGe(eSiGe)的PMOS器件的半导体器件的方法。
背景技术
为了满足终端用户对小尺寸电子器件的需求，在改进的超大规模集成电路(VLSI)工艺中，采用应力技术来提高器件的性能。其中一种有效的方法是采用嵌入式SiGe(eSiGe)结构来提高PMOS器件沟道区的空穴迁移率。
在∑形状的eSiGe结构中，由于SiGe的晶格常数大于Si的晶格常数，而且∑形状的SiGe减小了源区和漏区之间的间距，所以有效地增大了沟道区中的应力。
图1A至1D示出了现有技术的在PMOS器件中形成∑形SiGe的方法。在Si衬底之上形成栅极以及位于栅极两侧侧壁上的侧壁间隔件(参见图1A)之后，通过干法刻蚀，在相邻栅极之间的Si衬底中形成凹槽，如图1B所示。图1B中所示的凹槽基本上是截面由A、B、C和D四个顶点限定的平底矩形形状。
接着，如图1C所示，对形成的矩形凹槽进行晶向选择性的湿法刻蚀，从而将该矩形凹槽扩展为∑形状。通常，晶向选择性的湿法刻蚀沿(100)晶面刻蚀得比沿(111)晶面快。实际上，这里晶向选择性的湿法刻蚀沿(111)晶面基本上刻蚀不动。结果是，如图1C所示，在图1B中的干法刻蚀之后形成的凹槽的C和D两个顶点作为(111)晶向的刻蚀停止点而保留。最后，如图1D所示，在所形成的∑形凹槽中外延生长SiGe，从而形成SiGe的源区和漏区。
本发明的发明人在对形成∑形SiGe的方法进行深入研究后发现上述现有技术的方法存在难以外延生长SiGe的问题。
具体而言，在图1B所示的对衬底进行干法刻蚀的工艺中，由于等离子体的连续轰击使得所形成的矩形凹槽边缘处，尤其是图1B中示出的C和D顶点处，出现Si晶格失配等缺陷。如前所述，作为晶向选择性的湿法刻蚀的结果，C和D两点成为(111)晶向的刻蚀停止点而保留不会被刻蚀掉。后续的SiGe外延生长工艺中，籽层对于Si的表面状况(例如，清洁度、Si晶格情况)非常敏感。诸如Si晶格适配等缺陷会导致籽层难以生长。因此，如图1E所示，C和D处出现的Si晶格缺陷会使得在后续工艺中难以外延生长SiGe籽层。
发明内容
为了消除或者至少部分地减轻现有技术中的上述问题，提出了本发明。
鉴于干法刻蚀处理会对衬底造成损伤，本公开的实施例采用诸如离子注入或氧化处理的改变衬底特性的工艺与各向同性湿法刻蚀处理相结合，来代替使用干法刻蚀，由此避免了对衬底造成损伤及对后续SiGe外延生长的不利影响。
本公开的实施例提供了一种制造半导体器件的方法，包括以下步骤：在衬底上形成栅极，栅极上形成有顶部掩模层；形成位于所述栅极两侧侧壁上的侧壁间隔件；以所述顶部掩模层和所述侧壁间隔件为掩模，改变在相邻的侧壁间隔件之间的衬底的一部分的特性；利用各向同性湿法刻蚀，去除具有改变的特性的衬底部分，以在衬底中形成凹槽；以及对所述凹槽进行晶向选择性的湿法刻蚀，以将所述凹槽的内壁形成为具有∑形状。
在一个实施例中，所述改变在相邻的侧壁间隔件之间的衬底的一部分的特性的步骤包括：通过对所述衬底进行离子注入或氧化处理来改变在相邻的侧壁间隔件之间的衬底的一部分的特性。
在一个实施例中，所述氧化处理包括热氧化或等离子体氧化工艺。
在一个实施例中，所述离子注入工艺包括向所述衬底注入以下离子中的任一种或多种：砷、硼、锗或者碳。
在一个实施例中，对所述衬底进行离子注入的步骤包括：以不超过100keV的能量向所述衬底前非晶化注入(PAI)锗或者碳离子达1013至1015离子/cm2的注入量。
在一个实施例中，所述顶部掩模层是硅氮化物。
在一个实施例中，所述顶部掩模层的厚度是基于包括该顶部掩模层的材料、注入离子的种类以及注入能量的参数来选择的。
在一个实施例中，在注入砷离子且所述顶部掩模层为Si3N4的情况下，所述顶部掩模层的厚度与注入能量的关系是：
Thk＝4.2X+25.5，
其中，Thk表示所述顶部掩模层的厚度，单位是埃；
X表示注入砷离子的能量，单位是keV。
在一个实施例中，所述对所述凹槽进行晶向选择性的湿法刻蚀的步骤包括：采用四甲基氢氧化铵(TMAH)对所述凹槽进行湿法刻蚀。
在一个实施例中，所述晶向选择性的湿法刻蚀沿(100)晶面比沿(111)晶面的刻蚀速率快。
在一个实施例中，所述晶向选择性的湿法刻蚀沿(111)晶面基本上刻蚀不动。
在一个实施例中，在所述衬底上形成的栅极为多晶硅栅。
在一个实施例中，所述方法还包括在改变相邻的侧壁间隔件之间的衬底的一部分的特性之前在所述衬底中进行离子注入以形成源区和漏区。
在一个实施例中，所述方法还包括在对所述凹槽进行晶向选择性的湿法刻蚀之后在所述衬底中进行离子注入以形成源区和漏区。
在一个实施例中，在对所述凹槽进行晶向选择性的湿法刻蚀之前，所述凹槽的深度约为300埃至500埃。
本公开实施例的方法通过采用改变衬底特性的工艺与各向同性湿法刻蚀处理相结合来代替使用干法刻蚀，由此避免了对衬底的损伤，从而能够获得良好的外延生长性能。
附图说明
在阅读了以下具体描述并参考附图的情况下，本发明的其它方面将变得显而易见。各附图中相同的附图标记将指代相同的部件或步骤。附图中：
图1A至1D示出了现有技术的在PMOS器件中形成∑形SiGe的方法。其中，图1A示出了在衬底上形成的栅极和位于栅极两侧侧壁上的侧壁间隔件；图1B示出了通过干法刻蚀在相邻栅极之间的衬底中形成的大体矩形的凹槽；图1C示出了对形成的矩形凹槽进行晶向选择性的湿法刻蚀，从而将该矩形凹槽扩展为∑形状；图1D示出了在所形成的∑形凹槽中外延生长SiGe，从而形成SiGe的源区和漏区。
图1E示出了图1A至1D中描述的现有技术方法的缺陷。
图2是示意性地示出了根据本公开实施例的在PMOS器件中形成∑形SiGe的方法的流程图。
图3A至3D是示意性地示出在图2中的形成∑形SiGe的方法中的各步骤的截面图。其中，图3A示出了在衬底上形成的栅极、覆盖在栅极上的顶部掩模层以及位于栅极两侧侧壁上的侧壁间隔件；图3B示出了以顶部掩模层为掩模，通过离子注入处理改变相邻的侧壁间隔件之间的衬底的一部分的特性；图3C示出了利用各向同性湿法刻蚀，去除具有改变的特性的衬底部分，以在该衬底部分中形成大体矩形的凹槽；以及图3D示出了对大体矩形凹槽进行晶向选择性的湿法刻蚀，从而将该凹槽扩展为∑形状。
具体实施方式
下面参照附图详细描述本发明的示例性实施例。应注意，以下的描述在本质上仅是解释性的。除非另外特别说明，否则，在实施例中阐述的部件和步骤并不限制本发明的范围。另外，对本领域技术人员已知的技术、方法和装置可能没有进行详细讨论，但在适当的情况下意在成为说明书的一部分。
在本公开的实施例中，代替采用会损伤衬底的晶格结构的干法刻蚀，而是先采用诸如离子注入或氧化处理的工艺改变衬底的预定部分的特性；然后利用各向同性湿法刻蚀去除具有改变的特性的衬底部分，以在衬底中形成大体矩形的凹槽；最后，利用晶向选择性的湿法刻蚀，将凹槽的内壁形成为具有∑形状。
本公开实施例的方法以改变衬底特性的工艺和各向同性湿法刻蚀处理相结合来替代干法刻蚀处理，由此避免了对衬底造成损伤及对后续SiGe外延生长的不利影响。
图2示意性地示出了根据本公开实施例的在PMOS器件中形成∑形SiGe的方法的流程图。图3A至3D是示意性地示出在图2中的形成∑形SiGe的方法中的各步骤的截面图。下面将参照图2和图3A至3D来详细描述本公开的实施例。
首先，在图2的步骤S210中，提供衬底并在衬底300上形成栅极301，在栅极301顶部形成有顶部掩模层302，并且在栅极两侧侧壁上形成有侧壁间隔件303(参见图3A)。衬底例如可以由硅制成。这里的栅极例如可以是多晶硅栅。顶部掩模层302和侧壁间隔件303用于在随后的离子注入或氧化处理、湿法刻蚀以及源区/漏区离子注入工艺中保护栅极301。顶部掩模层302例如可以是硅氮化物，侧壁间隔件303例如可以是硅氮化物或者硅氧化物。栅极301，顶部掩模层302以及侧壁间隔件303的形成可以利用本领域技术人员公知的工艺实现，在此不再赘述。
接着，在图2的步骤S220中，如图3B所示，以顶部掩模层302和侧壁间隔件303为掩模，改变在相邻的侧壁间隔件303之间的衬底300的预定部分304的物质特性，例如，将衬底预定部分304中的硅改变为非晶状态。
在一些实施例中，可以通过对衬底300进行离子注入来实现对预定部分304的特性的改变。例如可以向衬底300注入砷、硼、锗或者碳中的任一种或多种。在一个示例中，可以在不超过100keV的能量下，向衬底300进行前非晶化注入(PAI)锗或者碳离子达1013至1015离子/cm2的注入量。
需要指出的是，尽管这里以示例的形式描述了可以向衬底注入砷、硼、锗或者碳等离子，但是本领域技术人员应当理解，也可以注入其他离子，只要能改变衬底部分的物质特性，同时便于后续的去除处理即可。同样，尽管上面以示例的形式描述了采用前非晶化注入工艺，但是采用其他类型的注入工艺也是可以的，例如集束离子注入工艺。
在对衬底300进行离子注入时，需要确保顶部掩模层302的厚度足以保护栅极不会受到离子注入的影响。通常，基于诸如顶部掩模层302的材料、注入离子的种类以及注入能量等参数来选择顶部掩模层302的厚度。在一个示例中，在注入砷离子且顶部掩模层302由Si3N4制成的情况下，顶部掩模层302的厚度与注入能量的关系是：
Thk＝4.2X+25.5(式1)
其中，Thk表示顶部掩模层302的厚度，单位是埃；X表示注入砷离子的能量，单位是keV。
除了采用离子注入，在另一些实施例中，还可以通过氧化处理来改变在相邻的侧壁间隔件303之间的衬底300的预定部分304的物质特性。可以采用包括热氧化或等离子体氧化工艺在内的本领域公知的氧化处理，优选地，采用湿法氧化处理。在一个示例中，在700℃至1200℃的温度下对衬底预定部分304进行氧化。
然后，在图2的步骤S230中，利用各向同性湿法刻蚀，去除具有改变的特性的衬底部分304，以在衬底中形成凹槽305，如图3C所示。这里，例如可以选择针对改变特性的衬底部分304和没有改变特性的衬底部分具有高刻蚀选择比的湿法刻蚀处理，来形成凹槽305。在一个实施例中，在步骤S220中通过氧化处理将衬底部分304形成为硅氧化物的情况下，可以采用HF酸溶液来将其去除。例如，可以采用H2O与HF的质量比例为100∶1或者50∶1的溶液，在23±0.5℃的温度下，进行上述湿法刻蚀处理。在一个示例中，凹槽305的深度H例如可以是大约300埃至大约500埃。
最后，在图2的步骤S240中，对凹槽305进行晶向选择性的湿法刻蚀，以将凹槽305的内壁形成为具有∑形状，如图3D所示。在一个实施例中，可以采用沿(100)晶面比沿(111)晶面刻蚀速率快的晶向选择性的湿法刻蚀处理。例如，可以采用质量浓度为10％至25％的四甲基氢氧化铵(TMAH)在温度70℃至90℃下进行刻蚀。在这种情况下，沿(111)晶面基本上刻蚀不动。
需要注意的是，可以在改变相邻的侧壁间隔件之间的衬底的一部分的特性(即，图2中的步骤S220)之前或者在对凹槽进行晶向选择性的湿法刻蚀(即，图2中的步骤S240)之后，在衬底中进行离子注入以形成源区和漏区。
如前所述，本公开实施例的方法以改变衬底特性的工艺和各向同性湿法刻蚀处理相结合来替代干法刻蚀处理，由此避免了对衬底造成损伤，从而能够获得良好的SiGe外延生长性能。
需要注意的是，eSiGe结构作为源区和漏区一般只是用于PMOS晶体管。因此，对于同时包括PMOS晶体管和NMOS晶体管的半导体器件，在为PMOS晶体管形成∑形状的过程中，需要用掩模等覆盖住NMOS晶体管部分。
尽管已经参考特定实施例对本发明进行了描述，但是应当理解，实施例是例示性的，而且本发明的范围不受限于此。对所述实施例的任何变化、修改、添加和改进都是可能的。这些变化、修改、添加和改进落入如以下权利要求中详述的本发明的范围内。

Claims (18)

1.一种制造半导体器件的方法，包括以下步骤：
在衬底上形成栅极，栅极上形成有顶部掩模层；
形成位于所述栅极两侧侧壁上的侧壁间隔件；
以所述顶部掩模层和所述侧壁间隔件为掩模，改变在相邻的侧壁间隔件之间的衬底的一部分的特性；
利用各向同性湿法刻蚀，去除具有改变的特性的衬底部分，以在衬底中形成矩形的凹槽；以及
对所述凹槽进行晶向选择性的湿法刻蚀，以将所述凹槽的内壁形成为具有∑形状。
2.如权利要求1所述的方法，其中，所述改变在相邻的侧壁间隔件之间的衬底的一部分的特性的步骤包括：通过对所述衬底进行离子注入来改变在相邻的侧壁间隔件之间的衬底的一部分的特性。
3.如权利要求2所述的方法，其中，所述离子注入工艺包括向所述衬底注入以下离子中的任一种或多种：砷、硼、锗或者碳。
4.如权利要求2所述的方法，其中，对所述衬底进行离子注入的步骤包括：以不超过100keV的能量向所述衬底前非晶化注入锗或者碳离子达1013至1015离子/cm2的注入量。
5.如权利要求1或2所述的方法，其中，所述顶部掩模层是硅氮化物。
6.如权利要求2所述的方法，其中，所述顶部掩模层的厚度是基于包括该顶部掩模层的材料、注入离子的种类以及注入能量的参数来选择的。
7.如权利要求6所述的方法，其中，在注入砷离子且所述顶部掩模层为Si3N4的情况下，所述顶部掩模层的厚度与注入能量的关系是：
Thk＝4.2X+25.5，
其中，Thk表示所述顶部掩模层的厚度，单位是埃；
X表示注入砷离子的能量，单位是keV。
8.如权利要求1所述的方法，其中，所述改变在相邻的侧壁间隔件之间的衬底的一部分的特性的步骤包括：通过对所述衬底进行氧化处理来改变在相邻的侧壁间隔件之间的衬底的一部分的特性。
9.如权利要求8所述的方法，其中，所述氧化处理包括湿法氧化工艺。
10.如权利要求1所述的方法，其中，所述对所述凹槽进行晶向选择性的湿法刻蚀的步骤包括：采用四甲基氢氧化铵对所述凹槽进行湿法刻蚀。
11.如权利要求1或10所述的方法，其中，所述晶向选择性的湿法刻蚀沿(100)晶面比沿(111)晶面的刻蚀速率快。
12.如权利要求11所述的方法，其中，所述晶向选择性的湿法刻蚀沿(111)晶面刻蚀不动。
13.如权利要求1所述的方法，其中，在所述衬底上形成的栅极为多晶硅栅。
14.如权利要求1所述的方法，还包括：在进行晶向选择性的湿法刻蚀将凹槽形成为∑形状之后，在该∑形状的凹槽内外延生长SiGe。
15.如权利要求1所述的方法，还包括在改变相邻的侧壁间隔件之间的衬底的一部分的特性之前在所述衬底中进行离子注入以形成源区和漏区。
16.如权利要求14所述的方法，还包括在∑形状的凹槽内外延生长SiGe之后在所述衬底中进行离子注入以形成源区和漏区。
17.如权利要求1所述的方法，其中，在对所述凹槽进行晶向选择性的湿法刻蚀之前，所述凹槽的深度为300埃至500埃。
18.如权利要求1所述的方法，还包括在改变相邻的侧壁间隔件之间的衬底的一部分的特性之前，在要形成NMOS器件的区域上方形成掩模，而暴露要形成PMOS器件的区域。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11889678B2 (en) 2020-05-12 2024-01-30 Changxin Memory Technologies, Inc. Method of manufacturing buried word line structure and semiconductor memory thereof

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681338B (zh) * 2012-09-18 2016-06-08 中芯国际集成电路制造(上海)有限公司 半导体器件及其制造方法
CN103151257B (zh) * 2013-03-14 2016-03-23 上海华力微电子有限公司 一种σ型硅沟槽的制造方法
CN103178014B (zh) * 2013-03-14 2016-01-27 上海华力微电子有限公司 一种u型沟槽的制造方法
CN104103515B (zh) * 2013-04-02 2017-02-08 中芯国际集成电路制造(上海)有限公司 Pmos晶体管的制作方法与nmos晶体管的制作方法
CN104183493B (zh) * 2013-05-21 2016-10-05 中芯国际集成电路制造(上海)有限公司 Pmos晶体管的制作方法
US9246003B2 (en) 2013-11-19 2016-01-26 Globalfoundries Inc. FINFET structures with fins recessed beneath the gate
US20150194311A1 (en) * 2014-01-08 2015-07-09 Macronix International Co., Ltd. Method For Manufacturing Semiconductor Device
CN104851783B (zh) * 2014-02-14 2018-05-01 中芯国际集成电路制造(上海)有限公司 一种锗硅硼外延层生长方法
CN104934311B (zh) * 2014-03-17 2018-08-03 中芯国际集成电路制造(上海)有限公司 刻蚀方法、在半导体基材上形成凹槽的方法、pmos晶体管及其制作方法
CN103887176B (zh) * 2014-03-20 2016-08-24 上海华力微电子有限公司 一种降低源漏外延生长缺陷的方法
CN105226021A (zh) * 2014-06-26 2016-01-06 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN105448736B (zh) * 2014-09-26 2019-01-22 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
US9601333B2 (en) * 2014-10-02 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Etching process
US20170141228A1 (en) * 2015-11-16 2017-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Field effect transistor and manufacturing method thereof
CN108807178B (zh) * 2017-05-05 2022-08-23 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN110246803A (zh) * 2018-03-08 2019-09-17 联华电子股份有限公司 半导体元件及其制作方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1399319A (zh) * 2001-07-19 2003-02-26 三星电子株式会社 Mos晶体管及其制造方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6030863A (en) * 1998-09-11 2000-02-29 Taiwan Semiconductor Manufacturing Company Germanium and arsenic double implanted pre-amorphization process for salicide technology
US6426254B2 (en) * 1999-06-09 2002-07-30 Infineon Technologies Ag Method for expanding trenches by an anisotropic wet etch
US7045407B2 (en) * 2003-12-30 2006-05-16 Intel Corporation Amorphous etch stop for the anisotropic etching of substrates
US6946350B2 (en) * 2003-12-31 2005-09-20 Intel Corporation Controlled faceting of source/drain regions
JP2006173491A (ja) * 2004-12-17 2006-06-29 Fujitsu Ltd 半導体装置およびその製造方法
US7303999B1 (en) * 2005-12-13 2007-12-04 Lam Research Corporation Multi-step method for etching strain gate recesses
TWI277153B (en) * 2006-03-21 2007-03-21 Promos Technologies Inc Semiconductor device with recessed channel and method of fabricating the same
US7732285B2 (en) * 2007-03-28 2010-06-08 Intel Corporation Semiconductor device having self-aligned epitaxial source and drain extensions
US7691752B2 (en) * 2007-03-30 2010-04-06 Intel Corporation Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby
US20090035911A1 (en) * 2007-07-30 2009-02-05 Willy Rachmady Method for forming a semiconductor device having abrupt ultra shallow epi-tip regions
CN101364545B (zh) * 2007-08-10 2010-12-22 中芯国际集成电路制造(上海)有限公司 应变硅晶体管的锗硅和多晶硅栅极结构
JP5315889B2 (ja) * 2008-09-22 2013-10-16 富士通セミコンダクター株式会社 半導体装置の製造方法
US7951657B2 (en) * 2009-05-21 2011-05-31 International Business Machines Corporation Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor
US8492234B2 (en) * 2010-06-29 2013-07-23 International Business Machines Corporation Field effect transistor device
CN103098046B (zh) * 2010-07-20 2016-04-13 惠普发展公司，有限责任合伙企业 将系统监视信息格式化的系统和方法
US8329547B2 (en) * 2010-07-22 2012-12-11 United Microelectronics Corp. Semiconductor process for etching a recess into a substrate by using an etchant that contains hydrogen peroxide
US8709897B2 (en) * 2010-11-30 2014-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. High performance strained source-drain structure and method of fabricating the same
US8334185B2 (en) * 2011-04-19 2012-12-18 Globalfoundries Inc. Early embedded silicon germanium with insitu boron doping and oxide/nitride proximity spacer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1399319A (zh) * 2001-07-19 2003-02-26 三星电子株式会社 Mos晶体管及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11889678B2 (en) 2020-05-12 2024-01-30 Changxin Memory Technologies, Inc. Method of manufacturing buried word line structure and semiconductor memory thereof

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