JP2006237263A - 半導体集積回路装置およびその製造方法 - Google Patents
半導体集積回路装置およびその製造方法 Download PDFInfo
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Abstract
【解決手段】 引張り応力膜のうち、pチャネルMOSトランジスタを覆う部分の少なくともゲート電極基部近傍に、Geを斜め方向からイオン注入により、導入されたGeイオンが側壁絶縁膜表面近傍にまで到達するように導入する工程と、さらにGeをイオン注入した引張り応力膜を、Ge濃度の高い部分において選択エッチングして除去し、pチャネルMOSトランジスタのゲート電極側壁面を覆う引張り応力膜の引張り応力が、前記ゲート電極直下のチャネル領域に伝達される応力伝播経路を遮断する。
【選択図】 図5
Description
図4〜6は、本発明の第1実施例による半導体集積回路装置の製造工程を示す図である。
[第2実施例]
図8〜11は、本発明の第2実施例による半導体集積回路装置の製造工程を示す図である。ただし図中、先に説明した部分に対応する部分には同一の参照符号を付し、その説明を省略する。
基板と、
前記基板上に素子分離領域により画成された第1および第2の素子領域と、
前記第1の素子領域に形成されたnチャネルMOSトランジスタと、
前記第2の素子領域に形成されたpチャネルMOSトランジスタとよりなり、
前記nチャネルMOSトランジスタは、
前記第1の素子領域中において前記nチャネルMOSトランジスタのチャネル領域に対応して、第1のゲート絶縁膜を介して形成され、両側壁面上に側壁絶縁膜を担持し、n型にドープされた第1のゲート電極と、
前記第1の素子領域中、前記第1のゲート電極の両側に形成された、n型のソースおよびドレイン領域と、
前記第2の素子領域中において前記pチャネルMOSトランジスタのチャネル領域に対応して、第2のゲート絶縁膜を介して形成され、両側壁面上に側壁絶縁膜を担持し、p型にドープされた第2のゲート電極と、
前記第2の素子領域中、前記第2のゲート電極の両側に形成された、p型のソースおよびドレイン領域とよりなる半導体集積回路装置において、
前記基板上には、前記第1および第2の素子領域にわたって、前記第1の素子領域においては前記第1のゲート電極を、その側壁絶縁膜を含めて連続的に覆うように、また前記第2の素子領域においては前記第2のゲート電極を、その側壁絶縁膜を含めて覆うように形成され、引張り応力を蓄積した引張り応力膜が形成され、
前記引張り応力膜は、前記第2の素子領域中、少なくとも前記第2のゲート電極の基部近傍において膜厚を減少させていることを特徴とする半導体集積回路装置。
前記引張り応力膜は、前記第2のゲート電極の基部近傍において欠損していることを特徴とする付記1記載の半導体集積回路装置。
前記第2のゲート電極の基部近傍において、前記第2のゲート電極の側壁絶縁膜が、前記引張り応力膜から露出されていることを特徴とする請求項1または2記載の半導体集積回路装置。
前記第2の素子領域において、前記露出された側壁絶縁膜は、Geを含むことを特徴とする付記3記載の半導体集積回路装置。
前記第2のゲート電極の基部近傍において、前記pチャネルMOSトランジスタのソースおよびドレイン領域が、前記引張り応力膜から露出されており、前記ソースおよびドレイン領域の露出部は、Geを含むことを特徴とする付記1〜4のうち、いずれか一項記載の半導体集積回路装置。
前記ソースおよびドレイン領域の露出部には、シリサイド層が形成されており、前記シリサイド層がGeを含むことを特徴とする付記5記載の半導体集積回路装置。
前記引張り応力膜は、シリコン窒化膜よりなることを特徴とする付記1〜6のうち、いずれか一項記載の半導体集積回路装置。
前記基板上には、前記第1および第2の素子領域にわたり層間絶縁膜が、前記第1および第2のゲート電極を、前記引張り応力膜を介して覆うように形成されており、
前記層間絶縁膜中には、前記第1の素子領域において、前記nチャネルMOSトランジスタのn型ソース領域およびドレイン領域と、前記引っ張り応力膜中に形成された開口部を介してコンタクトする一対のコンタクトプラグが形成されており、
さらに前記層間絶縁膜中には、前記第2の素子領域において、前記pチャネルMOSトランジスタのp型ソース領域およびドレイン領域と、前記引っ張り応力膜中に形成された開口部を介してコンタクトする別の一対のコンタクトプラグが形成されていることを特徴とする付記1〜7のうち、いずれか一項記載の半導体集積回路装置。
基板上に素子分離領域により画成された第1および第2の素子領域に、それぞれnチャネルMOSトランジスタおよびpチャネルMOSトランジスタを形成する工程と、
前記基板上に、前記第1および第2の素子領域を、前記nチャネルMOSトランジスタのゲート電極および前記pチャネルMOSトランジスタのゲート電極を、それぞれの側壁絶縁膜を含めて連続的に覆うように、引張り応力膜を、引張り応力を蓄積するように形成する工程と、
前記第2の素子領域において、前記引張り応力膜に、前記基板の面に対して斜めに、前記引張り応力膜中の引張り応力を緩和する元素をイオン注入する工程とよりなり、
前記イオン注入工程は、前記引張り応力膜中に、前記引張り応力膜中の引張り応力を緩和するような元素を、少なくとも前記第2のゲート電極の基部近傍において、前記第2のゲート電極の側壁絶縁膜に到達するようなエネルギで導入することを特徴とする半導体集積回路装置の製造方法。
前記イオン注入工程の後、前記引張り応力膜を前記第2の素子領域において、エッチングする工程をさらに含むことを特徴とする付記9記載の半導体集積回路装置の製造方法。
前記エッチング工程は、前記引張り応力膜のうち、前記元素が導入された部分が優先的に除去されるように実行されることを特徴とする付記10記載の半導体集積回路装置の製造方法。
前記元素はGeであり、前記引張り応力膜はシリコン窒化膜よりなり、前記エッチング工程は、燐酸を使って実行されることを特徴とする付記11記載の半導体集積回路装置の製造方法。
さらに、前記基板上に前記第1および第2の素子領域にわたり層間絶縁膜を、前記層間絶縁膜が前記第1および第2のゲート電極を、前記引張り応力膜を介して覆うように形成する工程と、
前記層間絶縁膜中に、前記nチャネルMOSトランジスタのソース領域およびドレイン領域、および前記pチャネルMOSトランジスタのソース領域およびドレイン領域にそれぞれ対応するコンタクトホールを、前記引張り応力膜をエッチングストッパとして形成する工程と、
前記コンタクトホールにおいて、前記引張り応力膜を選択的にエッチング除去する工程を含むことを特徴とする付記9〜12のうち、いずれか一項記載の半導体集積回路装置の製造方法。
11A,11B、41A,41B 素子領域
11I,41I 素子分離領域
11a,21a,41a,41e ソースエクステンション領域
11b,21b,41b,41f ドレインエクステンション領域
11c,21c,41c,41g ソース領域
11d,21d,41d,41h ドレイン領域
12,42A,42B ゲート絶縁膜
13,43A,43B ゲート電極
13A,13B,23A,23B,44A,44B 側壁絶縁膜
14A〜14C,24A〜24C,41SA,41SB,43SA,43SB シリサイド層
15,45 引張り応力膜
41SG SiGe混晶層再成長領域
41TA,41TB 溝部
45X,45Y 引張り応力膜薄膜部
46 層間絶縁膜
46A〜46D コンタクトホール
47A〜47D コンタクトプラグ
Claims (6)
- 基板と、
前記基板上に素子分離領域により画成された第1および第2の素子領域と、
前記第1の素子領域に形成されたnチャネルMOSトランジスタと、
前記第2の素子領域に形成されたpチャネルMOSトランジスタとよりなり、
前記nチャネルMOSトランジスタは、
前記第1の素子領域中において前記nチャネルMOSトランジスタのチャネル領域に対応して、第1のゲート絶縁膜を介して形成され、両側壁面上に側壁絶縁膜を担持し、n型にドープされた第1のゲート電極と、
前記第1の素子領域中、前記第1のゲート電極の両側に形成された、n型のソースおよびドレイン領域と、
前記第2の素子領域中において前記pチャネルMOSトランジスタのチャネル領域に対応して、第2のゲート絶縁膜を介して形成され、両側壁面上に側壁絶縁膜を担持し、p型にドープされた第2のゲート電極と、
前記第2の素子領域中、前記第2のゲート電極の両側に形成された、p型のソースおよびドレイン領域とよりなる半導体集積回路装置において、
前記基板上には、前記第1および第2の素子領域にわたって、前記第1の素子領域においては前記第1のゲート電極を、その側壁絶縁膜を含めて連続的に覆うように、また前記第2の素子領域においては前記第2のゲート電極を、その側壁絶縁膜を含めて覆うように引張り応力膜が形成され、
前記引張り応力膜は、前記第2の素子領域中、少なくとも前記第2のゲート電極の基部近傍において膜厚を減少させていることを特徴とする半導体集積回路装置。 - 前記引張り応力膜は、前記第2のゲート電極の基部近傍において欠損していることを特徴とする請求項1記載の半導体集積回路装置。
- 前記第2のゲート電極の基部近傍において、前記第2のゲート電極の側壁絶縁膜が、前記引張り応力膜から露出されていることを特徴とする請求項1または2記載の半導体集積回路装置。
- 基板上、素子分離領域により画成された第1および第2の素子領域に、それぞれnチャネルMOSトランジスタおよびpチャネルMOSトランジスタを形成する工程と、
前記基板上に、前記第1および第2の素子領域を、前記nチャネルMOSトランジスタのゲート電極および前記pチャネルMOSトランジスタのゲート電極を、それぞれの側壁絶縁膜を含めて連続的に覆うように、引張り応力膜を、引張り応力を蓄積するように形成する工程と、
前記第2の素子領域において、前記引張り応力膜に、前記基板の面に対して斜めに、前記引張り応力膜中の引張り応力を緩和する元素をイオン注入する工程とよりなり、
前記イオン注入工程は、前記引張り応力膜中に、前記引張り応力膜中の引張り応力を緩和するような元素を、少なくとも前記第2のゲート電極の基部近傍において、前記第2のゲート電極の側壁絶縁膜に到達するようなエネルギで導入することを特徴とする半導体集積回路装置の製造方法。 - さらに前記イオン注入工程の後、前記引張り応力膜を前記第2の素子領域において、エッチングする工程をさらに含むことを特徴とする付記4記載の半導体集積回路装置の製造方法。
- 前記エッチング工程は、前記引張り応力膜のうち、前記元素が導入された部分が優先的に除去されるように実行されることを特徴とする請求項5記載の半導体集積回路装置の製造方法。
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JP2009170523A (ja) * | 2008-01-11 | 2009-07-30 | Rohm Co Ltd | 半導体装置およびその製造方法 |
WO2011083523A1 (ja) * | 2010-01-07 | 2011-07-14 | パナソニック株式会社 | 半導体装置及びその製造方法 |
CN102849663A (zh) * | 2012-09-15 | 2013-01-02 | 侯如升 | 一种液压拖车的拉手装置 |
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US20060186557A1 (en) | 2006-08-24 |
US7202120B2 (en) | 2007-04-10 |
US20070148835A1 (en) | 2007-06-28 |
US7476941B2 (en) | 2009-01-13 |
JP4361886B2 (ja) | 2009-11-11 |
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