CN102810481B - 半导体器件的制造方法 - Google Patents
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Abstract
本公开实施例提供了一种半导体器件制造方法,包括:在衬底上形成栅极,栅极上形成有顶部掩模层;形成位于所述栅极两侧侧壁上的侧壁间隔件;以所述顶部掩模层为掩模,对所述衬底进行干法刻蚀,以在相邻的侧壁间隔件之间的衬底中形成凹槽;对所述凹槽进行氧化,以围绕所述凹槽的内壁形成衬里氧化物层;通过各向同性湿法刻蚀,去除所述衬里氧化物层;对所述凹槽进行晶向选择性的湿法刻蚀,以将所述凹槽的内壁形成为具有∑形状。本公开实施例的方法利用氧化处理和湿法刻蚀处理去除了被干法刻蚀损伤的有晶格缺陷的衬底部分,从而能够获得良好的外延生长性能。
Description
技术领域
本公开涉及制造半导体器件的方法,尤其是涉及制造包括具有嵌入式SiGe(eSiGe)的PMOS器件的半导体器件的方法。
背景技术
为了满足终端用户对小尺寸电子器件的需求,在改进的超大规模集成电路(VLSI)工艺中,采用应力技术来提高器件的性能。其中一种有效的方法是采用嵌入式SiGe(eSiGe)结构来提高PMOS器件沟道区的空穴迁移率。
在∑形状的eSiGe结构中,由于SiGe的晶格常数大于Si的晶格常数,而且∑形状的SiGe减小了源区和漏区之间的间距,所以有效地增大了沟道区中的应力。
图1A至1D示出了现有技术的在PMOS器件中形成∑形SiGe的方法。在Si衬底之上形成栅极以及位于栅极两侧侧壁上的侧壁间隔件(参见图1A)之后,通过干法刻蚀,在相邻栅极之间的Si衬底中形成凹槽,如图1B所示。图1B中所示的凹槽基本上是截面由A、B、C和D四个顶点限定的平底矩形形状。
接着,如图1C所示,对形成的矩形凹槽进行晶向选择性的湿法刻蚀,从而将该矩形凹槽扩展为∑形状。通常,晶向选择性的湿法刻蚀沿(100)晶面刻蚀得比沿(111)晶面快。实际上,这里晶向选择性的湿法刻蚀沿(111)晶面基本上刻蚀不动。结果是,如图1C所示,在图1B中的干法刻蚀之后形成的凹槽的C和D两个顶点作为(111)晶向的刻蚀停止点而保留。最后,如图1D所示,在所形成的∑形凹槽中外延生长SiGe,从而形成SiGe的源区和漏区。
本发明的发明人在对形成∑形SiGe的方法进行深入研究后发现上述现有技术的方法存在难以外延生长SiGe的问题。
具体而言,在图1B所示的对衬底进行干法刻蚀的工艺中,由于等离子体的连续轰击使得所形成的矩形凹槽边缘处,尤其是图1B中示出的C和D顶点处,出现Si晶格失配等缺陷。如前所述,作为晶向选择性的湿法刻蚀的结果,C和D两点成为(111)晶向的刻蚀停止点而保留不会被刻蚀掉。后续的SiGe外延生长工艺中,籽层对于Si的表面状况(例如,清洁度、Si晶格情况)非常敏感。诸如Si晶格适配等缺陷会导致籽层难以生长。因此,如图1E所示,C和D处出现的Si晶格缺陷会使得在后续工艺中难以外延生长SiGe籽层。
发明内容
为了消除或者至少部分地减轻现有技术中的上述问题,提出了本发明。
本公开的实施例通过在干法刻蚀之后进行氧化处理以针对被干法刻蚀损伤的衬底部分形成氧化物层、然后去除该氧化物层,使得在进行SiGe外延生长之前已经去除了有晶格缺陷的衬底部分。
本公开的实施例提供了一种制造半导体器件的方法,包括以下步骤:一种制造半导体器件的方法,包括以下步骤:在衬底上形成栅极,栅极上形成有顶部掩模层;形成位于所述栅极两侧侧壁上的侧壁间隔件;以所述顶部掩模层为掩模,对所述衬底进行干法刻蚀,以在相邻的侧壁间隔件之间的衬底中形成凹槽;对所述凹槽进行氧化,以围绕所述凹槽的内壁形成衬里氧化物层;通过各向同性湿法刻蚀,去除所述衬里氧化物层;对所述凹槽进行晶向选择性的湿法刻蚀,以将所述凹槽的内壁形成为具有∑形状。
在一个实施例中,所述衬里氧化物层被形成为使得其厚度足以包括在对所述衬底进行干法刻蚀时受损伤的衬底部分。
在一个实施例中,对所述凹槽的氧化包括热氧化或者等离子体氧化工艺。
在一个实施例中,所述热氧化工艺包括在700℃至1200℃的温度下对所述衬底进行氧化。
在一个实施例中,所述热氧化工艺包括在700℃至1200℃的温度下对所述衬底进行干法氧化。
在一个实施例中,所述等离子体氧化工艺包括在射频等离子体环境中对所述衬底进行氧化。
在一个实施例中,所述衬里氧化物层的厚度约为50埃至150埃。
在一个实施例中,所述湿法去除所述衬里氧化物层的步骤包括:采用HF酸溶液来去除所述衬里氧化物层。
在一个实施例中,所述对所述凹槽进行晶向选择性的湿法刻蚀的步骤包括:采用四甲基氢氧化铵(TMAH)对所述凹槽进行湿法刻蚀。
在一个实施例中,所述晶向选择性的湿法刻蚀沿(100)晶面比沿(111)晶面的刻蚀速率快。
在一个实施例中,所述晶向选择性的湿法刻蚀沿(111)晶面基本上刻蚀不动。
在一个实施例中,在所述衬底上形成的栅极为多晶硅栅。
在一个实施例中,所述方法还包括在对衬底进行干法刻蚀之前在所述衬底中进行离子注入以形成源区和漏区。
在一个实施例中,所述方法还包括在对所述凹槽进行晶向选择性的湿法刻蚀之后在所述衬底中进行离子注入以形成源区和漏区。
在一个实施例中,在对所述凹槽进行晶向选择性的湿法刻蚀之前,所述凹槽的深度约为300埃至500埃。
本公开实施例的方法利用氧化处理和湿法刻蚀处理去除了被干法刻蚀损伤的有晶格缺陷的衬底部分,从而能够获得良好的外延生长性能。
附图说明
在阅读了以下具体描述并参考附图的情况下,本发明的其它方面将变得显而易见。各附图中相同的附图标记将指代相同的部件或步骤。附图中:
图1A至1D示出了现有技术的在PMOS器件中形成∑形SiGe的方法。其中,图1A示出了在衬底上形成的栅极和位于栅极两侧侧壁上的侧壁间隔件;图1B示出了通过干法刻蚀在相邻栅极之间的衬底中形成的大体矩形的凹槽;图1C示出了对形成的矩形凹槽进行晶向选择性的湿法刻蚀,从而将该矩形凹槽扩展为∑形状;图1D示出在所形成的∑形凹槽中外延生长SiGe,从而形成SiGe的源区和漏区。
图1E示出了图1A至1D中描述的现有技术方法的缺陷。
图2是示意性地示出了根据本公开实施例的在PMOS器件中形成∑形SiGe的方法的流程图。
图3A至3E是示意性地示出在图2中的形成∑形SiGe的方法中的各步骤的截面图。其中,图3A示出了在衬底上形成的栅极、覆盖在栅极上的顶部掩模层以及位于栅极两侧侧壁上的侧壁间隔件;图3B示出了以顶部掩模层为掩模通过干法刻蚀在相邻的侧壁间隔件之间的衬底中形成的大体矩形的凹槽;图3C示出了对凹槽进行氧化,以围绕凹槽的内壁形成衬里氧化物层;图3D示出了通过各向同性湿法刻蚀去除衬里氧化物层;以及图3E示出了对大体矩形凹槽进行晶向选择性的湿法刻蚀,从而将该凹槽扩展为∑形状。
具体实施方式
下面参照附图详细描述本发明的示例性实施例。应注意,以下的描述在本质上仅是解释性的。除非另外特别说明,否则,在实施例中阐述的部件和步骤并不限制本发明的范围。另外,对本领域技术人员已知的技术、方法和装置可能没有进行详细讨论,但在适当的情况下意在成为说明书的一部分。
在本公开的实施例中,通过在干法刻蚀之后进行氧化处理以针对被干法刻蚀损伤的衬底部分形成氧化物层、然后去除该氧化物层,使得在进行SiGe外延生长之前已经去除了有晶格缺陷的衬底部分,由此实现良好的外延生长性能。
图2示意性地示出了根据本公开实施例的在PMOS器件中形成∑形SiGe的方法的流程图。图3A至3E是示意性地示出在图2中的形成∑形SiGe的方法中的各步骤的截面图。下面将参照图2和图3A至3E来详细描述本公开的实施例。
首先,在图2的步骤S210中,提供衬底并在衬底300上形成栅极301,在栅极301顶部形成有顶部掩模层302,并且在栅极两侧侧壁上形成有侧壁间隔件303(参见图3A)。衬底例如可以由硅制成。这里的栅极例如可以是多晶硅栅。顶部掩模层302和侧壁间隔件303用于在随后的干法刻蚀、湿法刻蚀、氧化处理以及源区/漏区离子注入工艺中保护栅极301。顶部掩模层302例如可以是硅氮化物。侧壁间隔件303例如可以是硅氮化物或者硅氧化物。栅极301,顶部掩模层302以及侧壁间隔件303的形成可以利用本领域技术人员公知的工艺实现,在此不再赘述。
接下来,在图2的步骤S220中,以顶部掩模层302为掩模,通过干法刻蚀处理在相邻的侧壁间隔件303之间的衬底300中形成截面由A’、B’、C’和D’四个顶点限定的大体矩形形状的凹槽305,如图3B所示。这里的干法刻蚀例如可以采用HBr或者Cl2作为主要反应气体。
在图2的步骤S230中,对凹槽305进行氧化处理,使得在凹槽305的内壁形成衬里氧化物层306,如图3C所示。在硅衬底的情况下,经氧化处理形成的衬里氧化物层306是硅氧化物,例如二氧化硅。
在一些实施例中,可以通过包括湿法氧化和干法氧化在内的热氧化工艺来形成衬底氧化物层306。在一个示例中,在700℃至1200℃的温度下对凹槽305进行热氧化处理。在期望获得较薄的衬底氧化物层306的情况下,优选地采用干法氧化处理。
在另一些实施例中,还可以通过等离子体氧化工艺来形成衬底氧化物层306。例如,可以在射频等离子体环境中对凹槽305提供氧气。在一个示例中,在压力为10mT至1000mT、氧气流量为10至5000sccm、温度为140℃至600℃的工艺条件下,形成衬底氧化物层306。
在上述步骤S230的氧化处理中,通过调整氧气流量及反应温度,可以控制衬里氧化物层306的形成,使得其厚度足以修复在对衬底300进行干法刻蚀时受损伤的衬底部分。在一个示例中,衬里氧化物层306的厚度约为50埃至150埃。
接下来,在图2的步骤S240中,利用各向同性湿法刻蚀,去除衬里氧化物层306,如图3D所示。在一个实施例中,在衬里氧化物层306为二氧化硅的情况下,可以采用HF酸溶液来将其去除。例如,可以采用H2O与HF的质量比例为100∶1或者50∶1的溶液,在23±0.5℃的温度下,进行上述湿法刻蚀处理。在一个示例中,当去除了衬里氧化物层306之后,凹槽305的深度H例如可以是大约300埃至大约500埃。
如前所述,由于在步骤S220的干法刻蚀处理中等离子体的连续轰击,使得凹槽305的边缘,尤其是顶点C’和D’,通常会受到损伤,例如出现晶格失配等缺陷。在本实施例中,通过在步骤S230中利用氧化处理使可能受损伤的衬底部分形成氧化物层,然后在步骤S240中利用各向同性的湿法刻蚀处理去除所形成的氧化物层,从而去除了可能受损伤的凹槽305的边缘(包括顶点C’和D’),暴露出没有缺陷或者缺陷较少的表面,由此克服了现有技术中由于衬底中的缺陷部分导致难以外延生长SiGe籽层的问题。
最后,在图2的步骤S250中,对凹槽305进行晶向选择性的湿法刻蚀,以将凹槽305的内壁形成为具有∑形状,如图3E所示。在一个实施例中,可以采用沿(100)晶面比沿(111)晶面刻蚀速率快的晶向选择性的湿法刻蚀处理。例如,可以采用质量浓度为10%至25%的四甲基氢氧化铵(TMAH)在温度70℃至90℃下进行刻蚀。在这种情况下,沿(111)晶面基本上刻蚀不动。
需要注意的是,可以在对衬底进行干法刻蚀(即,图2中的步骤S220)之前或者在对凹槽进行晶向选择性的湿法刻蚀(即,图2中的步骤S250)之后,在衬底中进行离子注入以形成源区和漏区。
本公开实施例的方法利用氧化处理和湿法刻蚀处理去除了被干法刻蚀损伤的有晶格缺陷的衬底部分,从而能够获得良好的外延生长性能。
需要注意的是,eSiGe结构作为源区和漏区一般只是用于PMOS晶体管。因此,对于同时包括PMOS晶体管和NMOS晶体管的半导体器件,在为PMOS晶体管形成∑形状的过程中,需要用掩模等覆盖住NMOS晶体管部分。
尽管已经参考特定实施例对本发明进行了描述,但是应当理解,实施例是例示性的,而且本发明的范围不受限于此。对所述实施例的任何变化、修改、添加和改进都是可能的。这些变化、修改、添加和改进落入如以下权利要求中详述的本发明的范围内。
Claims (12)
1.一种制造半导体器件的方法,包括以下步骤:
在衬底上形成栅极,栅极上形成有顶部掩模层;
形成位于所述栅极两侧侧壁上的侧壁间隔件;
以所述顶部掩模层为掩模,对所述衬底进行干法刻蚀,以在相邻的侧壁间隔件之间的衬底中形成凹槽;
对所述凹槽进行氧化,以围绕所述凹槽的内壁形成衬里氧化物层;
通过各向同性湿法刻蚀去除所述衬里氧化物层;
对所述凹槽进行晶向选择性的湿法刻蚀,以将所述凹槽的内壁形成为具有∑形状;以及
在进行晶向选择性的湿法刻蚀将凹槽形成为∑形状之后,在该∑形状的凹槽内外延生长SiGe;
其中对所述凹槽的氧化包括等离子体氧化工艺;
其中,所述等离子体氧化工艺包括在压力为10mT至1000mT、氧气流量为10至5000sccm、温度为140℃至600℃的工艺条件下在射频等离子体环境中对所述衬底进行氧化。
2.如权利要求1所述的方法,其中,所述衬里氧化物层被形成为使得其厚度足以包括在对所述衬底进行干法刻蚀时受损伤的衬底部分。
3.如权利要求1或2所述的方法,其中,所述衬里氧化物层的厚度为50埃至150埃。
4.如权利要求1所述的方法,其中,所述湿法去除所述衬里氧化物层的步骤包括:采用HF酸溶液来去除所述衬里氧化物层。
5.如权利要求1所述的方法,其中,所述对所述凹槽进行晶向选择性的湿法刻蚀的步骤包括:采用四甲基氢氧化铵(TMAH)对所述凹槽进行湿法刻蚀。
6.如权利要求1或5所述的方法,其中,所述晶向选择性的湿法刻蚀沿(100)晶面比沿(111)晶面的刻蚀速率快。
7.如权利要求6所述的方法,其中,所述晶向选择性的湿法刻蚀沿(111)晶面刻蚀不动。
8.如权利要求1所述的方法,其中,在所述衬底上形成的栅极为多晶硅栅。
9.如权利要求1所述的方法,还包括在对所述衬底进行干法刻蚀之前在所述衬底中进行离子注入以形成源区和漏区。
10.如权利要求1所述的方法,还包括在∑形状的凹槽内外延生长SiGe之后在所述衬底中进行离子注入以形成源区和漏区。
11.如权利要求1所述的方法,其中,在对所述凹槽进行晶向选择性的湿法刻蚀之前,所述凹槽的深度为300埃至500埃。
12.如权利要求1所述的方法,还包括在对所述衬底进行干法刻蚀以形成凹槽之前,在要形成NMOS器件的区域上方形成掩模,而暴露要形成PMOS器件的区域。
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