KR100746543B1 - 반도체 집적 회로 장치의 제조 방법 - Google Patents
반도체 집적 회로 장치의 제조 방법 Download PDFInfo
- Publication number
- KR100746543B1 KR100746543B1 KR1020000046084A KR20000046084A KR100746543B1 KR 100746543 B1 KR100746543 B1 KR 100746543B1 KR 1020000046084 A KR1020000046084 A KR 1020000046084A KR 20000046084 A KR20000046084 A KR 20000046084A KR 100746543 B1 KR100746543 B1 KR 100746543B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- insulating film
- groove
- silicon oxide
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/694—Inorganic materials composed of nitrides
- H10P14/6943—Inorganic materials composed of nitrides containing silicon
- H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6328—Deposition from the gas or vapour phase
- H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
- H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P52/40—Chemomechanical polishing [CMP]
- H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P70/00—Cleaning of wafers, substrates or parts of devices
- H10P70/20—Cleaning during device manufacture
- H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
- H10P70/234—Cleaning during device manufacture during, before or after processing of insulating materials the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P70/00—Cleaning of wafers, substrates or parts of devices
- H10P70/20—Cleaning during device manufacture
- H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
- H10P70/277—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a planarisation of conductive layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0431—Apparatus for thermal treatment
- H10P72/0436—Apparatus for thermal treatment mainly by radiation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
- H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
- H10P72/7626—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the construction of the shaft
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
- H10W20/059—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by reflowing or applying pressure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
- H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/425—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
- H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
- H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
- H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1999-226876 | 1999-08-10 | ||
| JP22687699A JP4554011B2 (ja) | 1999-08-10 | 1999-08-10 | 半導体集積回路装置の製造方法 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020070005834A Division KR100746895B1 (ko) | 1999-08-10 | 2007-01-18 | 반도체 집적 회로 장치의 제조 방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010030070A KR20010030070A (ko) | 2001-04-16 |
| KR100746543B1 true KR100746543B1 (ko) | 2007-08-06 |
Family
ID=16851969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000046084A Expired - Lifetime KR100746543B1 (ko) | 1999-08-10 | 2000-08-09 | 반도체 집적 회로 장치의 제조 방법 |
Country Status (4)
| Country | Link |
|---|---|
| US (11) | US20020119651A1 (https=) |
| JP (1) | JP4554011B2 (https=) |
| KR (1) | KR100746543B1 (https=) |
| TW (1) | TW521373B (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8334204B2 (en) | 2008-07-24 | 2012-12-18 | Tokyo Electron Limited | Semiconductor device and manufacturing method therefor |
Families Citing this family (103)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3645129B2 (ja) * | 1999-06-25 | 2005-05-11 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP4554011B2 (ja) * | 1999-08-10 | 2010-09-29 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
| JP3805588B2 (ja) * | 1999-12-27 | 2006-08-02 | 株式会社日立製作所 | 半導体装置の製造方法 |
| JP2001223269A (ja) * | 2000-02-10 | 2001-08-17 | Nec Corp | 半導体装置およびその製造方法 |
| US6989600B2 (en) * | 2000-04-20 | 2006-01-24 | Renesas Technology Corporation | Integrated circuit device having reduced substrate size and a method for manufacturing the same |
| JP2002110679A (ja) * | 2000-09-29 | 2002-04-12 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| US7271489B2 (en) * | 2003-10-15 | 2007-09-18 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
| TW462085B (en) * | 2000-10-26 | 2001-11-01 | United Microelectronics Corp | Planarization of organic silicon low dielectric constant material by chemical mechanical polishing |
| EP1298715B1 (en) * | 2001-03-16 | 2013-08-07 | Shin-Etsu Handotai Co., Ltd. | Method for storing a silicon wafer |
| US6787462B2 (en) | 2001-03-28 | 2004-09-07 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device having buried metal wiring |
| KR100750922B1 (ko) * | 2001-04-13 | 2007-08-22 | 삼성전자주식회사 | 배선 및 그 제조 방법과 그 배선을 포함하는 박막트랜지스터 기판 및 그 제조 방법 |
| JP4803625B2 (ja) * | 2001-09-04 | 2011-10-26 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US6949411B1 (en) * | 2001-12-27 | 2005-09-27 | Lam Research Corporation | Method for post-etch and strip residue removal on coral films |
| US20030134499A1 (en) | 2002-01-15 | 2003-07-17 | International Business Machines Corporation | Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof |
| JP3734447B2 (ja) * | 2002-01-18 | 2006-01-11 | 富士通株式会社 | 半導体装置の製造方法および半導体装置の製造装置 |
| US6518184B1 (en) * | 2002-01-18 | 2003-02-11 | Intel Corporation | Enhancement of an interconnect |
| US6764952B1 (en) * | 2002-03-13 | 2004-07-20 | Novellus Systems, Inc. | Systems and methods to retard copper diffusion and improve film adhesion for a dielectric barrier on copper |
| WO2003079429A1 (fr) * | 2002-03-15 | 2003-09-25 | Renesas Technology Corp. | Procede de production d'un dispositif a circuit imprime a semi-conducteur |
| JP3989763B2 (ja) * | 2002-04-15 | 2007-10-10 | 株式会社半導体エネルギー研究所 | 半導体表示装置 |
| JP2003318151A (ja) | 2002-04-19 | 2003-11-07 | Nec Electronics Corp | 半導体装置の製造方法 |
| TWI288443B (en) | 2002-05-17 | 2007-10-11 | Semiconductor Energy Lab | SiN film, semiconductor device, and the manufacturing method thereof |
| US6909196B2 (en) * | 2002-06-21 | 2005-06-21 | Micron Technology, Inc. | Method and structures for reduced parasitic capacitance in integrated circuit metallizations |
| JP4087172B2 (ja) * | 2002-07-11 | 2008-05-21 | セイコーインスツル株式会社 | 半導体装置の製造方法 |
| US7582260B2 (en) * | 2002-07-18 | 2009-09-01 | Montana State University | Zwitterionic dyes for labeling in proteomic and other biological analyses |
| JP3974470B2 (ja) * | 2002-07-22 | 2007-09-12 | 株式会社東芝 | 半導体装置 |
| CN100352036C (zh) | 2002-10-17 | 2007-11-28 | 株式会社瑞萨科技 | 半导体器件及其制造方法 |
| JP2004172576A (ja) * | 2002-10-30 | 2004-06-17 | Sony Corp | エッチング液、エッチング方法および半導体装置の製造方法 |
| US6790777B2 (en) | 2002-11-06 | 2004-09-14 | Texas Instruments Incorporated | Method for reducing contamination, copper reduction, and depositing a dielectric layer on a semiconductor device |
| DE10257682A1 (de) * | 2002-12-10 | 2004-07-08 | Infineon Technologies Ag | Halbleiterschaltungsanordnung |
| JP2004304021A (ja) * | 2003-03-31 | 2004-10-28 | Ebara Corp | 半導体装置の製造方法及び製造装置 |
| JP2004273523A (ja) * | 2003-03-05 | 2004-09-30 | Renesas Technology Corp | 配線接続構造 |
| JP2004288696A (ja) * | 2003-03-19 | 2004-10-14 | Fujitsu Ltd | 半導体装置の製造方法 |
| JP4454242B2 (ja) | 2003-03-25 | 2010-04-21 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
| JP2004356178A (ja) * | 2003-05-27 | 2004-12-16 | Oki Electric Ind Co Ltd | エッチング方法、及び半導体装置の製造方法 |
| US20040266185A1 (en) * | 2003-06-30 | 2004-12-30 | Texas Instruments Incorporated | Method for reducing integrated circuit defects |
| US20050048768A1 (en) * | 2003-08-26 | 2005-03-03 | Hiroaki Inoue | Apparatus and method for forming interconnects |
| EP1691403A4 (en) * | 2003-12-04 | 2009-04-15 | Tokyo Electron Ltd | METHOD FOR CLEANING THE CONDUCTIVE COATING SURFACE OF A SEMICONDUCTOR SUBSTRATE |
| JP2005183814A (ja) | 2003-12-22 | 2005-07-07 | Fujitsu Ltd | 半導体装置の製造方法 |
| JP4065855B2 (ja) * | 2004-01-21 | 2008-03-26 | 株式会社日立製作所 | 生体および化学試料検査装置 |
| KR20060043082A (ko) * | 2004-02-24 | 2006-05-15 | 마츠시타 덴끼 산교 가부시키가이샤 | 반도체장치의 제조방법 |
| SG157226A1 (en) * | 2004-02-24 | 2009-12-29 | Taiwan Semiconductor Mfg | A method for improving time dependent dielectric breakdown lifetimes |
| KR100519801B1 (ko) * | 2004-04-26 | 2005-10-10 | 삼성전자주식회사 | 스트레스 완충 스페이서에 의해 둘러싸여진 노드 콘택플러그를 갖는 반도체소자들 및 그 제조방법들 |
| US7829152B2 (en) * | 2006-10-05 | 2010-11-09 | Lam Research Corporation | Electroless plating method and apparatus |
| JP4854938B2 (ja) * | 2004-07-06 | 2012-01-18 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US7138717B2 (en) | 2004-12-01 | 2006-11-21 | International Business Machines Corporation | HDP-based ILD capping layer |
| JP2006179599A (ja) * | 2004-12-21 | 2006-07-06 | Toshiba Corp | 半導体装置およびその製造方法 |
| US7442114B2 (en) * | 2004-12-23 | 2008-10-28 | Lam Research Corporation | Methods for silicon electrode assembly etch rate and etch uniformity recovery |
| KR100640525B1 (ko) * | 2004-12-29 | 2006-10-31 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 라인 형성 방법 |
| KR100628225B1 (ko) * | 2004-12-29 | 2006-09-26 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조방법 |
| JP4516447B2 (ja) * | 2005-02-24 | 2010-08-04 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US7368383B2 (en) * | 2005-05-24 | 2008-05-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hillock reduction in copper films |
| US7414275B2 (en) * | 2005-06-24 | 2008-08-19 | International Business Machines Corporation | Multi-level interconnections for an integrated circuit chip |
| DE102005035740A1 (de) * | 2005-07-29 | 2007-02-08 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer isolierenden Barrierenschicht für eine Kupfermetallisierungsschicht |
| JP4548280B2 (ja) * | 2005-08-31 | 2010-09-22 | ソニー株式会社 | 半導体装置の製造方法 |
| US8039049B2 (en) * | 2005-09-30 | 2011-10-18 | Tokyo Electron Limited | Treatment of low dielectric constant films using a batch processing system |
| US20070080455A1 (en) * | 2005-10-11 | 2007-04-12 | International Business Machines Corporation | Semiconductors and methods of making |
| DE102005057057B4 (de) * | 2005-11-30 | 2017-01-05 | Advanced Micro Devices, Inc. | Verfahren zur Herstellung einer isolierenden Deckschicht für eine Kupfermetallisierungsschicht unter Anwendung einer Silanreaktion |
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| US20020142576A1 (en) | 2002-10-03 |
| US20020113271A1 (en) | 2002-08-22 |
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| US20030001277A1 (en) | 2003-01-02 |
| US20080138979A1 (en) | 2008-06-12 |
| US6849535B2 (en) | 2005-02-01 |
| US20030001183A1 (en) | 2003-01-02 |
| KR20010030070A (ko) | 2001-04-16 |
| TW521373B (en) | 2003-02-21 |
| US6815330B2 (en) | 2004-11-09 |
| US20030045086A1 (en) | 2003-03-06 |
| US6797606B2 (en) | 2004-09-28 |
| US20020127842A1 (en) | 2002-09-12 |
| US6864169B2 (en) | 2005-03-08 |
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