WO2003079429A1 - Procede de production d'un dispositif a circuit imprime a semi-conducteur - Google Patents

Procede de production d'un dispositif a circuit imprime a semi-conducteur Download PDF

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Publication number
WO2003079429A1
WO2003079429A1 PCT/JP2003/001233 JP0301233W WO03079429A1 WO 2003079429 A1 WO2003079429 A1 WO 2003079429A1 JP 0301233 W JP0301233 W JP 0301233W WO 03079429 A1 WO03079429 A1 WO 03079429A1
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WIPO (PCT)
Prior art keywords
insulating film
integrated circuit
semiconductor substrate
wiring
circuit device
Prior art date
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PCT/JP2003/001233
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English (en)
Japanese (ja)
Inventor
Junji Noguchi
Original Assignee
Renesas Technology Corp.
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Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to JP2003577326A priority Critical patent/JPWO2003079429A1/ja
Publication of WO2003079429A1 publication Critical patent/WO2003079429A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor integrated circuit device manufacturing technique, and more particularly to chemical mechanical polishing.
  • the embedded wiring structure on the semiconductor substrate is formed by embedding the wiring metal film in the wiring embedding opening such as the wiring groove and hole formed in the insulating film, and then chemically polishing the unnecessary metal film outside the opening. It is formed by damascene wiring technology called Single-Damascene or Dual-Damascene, which is removed by a method.
  • the Cu wiring is in direct contact with the insulating film because it is more easily diffused into the insulating film than other metal films for wiring such as aluminum (AI).
  • the Cu wiring is in direct contact with the insulating film because it is more easily diffused into the insulating film than other metal films for wiring such as aluminum (AI).
  • a thin barrier metal film By covering the bottom and sides of the Cu wiring with a thin barrier metal film and covering the surface of the Cu wiring with a cap insulating film, Cu atoms in the Cu wiring can be prevented from diffusing into the surrounding insulating film. I'm preventing.
  • Japanese Patent Application Laid-Open No. 111-1843 discloses a structure in which the upper surface of a Cu wiring is formed lower than the upper surface of an insulating film, and a barrier insulating film is embedded therein.
  • Japanese Patent Application Laid-Open No. 10-50632 discloses a structure in which the upper surfaces of a Cu wiring and a barrier metal film are formed lower than the upper surface of an insulating film, and a barrier insulating film is embedded therein. Disclosure of the invention
  • the LSI under development by the present inventors forms Cu wiring by the following process.
  • an opening is formed in an insulating film deposited on a semiconductor substrate (wafer), and then a thin barrier metal film such as a titanium nitride film is deposited on the insulating film including the inside of the opening.
  • a Cu film having a thickness greater than the depth of the opening is deposited on the top of the substrate.
  • Cu wiring is formed inside the opening by removing unnecessary Cu film and barrier metal film outside the opening by chemical mechanical polishing.
  • the semiconductor substrate on which the Cu wiring is formed is transported to a cleaning processing unit, and cleaning for removing foreign substances such as slurry adhered to the surface of the semiconductor substrate in the polishing process (hereinafter referred to as post-cleaning). I do.
  • the post-cleaning process includes a cleaning process followed by an acid cleaning process.
  • the purpose of the cleaning process is to neutralize the acidic slurry containing an oxidizing agent attached to the surface of the semiconductor substrate, and to clean the surface of the semiconductor substrate while supplying a weak chemical solution.
  • the acid cleaning treatment is for the purpose of removing residual metal, reducing dangling ponds on the surface of the insulating film, and removing irregularities on the surface of the insulating film, etc., while supplying a chemical containing acid to the surface of the semiconductor substrate. Wash.
  • the acid contained in the above chemical solution is a strong acid such as dilute hydrofluoric acid (DHF)
  • DHF dilute hydrofluoric acid
  • a thin oxide layer (CuO) on the surface of the Cu wiring generated by the chemical mechanical polishing process is removed.
  • the cross-sectional area of the Cu wiring may be reduced, and the electric resistance may be increased. Therefore, it is desirable to use a chemical solution containing a weak acid such as an organic acid, particularly when the line width of the Cu wiring is fine.
  • a chemical solution containing an organic acid particularly when the line width of the Cu wiring is fine.
  • the cleaning is performed using a chemical solution containing an organic acid, the oxide layer (CuO) on the surface of the Cu wiring is not removed. Therefore, after the cleaning, a reduction treatment such as hydrogen anneal is performed and the oxide layer (CuO) is removed. ) Must be removed.
  • a cap insulating film made of a silicon nitride film or the like is deposited on the surface of the semiconductor substrate on which the post-cleaning process has been completed by using a plasma CVD method or the like.
  • the present inventor considers a case where the semiconductor substrate (wafer) is left in a clean room between the completion of the post-cleaning process and the deposition of the cap insulating film.
  • the TDDB life is a measure for objectively measuring the time dependency of dielectric breakdown.
  • a relatively high voltage is applied between Cu wirings under a measurement condition of a predetermined temperature (for example, 140 ° C). Create a graph in which the time from application to dielectric breakdown is plotted against the applied electric field, and extrapolate the actual electric field strength (for example, 0.2 MVZcm) from this graph to the time (life).
  • An object of the present invention is to provide a technique capable of suppressing a decrease in T DDB life of C U wiring.
  • the method of manufacturing a semiconductor integrated circuit device includes: (a) depositing a first insulating film on a semiconductor substrate and then forming an opening for wiring embedding in the first insulating film; b) depositing a conductive film containing Cu as a main component on the first insulating film including the inside of the opening; and (c) chemically and mechanically polishing the conductive film to leave the inside of the opening. Forming a Cu wiring in the opening; (d) cleaning the surface of the semiconductor substrate after the (c); and (e) cleaning the semiconductor after the (d).
  • FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. It is principal part sectional drawing of a conductor board.
  • FIG. 2 is a cross-sectional view of a main part of a semiconductor substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
  • FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.
  • FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
  • FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
  • FIG. 8 is a graph showing the relationship between the number of days the substrate has been left until the cap insulating film is deposited after the post-cleaning process after chemical mechanical polishing and the breakdown electric field strength.
  • FIG. 9 is a graph showing the standing time dependence of the TDD B life of the sample used for the measurement of FIG.
  • Figure 10 is a graph of the relationship between the number of days the substrate has been left until the cap insulating film is deposited and the breakdown electric field strength after performing post-cleaning treatment after chemical mechanical polishing using two types of cap insulating films. It is.
  • FIG. 11 is a schematic diagram showing a degradation model of TDD B life due to standing time considered by the present inventors.
  • FIG. 12 is an explanatory view showing an example of a method of storing a semiconductor substrate after the post-cleaning process.
  • FIG. 13 is an explanatory diagram illustrating an example of a method of storing a semiconductor substrate after the post-cleaning process.
  • FIGS. 14 (a), (b) and (c) are explanatory views showing an example of a substrate management method from the post-cleaning process to the deposition of the cap insulating film.
  • Figure 15 shows an example of the substrate management method from the post-cleaning process to the deposition of the cap insulating film.
  • FIG. 16 is an explanatory diagram illustrating an example of a substrate management method from the post-cleaning process to the deposition of the cap insulating film.
  • FIG. 17 is a graph showing the TDB life of Cu wiring manufactured by introducing the method of managing a semiconductor substrate according to one embodiment of the present invention.
  • the present embodiment is applied to a method of manufacturing an LSI in which a Cu line is formed on a complementary metal insulator semiconductor field effect transistor (MIS) formed on a semiconductor substrate.
  • MIS complementary metal insulator semiconductor field effect transistor
  • a wafer-like semiconductor substrate (hereinafter, referred to as a * plate, sometimes also referred to as a wafer) 1 made of single-crystal silicon is prepared.
  • a wafer-like semiconductor substrate (hereinafter, referred to as a * plate, sometimes also referred to as a wafer) 1 made of single-crystal silicon is prepared.
  • an n-channel MISFETQn is formed in the p-type well 4
  • a p-channel MISFETQp is formed in the n-type well 5.
  • the substrate 1 in the element isolation region is etched to form a groove, and then a silicon oxide film 3 is deposited on the substrate 1 including the inside of the groove by a CVD method.
  • the silicon oxide film 3 outside is removed by a chemical mechanical polishing method.
  • boron ions are implanted into a part of the substrate 1 and phosphorus ions are implanted into the other part, and then the substrate 1 is heat-treated. These impurities are diffused into the substrate 1.
  • the n-channel type MISFETQn and the p-channel type MISFETQp may be formed by using any of the well-known processes. For example, they are formed as follows. First, a gate insulating film 6 made of a silicon oxide film is formed on each surface of the p-type well 4 and the n-type well 5 by steam oxidation of the substrate 1. A polycrystalline silicon film is deposited on the upper insulating film 6 by a CVD method, and then phosphorus is ion-implanted into the upper polycrystalline silicon film on the p-type well 4 to form a polycrystalline silicon film on the upper n-type well 5. After ion implantation of boron, the polycrystalline silicon film is buttered by drying using a photoresist film as a mask (the gate electrode 7 is formed).
  • an n-type semiconductor region 8 having a low impurity concentration is formed by ion-implanting phosphorus or arsenic into the p-type well 4, and a low impurity concentration is formed by ion-implanting boron into the n-type well 5.
  • a silicon nitride film is deposited on the substrate 1 by a CVD method, and then the silicon nitride film is anisotropically etched to form a sidewall on the side wall of the gate electrode 7.
  • a pulse 10 is formed.
  • an n + type semiconductor region 11 having a high impurity concentration is formed by ion-implanting phosphorus or arsenic into the p-type well 4 and ion-implanting boron into the n-type well 5.
  • a P + type semiconductor region 12 having a high impurity concentration is formed.
  • a silicide layer is formed on each of the gate electrode 7, the n + type semiconductor region 11 (source, drain) and the p + type semiconductor region 12 (source, drain).
  • Form 1 3 To form the silicide layer 13, a large amount of Co (cobalt) is deposited on the substrate 1 by a sputtering method, and then heat treatment is performed in a nitrogen gas atmosphere to form the substrate 1 and the gate electrode 7 with the Co film. After the reaction, the unreacted Co film is removed by wet etching. With the steps so far, the n-channel type MISFETQ n and the p-channel type MISFETQ p are completed.
  • a first-layer W (tungsten) wiring 20 is formed on the n-channel type MISFET Qn and the p-channel type MISFETQp.
  • a silicon nitride film 15 and a silicon oxide film 16 are deposited on the substrate 1 by a CVD method, and then the n + -type semiconductor regions 11 (source and drain) and After the silicon oxide film 16 and the silicon nitride film 15 on each of the p + type semiconductor regions 12 (source and drain) are dry-etched to form contact holes 17, the contact holes 17 are formed.
  • Form metal plug 18 is
  • the silicon oxide film 16 may be a silicon oxide film formed by a normal CVD method using monosilane (SiH 4 ) as a source gas, a BPSG (Boron-doped Phospho Silicate Glass) film, or It may be composed of an SOG (Spin On Glass) film formed by a spin coating method.
  • a TiN (titanium nitride) film and a W film are deposited by CVD on the silicon oxide film 16 including the inside of the contact hole 17, and then a silicon oxide film Unnecessary TiN film and W film on top of 16 are removed by chemical mechanical polishing.
  • a W film is deposited on the silicon oxide film 16 by a sputtering method, and the W film is patterned by dry etching using a photoresist film as a mask, thereby forming a first layer on the silicon oxide film 16.
  • the W wiring 20 of the eye is formed.
  • the first layer W wiring 20 is connected to the source and drain (n + type semiconductor region 11) or p channel of the n-channel type MIS FETQn through the metal plug 18 embedded in the contact hole 17. It is electrically connected to the source and drain of the type MISF ETQ p (p + type semiconductor region 12).
  • two insulating films 21 and 22 are deposited on the W wiring 20 by a CVD method or a coating method, and then the insulating films 21 and 22 are formed by dry etching using a photoresist film as a mask. after forming the through hole 23 to 22, to form the metal plug 24 in the through-holes 2 3.
  • OMV / Vm Or polyallyl ether (PAE) based material FLARE (manu
  • the insulating film 21 is composed of the above-mentioned organic insulating material, a Si OF-based material, an HSQ (hydrogen sUsesquioxane) -based material, a MSQ (methyl silsesquioxane) -based material, a porous HSQ-based material, a porous MS Q material, and the like. You may.
  • the insulating film 22 above the insulating film 21 is formed to protect the insulating film 21 having lower mechanical strength and moisture resistance than the inorganic insulating material.
  • the insulating film 22 is made of, for example, a silicon oxide film deposited by a CVD method, a silicon carbide (SiC) film or a silicon carbonitride (SiCN) film having a lower dielectric constant than the silicon oxide film.
  • Examples of the silicon carbide film and silicon carbonitride (SSCN) film include BLOk (manufactured by AMAT).
  • a W film is deposited on the insulating film 22 by a sputtering method, and then unnecessary W on the top of the silicon oxide film 22 is formed. The film is removed by a chemical mechanical polishing method.
  • two insulating films 25 and 26 are deposited on the silicon oxide film 22 by the CVD method, and then the upper portion of the through hole 23 is etched by dry etching using a photoresist film as a mask.
  • a wiring groove 27 is formed in the films 25 and 26.
  • the upper insulating film 26 is composed of, for example, a silicon oxide film deposited using oxygen and tetraethoxysilane (TEOS) as a source gas.
  • the lower insulating film 25 is a stopper film that prevents the lower insulating film 22 made of a silicon oxide film or the like from being etched when the wiring film 27 is formed by etching the insulating film 26. It is composed of an insulating film such as a silicon film having a large etching selectivity to a silicon oxide film.
  • a silicon oxynitride (SiON) film or a silicon carbonitride (SiCN) film having a lower dielectric constant than the silicon nitride film may be used.
  • a barrier metal film 28 made of a titanium nitride film or the like is deposited on the insulating film 26 including the inside of the wiring groove 27 by a sputtering method.
  • a Cu film 30a having a thickness larger than the depth of the wiring groove 27 is deposited by a sputtering method.
  • the barrier metal film 28 is formed by diffusing the Cu film 30a deposited inside the wiring groove 27 into the surrounding insulating film 26, and the adhesion between the Cu film 30a and the insulating film 26. It is formed in order to improve the quality.
  • the rear metal film 28 can be made of a conductive film such as a tungsten nitride (WN) film, a tantalum nitride (TaN) film, or a titanium tungsten (TiW) film, in addition to a titanium nitride film.
  • the substrate 1 is subjected to a heat treatment in a non-oxidizing atmosphere (for example, a hydrogen atmosphere) after the film formation to reflow the Cu film 30a.
  • a non-oxidizing atmosphere for example, a hydrogen atmosphere
  • a high-directional sputtering method such as a long throw sputtering method and a collimated sputtering method that can satisfactorily bury the Cu film 30a in the wiring groove 27 is used.
  • the Cu film 30a can be formed by a CVD method, an electrolytic plating method, or an electroless plating method, in addition to the sputtering method.
  • a thin Cu seed layer is formed on the barrier metal film 28 by a sputtering method, and then the Cu film 3 is formed on the surface of the seed layer using a plating solution such as copper sulfate. Grow 0a.
  • the thin film 303 may be made of a Cu alloy containing Cu as a main component in addition to a single Cu.
  • the Cu film 30a and the barrier metal film 28 outside the wiring groove 27 are removed by a chemical mechanical polishing method, so that the second inside of the wiring groove 27 is formed.
  • a Cu wiring 30 serving as a wiring of the layer is formed.
  • the Cu wiring 30 is electrically connected to the first-layer W wiring 20 via a metal plug 24 embedded in the through hole 23.
  • the Cu wiring 30 is formed by a so-called single damascene method in which the Cu film 30a is buried in the wiring groove 27, but the wiring groove 27 and the through hole 2 below the Cu wiring 30 are formed.
  • the Cu wiring 30 may be formed by a so-called dual damascene method, in which a Cu film 30a is buried in the inside of 3 simultaneously.
  • the polishing of the Cu film 30a is mainly performed by using abrasive grains such as alumina and silica and an oxidizing agent such as a hydrogen peroxide solution or an aqueous ferric nitrate solution, and dispersing or dissolving them in pure water.
  • a general-purpose polishing slurry may be used, but from the viewpoint of preventing micro scratches generated on the surface of the substrate 1, a slurry containing no abrasive (abrasive free) It is preferred to use (slurry).
  • the composition of the abrasive free slurry is a mixture of pure water with an oxidizing agent, an organic acid, and a corrosion inhibitor.
  • an oxidizing agent hydrogen peroxide (H 2 0 2), hydroxide Anmoniu ⁇ , nitric Anmoniumu
  • a chloride Anmoniumu as the organic acid, Kuen acid, malonic acid, fumaric acid, malic acid, Examples thereof include adipic acid, benzoic acid, phthalic acid, tartaric acid, lactic acid, succinic acid, and oxalic acid.
  • hydrogen peroxide is a suitable oxidizing agent to be used for a slurry because it contains no metal component and is not a strong acid.
  • cunic acid is commonly used as a food additive and has low toxicity, low harm as a waste liquid, no odor, and high solubility in water. Preferred organic acids.
  • the anticorrosion agent examples include benzotriazole (BTA), BTA derivatives such as BTA carboxylic acid, dodecyl mercaptan, triazole, and tolyl triazole. Particularly, when benzotriazole is used, Cu A stable corrosion-resistant protective film can be formed on the surface of the wiring 30.
  • the addition amount of the anticorrosive may be about 0.001-1% by weight of the total amount of the slurry.
  • polyacrylic acid, polymethacrylic acid, an ammonium salt thereof, or ethylenediaminetetraacetic acid (EDTA) may be added as necessary.
  • the surface of the Cu film 30a is oxidized by an oxidizing agent to form a thin oxide layer (CuO).
  • a substance for making the oxide water-soluble is supplied, a part of the oxidized layer is eluted as an aqueous solution, and the film thickness is reduced.
  • the thinned portion of the oxide layer on the surface of the Cu film 30a is again exposed to the oxidizing substance, and the thickness of the oxide layer increases. Chemical mechanical polishing of the Cu film 30a proceeds while repeating such a series of reactions.
  • the surface of the barrier metal film 28 on the insulating film 26 is exposed.
  • a polishing slurry containing abrasive grains such as alumina and silica is used. It is better to use the one with increased number. By using such a polishing slurry, the inside of the wiring groove 27 can be The barrier metal film 28 on the insulating film 26 can be removed without excessively polishing the Cu film 30a.
  • This anti-corrosion treatment is a treatment for forming a hydrophobic protective film on the surface of the Cu wiring 30.
  • a chemical solution containing an anti-corrosion agent such as benzotriazole (BTA) described above is applied to the substrate.
  • the substrate 1 on which the anticorrosion treatment has been completed is transported to the post-cleaning processing section, and the surface of the substrate 1, that is, the surface of the Cu wiring 30 or the insulating film 26 Removes foreign matter such as slurry attached to the surface.
  • the substrate 1 that has been subjected to the anticorrosion treatment is temporarily stored in the immersion treatment unit until it is transported to the post-cleaning treatment unit in order to prevent the oxidation of the Cu wiring 30 by drying.
  • the immersion treatment section has a structure in which, for example, a predetermined number of substrates 1 are immersed and stored in an immersion tank (storage force) in which pure water overflows. Prevention of drying of the surface of the substrate 1 is not limited to the above-described method of storing in the immersion tank, as long as at least the surface of the substrate 1 can be kept in a wet state, for example, by supplying a pure water shower. . In addition, the transfer of the substrate 1 from the immersion processing section to the post-cleaning processing section is performed promptly while keeping the surface of the substrate 1 wet.
  • the post-cleaning process includes an alkali cleaning process and a subsequent acid cleaning process.
  • the alkali cleaning is performed to neutralize an acidic slurry containing an oxidizing agent adhered to the surface of the substrate 1.
  • the surface of the substrate 1 is supplied while supplying a weak chemical solution having a pH of about 8. Scrub or brush wash.
  • a weak alkaline chemical solution is an aqueous solution containing about 0.01% of aminoethanol (DAE: Diluted Amino Ethanol).
  • the acid cleaning after the alkali cleaning is for the purpose of improving TDDB characteristics, removing residual metal, reducing dangling bonds on the surface of the insulating film 26, and removing irregularities on the surface of the insulating film 26.
  • the surface of the substrate 1 while supplying a chemical containing an organic acid such as an acid, such as Electraclean (EC) (Applied Materials, Inc., pH 5.5) or Silex (CIREX, manufactured by Wako Pure Chemical). Scrub or brush clean.
  • EC Electraclean
  • Silex Silex
  • Scrub or brush clean instead of these cleaning methods, disk-type cleaning methods and pen-type cleaning methods A cleaning method may be used.
  • the surface of the substrate 1 is subjected to pure water scrub cleaning, pure water ultrasonic cleaning, pure water running water cleaning, or pure water spin cleaning, or the back surface of the substrate 1 is purified.
  • Water scrub cleaning may be used.
  • the above post-cleaning treatment can be performed by a combination of alkali cleaning using ammonium hydroxide and acid cleaning using dilute hydrofluoric acid (DHF).
  • DHF dilute hydrofluoric acid
  • the hydrofluoric acid is an acid stronger than the organic acid
  • the thin oxide layer (CuO) on the surface of the Cu wiring 30 generated by the polishing treatment is removed.
  • Hydrogen annealing can be simplified or omitted.
  • hydrofluoric acid not only the oxide layer (CuO) on the surface of the Cu wiring 30 but also the Cu wiring 30 itself is etched, so the cross-sectional area of the Cu wiring 30 is reduced. There is a possibility that the electric resistance may increase if it is small. Therefore, especially when the line width of the Cu wiring 30 is fine, acid cleaning using an aqueous solution containing an organic acid is desirable.
  • the oxide layer (CuO) on the surface of the Cu wiring 30 is not removed, and thereafter, the oxide layer (CuO) is removed by performing a hydrogen annealing treatment.
  • the oxide layer (CuO) is removed by performing a hydrogen annealing treatment.
  • the acid cleaning is performed using hydrofluoric acid, it is not desirable to completely remove the oxide layer (CuO) during the acid cleaning in order to prevent the Cu wiring 30 from being scraped. Therefore, in this case, it is preferable to stop the acid cleaning in a short time so that the oxide layer (CuO) is not completely removed, and to completely remove the remaining oxide layer (CuO) by hydrogen annealing.
  • Organic acids and dilute hydrofluoric acid are used as acid cleaning chemicals to remove foreign matter remaining on the surface of the Cu wiring 30 and the surface of the insulating film 26 while minimizing scraping of the surface of the Cu wiring 30.
  • DHF dilute hydrofluoric acid
  • the concentration of hydrofluoric acid in this chemical solution is set to about 0.1 to 1% in order to minimize scraping of the Cu wiring 30.
  • the concentration of the organic acid should be about 0.1-1%, and the pH should be in the range of 2-6 (preferably about 3).
  • Examples of the organic acid include citric acid, malic acid, oxalic acid, malonic acid, and formic acid.
  • the etching rate of Cu can be suppressed to 3 nmz or less, and the etching rate of silicon oxide forming the insulating film 26 can be 1 n or more.
  • the foreign matter on the surface of the insulating film 26 can be lifted off while minimizing the scraping.
  • the dependence of the TDDB life described later on the standing time can be made the same level (10 days) as the acid cleaning using hydrofluoric acid.
  • an aqueous solution obtained by adding ammonia to the above-mentioned mixed aqueous solution of the organic acid and the diluted hydrofluoric acid (a mixed aqueous solution of the organic acid, the diluted hydrofluoric acid and ammonium hydroxide) can also be used.
  • the concentration of each of the organic acid, hydrofluoric acid and ammonium hydroxide should be about 0.1 to 1%.
  • this mixed aqueous solution has a pH of about 6 to 8, it is an aqueous solution that is closer to neutral than an acidic aqueous solution, so that the effect of protecting the surface of the Cu wiring 30 is better than when an acidic aqueous solution is used. Is improved.
  • an anticorrosive such as benzotriazole (BTA)
  • the above-mentioned% indicating the concentration of the aqueous solution to which hydrofluoric acid, organic acid and ammonia are added means weight%.
  • the surface moisture is sufficiently removed in advance by a drying process such as a spin drier.
  • the oxide layer (CuO) on the surface of the Cu wiring 30 is reduced by heat-treating the substrate 1 in a hydrogen gas atmosphere at 200 ° C to 475 ° C for about 0.5 to 5 minutes. This is the process of removing.
  • This hydrogen annealing treatment is desirably performed as soon as possible (preferably within half a day) after the post-cleaning treatment is completed.
  • the oxide layer (CuO) grows on the surface of the Cu wiring 30 that is in contact with the air in the clean room.
  • the removal of the oxide layer (CuO) will be incomplete, and the TDDB life will be shortened.
  • a silicon nitride film is formed on the insulating film 26 by a CVD method.
  • the surface of the Cu wiring 30 is covered with the cap insulating film 3 "I by depositing a cap insulating film 31 made of the same material.
  • C C diffuses from the surface of the Cu wiring 30 to the surrounding insulating film.
  • the cap insulating film 31 is deposited using, for example, a parallel plate type plasma CVD apparatus.
  • ammonia ( ⁇ 3 ) gas is supplied into the processing chamber of the plasma CVD apparatus.
  • the surface of the substrate 1 may be subjected to an ammonia plasma treatment.
  • a hydrogen gas may be supplied into the treatment chamber, and the surface of the substrate 1 may be subjected to the hydrogen plasma treatment.
  • Figure 8 shows a post-cleaning process after chemical mechanical polishing (CMP) using the above-mentioned aminoethanol aqueous solution (DAE) and CI REX, and then depositing a cap insulating film 31 composed of a silicon nitride film.
  • CMP chemical mechanical polishing
  • DAE aminoethanol aqueous solution
  • CI REX CI REX
  • FIG. 9 is a graph showing the dependence of the TDDB life of the same sample on the standing time.
  • the TDDB life is the same from the time immediately after standing to the 4th term, but it decreases by about 3 digits between the 4th and 5th days, and about 3 digits between the 5th and 6th days. It was found that the TDD B life decreased sharply after 4 days of standing, such as a decrease of about 3 digits between the 6th and the 11th day.
  • FIG. 10 shows the result of performing similar measurements by changing the material of the cap insulating film 31 and the chemical solution for post-cleaning. From these results, (1) when the cap insulating film 31 is formed of a silicon carbonitride film, the TDDB life is less deteriorated (about one third) than when the cap insulating film 31 is formed of a silicon nitride film. ) When post-cleaning using hydrofluoric acid, there is not much change in the TDDB life.However, when post-cleaning using CI REX or EC, the TDDB will pass 10 days after standing. It was found that the life was shortened.
  • FIG. 11 shows a model of the degradation of the TDD DB life due to the standing time considered by the present inventors.
  • the time from the post-cleaning process after the chemical mechanical polishing process to the deposition of the cap insulating film 31, that is, the time during which the wiring 30 is exposed to the oxygen or moisture in the atmosphere is within 4 words. It was concluded that That is, in an LSI manufacturing line having the above-described Cu wiring forming process, the design and management of the line are performed so that the process from the post-cleaning process to the deposition process of the cap insulating film 31 is completed within four days. It is desirable to do.
  • a countermeasure for example, as shown in Fig. 12, store the wafer case 40 containing the substrate (wafer) 1 after the post-cleaning process in the storage box 41 to avoid contact with oxygen and moisture. Therefore, a method of storing the substrate (wafer) 1 while supplying a non-oxidizing gas such as nitrogen substantially free of moisture into the storage box 41 is conceivable. In this case, if the dehumidifying agent 42 is put in the storage box 41 or the dehumidifying agent 42 is put in the wafer case 40 as shown in FIG. The progress of oxidation and corrosion can be more effectively suppressed.
  • the method of storing the wafer case 40 containing the substrate (wafer) 1 in the storage box 41 as described above is effective.
  • the substrate 1 after re-cleaning is left in a clean room for a long time, the surface of the Cu wiring 30 is oxidized and corroded again, so this re-cleaning is performed immediately before the cap insulating film 31 is deposited. It is desirable to carry out. Even in the case where the substrate 1 after the re-cleaning process is unavoidably temporarily left behind, by storing it in the storage box 41 described above, reoxidation and corrosion of the surface of the Cu wiring 30 are minimized. Can be stopped.
  • the hydrogen annealing process may be performed again to reduce the surface of the Cu wiring 30 and then the cap insulating film 31 may be deposited. At that time, if it is expected that the time for leaving the substrate 1 will be long, it is effective to repeat the hydrogen annealing every predetermined time. Further, the hydrogen annealing treatment may be performed in combination with the re-cleaning treatment, the reducing plasma treatment, or the like. Further, the substrate 1 is transported again to the chemical mechanical polishing step to polish the surface of the Cu wiring 30 thinly, and then the post-cleaning treatment and the hydrogen annealing treatment are performed, and then the cap insulating film 31 is deposited. May go.
  • the cap insulating film 31 may be deposited after cleaning the substrate 1 with hydrofluoric acid (DHF) to remove oxides and Cu particles on the surface.
  • DHF hydrofluoric acid
  • the chemical mechanical polishing method is performed again or the re-cleaning method using hydrofluoric acid is used, the Cu wiring 30 itself is also cut, so that the cross-sectional area becomes small and the electric resistance increases. Care must be taken because of the danger.
  • any one of them may be performed alone, or a plurality of processing may be performed in combination.
  • a management system that allows the leaving period from the post-cleaning process to the deposition process of the cap insulating film 31 to be within four days is adopted, and the leaving period is four days. It is necessary to adopt a management system that immediately executes the above-mentioned regenerating process for the substrate 1 that has passed.
  • each of the production lines ranges from a post-cleaning process to a deposition process of the cap insulating film 31. It is necessary to employ a management system in which the leaving period of the substrate is 4 days or less, and a management system in which the substrate 1 whose leaving period has passed 4 is subjected to a regenerating process.
  • the substrate (wafer) 1 after the post-cleaning process is completed.
  • a normal process control card, a lot number display card, etc. and a standing time control card are stuck on the surface of the wafer case 40 or storage box 41 for storing It is conceivable to enter and manage the date and time when the post-cleaning process is completed and the remaining time.
  • the number of idle days and whether a regeneration process is in progress The number of days that can be left at a glance to determine whether or not it is possible.
  • a reproduction display card, etc. has been created, and as shown in Figure 15, the number of days left in the wafer case storage area in the clean room that stores the wafer case 40 and storage box 41. It is effective to install a display card that describes the necessity of reproduction processing.
  • a cap insulating film 31 is deposited on the host computer that manages all the production lines in the factory after the chemical mechanical polishing process and the post-cleaning process are completed.
  • a data management system will be built in which data such as the idle time until and the presence or absence of playback processing can be entered, and these data can be displayed on a screen on a computer terminal that manages the progress of the lot.
  • a warning to prohibit the deposition of the cap insulating film 31 is displayed on the computer terminal.
  • the process from forming the wiring to depositing the cap insulating film is performed. By performing the process within four days, it is possible to suppress a decrease in the TDDB life of the Cu wiring.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne une ligne de production LSI comprenant les étapes consistant à former un câblage en cuivre dans l'ouverture d'une pellicule isolante par polissage chimico-mécanique, puis à recouvrir la surface du câblage en cuivre à l'aide d'une pellicule isolante de couverture. La durée nécessaire entre la formation du câblage en cuivre et le dépôt de la pellicule isolante de couverture étant fixée à 4 jours. De plus, un substrat semi-conducteur qui a nécessité au moins 4 jours entre l'étape de post-nettoyage et le dépôt de la pellicule isolante de couverture, est soumis à un traitement de régénération, ce qui permet de minimiser une dégradation de la vie TDDB, et de garantir la fiabilité et la rentabilité d'une intégration à grande échelle (LSI).
PCT/JP2003/001233 2002-03-15 2003-02-06 Procede de production d'un dispositif a circuit imprime a semi-conducteur WO2003079429A1 (fr)

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Cited By (6)

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JP2005317808A (ja) * 2004-04-28 2005-11-10 Nitta Haas Inc 薄膜研磨用研磨布およびそれを用いる薄膜の研磨方法
JP2012186480A (ja) * 2003-10-27 2012-09-27 Wako Pure Chem Ind Ltd 半導体基板表面の処理方法
JP2019504480A (ja) * 2015-12-08 2019-02-14 ノースロップ グラマン システムズ コーポレイションＮｏｒｔｈｒｏｐ Ｇｒｕｍｍａｎ Ｓｙｓｔｅｍｓ Ｃｏｒｐｏｒａｔｉｏｎ 超電導デバイス用の非酸化物系誘電体
US10608159B2 (en) 2016-11-15 2020-03-31 Northrop Grumman Systems Corporation Method of making a superconductor device
US10763419B2 (en) 2017-06-02 2020-09-01 Northrop Grumman Systems Corporation Deposition methodology for superconductor interconnects
US10985059B2 (en) 2018-11-01 2021-04-20 Northrop Grumman Systems Corporation Preclean and dielectric deposition methodology for superconductor interconnect fabrication

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JP2001053076A (ja) * 1999-08-10 2001-02-23 Hitachi Ltd 半導体集積回路装置および半導体集積回路装置の製造方法
WO2001024257A1 (fr) * 1999-09-30 2001-04-05 Lam Research Corporation Procedes servant a traiter une couche de semence dans des dispositifs et interconnexions en cuivre
JP2001148385A (ja) * 1999-11-19 2001-05-29 Nec Corp 半導体ウェハおよび半導体装置の製造方法
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JPH1034522A (ja) * 1996-07-17 1998-02-10 Nikon Corp Ｃｍｐ用研磨装置及びｃｍｐ用装置システム
JP2001053076A (ja) * 1999-08-10 2001-02-23 Hitachi Ltd 半導体集積回路装置および半導体集積回路装置の製造方法
WO2001024257A1 (fr) * 1999-09-30 2001-04-05 Lam Research Corporation Procedes servant a traiter une couche de semence dans des dispositifs et interconnexions en cuivre
JP2001148385A (ja) * 1999-11-19 2001-05-29 Nec Corp 半導体ウェハおよび半導体装置の製造方法
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JP2001338927A (ja) * 2000-05-29 2001-12-07 Sony Corp 半導体装置の製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012186480A (ja) * 2003-10-27 2012-09-27 Wako Pure Chem Ind Ltd 半導体基板表面の処理方法
JP2005317808A (ja) * 2004-04-28 2005-11-10 Nitta Haas Inc 薄膜研磨用研磨布およびそれを用いる薄膜の研磨方法
JP2019504480A (ja) * 2015-12-08 2019-02-14 ノースロップ グラマン システムズ コーポレイションＮｏｒｔｈｒｏｐ Ｇｒｕｍｍａｎ Ｓｙｓｔｅｍｓ Ｃｏｒｐｏｒａｔｉｏｎ 超電導デバイス用の非酸化物系誘電体
US10608159B2 (en) 2016-11-15 2020-03-31 Northrop Grumman Systems Corporation Method of making a superconductor device
US10763419B2 (en) 2017-06-02 2020-09-01 Northrop Grumman Systems Corporation Deposition methodology for superconductor interconnects
US10985059B2 (en) 2018-11-01 2021-04-20 Northrop Grumman Systems Corporation Preclean and dielectric deposition methodology for superconductor interconnect fabrication

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JPWO2003079429A1 (ja) 2005-07-21

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