WO2003079429A1

WO2003079429A1 - Production method for semiconductor integrated circuit device

Info

Publication number: WO2003079429A1
Application number: PCT/JP2003/001233
Authority: WO
Inventors: Junji Noguchi
Original assignee: Renesas Technology Corp.
Priority date: 2002-03-15
Filing date: 2003-02-06
Publication date: 2003-09-25
Also published as: JPWO2003079429A1; TW200402843A

Abstract

An LSI production line including the processes of forming Cu wiring in the opening of an insulation film by means of a chemical-mechanical polishing method, and then covering the surface of the Cu wiring with a cap insulation film, wherein time required from the Cu wiring formation up to the cap insulation film deposition is set to be within four days. In addition, a semiconductor substrate that has required at least four days from a post-cleaning step up to the cap insulation film deposition process is subjected to a regenerative treatment, thereby minimizing a deterioration in a TDDB life and ensuring the reliability and production yield of an LSI.

Description

Description Method of manufacturing semiconductor integrated circuit device

The present invention relates to a semiconductor integrated circuit device manufacturing technique, and more particularly to chemical mechanical polishing.

Technology that is effective when applied to the manufacture of semiconductor integrated circuit devices that have a process of forming buried interconnects consisting of a conductive film containing copper (Cu) as a main component using the (Chemical Mechanical Polishing) method It is. Background art

The embedded wiring structure on the semiconductor substrate is formed by embedding the wiring metal film in the wiring embedding opening such as the wiring groove and hole formed in the insulating film, and then chemically polishing the unnecessary metal film outside the opening. It is formed by damascene wiring technology called Single-Damascene or Dual-Damascene, which is removed by a method.

However, when the metal film is copper (Cu), the Cu wiring is in direct contact with the insulating film because it is more easily diffused into the insulating film than other metal films for wiring such as aluminum (AI). By covering the bottom and sides of the Cu wiring with a thin barrier metal film and covering the surface of the Cu wiring with a cap insulating film, Cu atoms in the Cu wiring can be prevented from diffusing into the surrounding insulating film. I'm preventing.

A technique for preventing diffusion into the insulating film around Cu nuclear in the Cu wiring is described in Japanese Patent Application Laid-Open No. H11-111842 / Japanese Patent Application Laid-Open No. H10-50632. Among them, Japanese Patent Application Laid-Open No. 111-1843 discloses a structure in which the upper surface of a Cu wiring is formed lower than the upper surface of an insulating film, and a barrier insulating film is embedded therein. Japanese Patent Application Laid-Open No. 10-50632 discloses a structure in which the upper surfaces of a Cu wiring and a barrier metal film are formed lower than the upper surface of an insulating film, and a barrier insulating film is embedded therein. Disclosure of the invention

The LSI under development by the present inventors forms Cu wiring by the following process.

First, an opening is formed in an insulating film deposited on a semiconductor substrate (wafer), and then a thin barrier metal film such as a titanium nitride film is deposited on the insulating film including the inside of the opening. A Cu film having a thickness greater than the depth of the opening is deposited on the top of the substrate. Next, Cu wiring is formed inside the opening by removing unnecessary Cu film and barrier metal film outside the opening by chemical mechanical polishing.

Next, the semiconductor substrate on which the Cu wiring is formed is transported to a cleaning processing unit, and cleaning for removing foreign substances such as slurry adhered to the surface of the semiconductor substrate in the polishing process (hereinafter referred to as post-cleaning). I do.

The post-cleaning process includes a cleaning process followed by an acid cleaning process. The purpose of the cleaning process is to neutralize the acidic slurry containing an oxidizing agent attached to the surface of the semiconductor substrate, and to clean the surface of the semiconductor substrate while supplying a weak chemical solution. The acid cleaning treatment is for the purpose of removing residual metal, reducing dangling ponds on the surface of the insulating film, and removing irregularities on the surface of the insulating film, etc., while supplying a chemical containing acid to the surface of the semiconductor substrate. Wash.

If the acid contained in the above chemical solution is a strong acid such as dilute hydrofluoric acid (DHF), a thin oxide layer (CuO) on the surface of the Cu wiring generated by the chemical mechanical polishing process is removed. In addition, since the Cu wiring itself is also etched, the cross-sectional area of the Cu wiring may be reduced, and the electric resistance may be increased. Therefore, it is desirable to use a chemical solution containing a weak acid such as an organic acid, particularly when the line width of the Cu wiring is fine. However, if the cleaning is performed using a chemical solution containing an organic acid, the oxide layer (CuO) on the surface of the Cu wiring is not removed. Therefore, after the cleaning, a reduction treatment such as hydrogen anneal is performed and the oxide layer (CuO) is removed. ) Must be removed.

Next, a cap insulating film made of a silicon nitride film or the like is deposited on the surface of the semiconductor substrate on which the post-cleaning process has been completed by using a plasma CVD method or the like.

Here, the present inventor considers a case where the semiconductor substrate (wafer) is left in a clean room between the completion of the post-cleaning process and the deposition of the cap insulating film. However, they found that the TDDB (Time Dependence on Dielectric Breakdown) life of the Cu wiring rapidly decreased after a certain period of time. The TDDB life is a measure for objectively measuring the time dependency of dielectric breakdown. A relatively high voltage is applied between Cu wirings under a measurement condition of a predetermined temperature (for example, 140 ° C). Create a graph in which the time from application to dielectric breakdown is plotted against the applied electric field, and extrapolate the actual electric field strength (for example, 0.2 MVZcm) from this graph to the time (life).

Therefore, when forming Cu wiring on a semiconductor substrate, some measures must be taken to prevent the TDDB life of the Cu wiring from being shortened between the post-cleaning process after polishing and the deposition of the cap insulating film.

An object of the present invention is to provide a technique capable of suppressing a decrease in T DDB life of C _U wiring.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

The following is a brief description of an outline of typical inventions among the inventions disclosed in the present application.

The method of manufacturing a semiconductor integrated circuit device according to one aspect of the present invention includes: (a) depositing a first insulating film on a semiconductor substrate and then forming an opening for wiring embedding in the first insulating film; b) depositing a conductive film containing Cu as a main component on the first insulating film including the inside of the opening; and (c) chemically and mechanically polishing the conductive film to leave the inside of the opening. Forming a Cu wiring in the opening; (d) cleaning the surface of the semiconductor substrate after the (c); and (e) cleaning the semiconductor after the (d). Covering the surface of the Cu wiring with the second insulating film by depositing a second insulating film on the substrate, wherein the step (d) is completed within four days after the step (d) is completed. ) The production line is managed so that the process is performed. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. It is principal part sectional drawing of a conductor board.

FIG. 2 is a cross-sectional view of a main part of a semiconductor substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 5 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 8 is a graph showing the relationship between the number of days the substrate has been left until the cap insulating film is deposited after the post-cleaning process after chemical mechanical polishing and the breakdown electric field strength.

FIG. 9 is a graph showing the standing time dependence of the TDD B life of the sample used for the measurement of FIG.

Figure 10 is a graph of the relationship between the number of days the substrate has been left until the cap insulating film is deposited and the breakdown electric field strength after performing post-cleaning treatment after chemical mechanical polishing using two types of cap insulating films. It is.

FIG. 11 is a schematic diagram showing a degradation model of TDD B life due to standing time considered by the present inventors.

FIG. 12 is an explanatory view showing an example of a method of storing a semiconductor substrate after the post-cleaning process.

09.

FIG. 13 is an explanatory diagram illustrating an example of a method of storing a semiconductor substrate after the post-cleaning process.

FIGS. 14 (a), (b) and (c) are explanatory views showing an example of a substrate management method from the post-cleaning process to the deposition of the cap insulating film.

Figure 15 shows an example of the substrate management method from the post-cleaning process to the deposition of the cap insulating film. FIG.

FIG. 16 is an explanatory diagram illustrating an example of a substrate management method from the post-cleaning process to the deposition of the cap insulating film.

FIG. 17 is a graph showing the TDB life of Cu wiring manufactured by introducing the method of managing a semiconductor substrate according to one embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and the description thereof will not be repeated.

The present embodiment is applied to a method of manufacturing an LSI in which a Cu line is formed on a complementary metal insulator semiconductor field effect transistor (MIS) formed on a semiconductor substrate. The method of manufacturing this LSI will be described below with reference to the drawings.

First, as shown in FIG. 1, a wafer-like semiconductor substrate (hereinafter, referred to as a * plate, sometimes also referred to as a wafer) 1 made of single-crystal silicon is prepared. After forming the p-type well 4 and the n-type well 5, an n-channel MISFETQn is formed in the p-type well ⁴ , and a p-channel MISFETQp is formed in the n-type well 5.

In order to form the element isolation groove 2, the substrate 1 in the element isolation region is etched to form a groove, and then a silicon oxide film 3 is deposited on the substrate 1 including the inside of the groove by a CVD method. The silicon oxide film 3 outside is removed by a chemical mechanical polishing method. In addition, to form the p-type well 4 and the n-type well 5, boron ions are implanted into a part of the substrate 1 and phosphorus ions are implanted into the other part, and then the substrate 1 is heat-treated. These impurities are diffused into the substrate 1.

The n-channel type MISFETQn and the p-channel type MISFETQp may be formed by using any of the well-known processes. For example, they are formed as follows. First, a gate insulating film 6 made of a silicon oxide film is formed on each surface of the p-type well 4 and the n-type well 5 by steam oxidation of the substrate 1. A polycrystalline silicon film is deposited on the upper insulating film 6 by a CVD method, and then phosphorus is ion-implanted into the upper polycrystalline silicon film on the p-type well 4 to form a polycrystalline silicon film on the upper n-type well 5. After ion implantation of boron, the polycrystalline silicon film is buttered by drying using a photoresist film as a mask (the gate electrode 7 is formed).

Next, an n-type semiconductor region 8 having a low impurity concentration is formed by ion-implanting phosphorus or arsenic into the p-type well 4, and a low impurity concentration is formed by ion-implanting boron into the n-type well 5. After the formation of the p-type semiconductor region 9, a silicon nitride film is deposited on the substrate 1 by a CVD method, and then the silicon nitride film is anisotropically etched to form a sidewall on the side wall of the gate electrode 7. A pulse 10 is formed. Next, an n + type semiconductor region 11 (source, drain) having a high impurity concentration is formed by ion-implanting phosphorus or arsenic into the p-type well 4 and ion-implanting boron into the n-type well 5. As a result, a P + type semiconductor region 12 (source, drain) having a high impurity concentration is formed.

Next, after cleaning the surface of the substrate 1, a silicide layer is formed on each of the gate electrode 7, the _n ⁺ type semiconductor region 11 (source, drain) and the p + type semiconductor region 12 (source, drain). Form 1 3 To form the silicide layer 13, a large amount of Co (cobalt) is deposited on the substrate 1 by a sputtering method, and then heat treatment is performed in a nitrogen gas atmosphere to form the substrate 1 and the gate electrode 7 with the Co film. After the reaction, the unreacted Co film is removed by wet etching. With the steps so far, the n-channel type MISFETQ n and the p-channel type MISFETQ p are completed.

Next, as shown in FIG. 2, a first-layer W (tungsten) wiring 20 is formed on the n-channel type MISFET Qn and the p-channel type MISFETQp.

To form the W wiring 20, first, a silicon nitride film 15 and a silicon oxide film 16 are deposited on the substrate 1 by a CVD method, and then the n + -type semiconductor regions 11 (source and drain) and After the silicon oxide film 16 and the silicon nitride film 15 on each of the p + type semiconductor regions 12 (source and drain) are dry-etched to form contact holes 17, the contact holes 17 are formed. Form metal plug 18. The silicon oxide film 16 may be a silicon oxide film formed by a normal CVD method using monosilane (SiH ₄ ) as a source gas, a BPSG (Boron-doped Phospho Silicate Glass) film, or It may be composed of an SOG (Spin On Glass) film formed by a spin coating method.

To form the metal plug 18, a TiN (titanium nitride) film and a W film are deposited by CVD on the silicon oxide film 16 including the inside of the contact hole 17, and then a silicon oxide film Unnecessary TiN film and W film on top of 16 are removed by chemical mechanical polishing.

Next, a W film is deposited on the silicon oxide film 16 by a sputtering method, and the W film is patterned by dry etching using a photoresist film as a mask, thereby forming a first layer on the silicon oxide film 16. The W wiring 20 of the eye is formed. The first layer W wiring 20 is connected to the source and drain (n + type semiconductor region 11) or p channel of the n-channel type MIS FETQn through the metal plug 18 embedded in the contact hole 17. It is electrically connected to the source and drain of the type MISF ETQ p (p + type semiconductor region 12).

Next, as shown in FIG. 3, two insulating films 21 and 22 are deposited on the W wiring 20 by a CVD method or a coating method, and then the insulating films 21 and 22 are formed by dry etching using a photoresist film as a mask. after forming the through hole 23 to 22, to form the metal plug 24 in the through-holes ² 3.

Here, the lower insulating film 21 is formed of silicon oxide to reduce the parasitic capacitance between the W wirings 20 or the parasitic capacitance between the W wiring 20 and the second-layer wiring formed in the next step. It is also made of an insulating material such as an organic polymer having a low dielectric constant and an organic silicon glass. Examples of this type of organic polymer include SiLK (a product of The Dow Chemical Co., USA, dielectric constant = 2.7, heat resistance temperature = 490 ° C or higher, dielectric breakdown voltage = 4.0 to 5. OMV / Vm ) Or polyallyl ether (PAE) based material FLARE (manufactured by Honeywell Electronic Materials, USA, dielectric constant = 2.8, heat resistance = 400 ° C or more). As organic silica glass, for example, HSG-R7 (manufactured by Hitachi Chemical Co., Ltd., relative permittivity = 2.8, heat-resistant temperature = 650 ° C). B lack Diamo η d (manufactured by Applied Materials, Inc., USA) Dielectric constant = 3.0-2.4, heat resistant temperature = 450 ° C), p-MT ES (manufactured by Hitachi, relative permittivity = 3.2), CORAL (manufactured by Novellus Systems, Inc., US, relative permittivity = 2.7 to 2.4, heat resistance temperature = 500 ° C) _{s There are} Si OC-based materials such as Au rora 2.7 (manufactured by Japan ASM Co., Ltd., relative permittivity = 2.7, heat resistance temperature = 450 ° C). The insulating film 21 is composed of the above-mentioned organic insulating material, a Si OF-based material, an HSQ (hydrogen sUsesquioxane) -based material, a MSQ (methyl silsesquioxane) -based material, a porous HSQ-based material, a porous MS Q material, and the like. You may.

The insulating film 22 above the insulating film 21 is formed to protect the insulating film 21 having lower mechanical strength and moisture resistance than the inorganic insulating material. The insulating film 22 is made of, for example, a silicon oxide film deposited by a CVD method, a silicon carbide (SiC) film or a silicon carbonitride (SiCN) film having a lower dielectric constant than the silicon oxide film. . Examples of the silicon carbide film and silicon carbonitride (SSCN) film include BLOk (manufactured by AMAT).

In order to form the metal plug 24 inside the through holes 23 formed in the insulating films 21 and 22, a W film is deposited on the insulating film 22 by a sputtering method, and then unnecessary W on the top of the silicon oxide film 22 is formed. The film is removed by a chemical mechanical polishing method.

Next, as shown in FIG. 4, two insulating films 25 and 26 are deposited on the silicon oxide film 22 by the CVD method, and then the upper portion of the through hole 23 is etched by dry etching using a photoresist film as a mask. A wiring groove 27 is formed in the films 25 and 26.

Of the two insulating films 25 and 26, the upper insulating film 26 is composed of, for example, a silicon oxide film deposited using oxygen and tetraethoxysilane (TEOS) as a source gas. The lower insulating film 25 is a stopper film that prevents the lower insulating film 22 made of a silicon oxide film or the like from being etched when the wiring film 27 is formed by etching the insulating film 26. It is composed of an insulating film such as a silicon film having a large etching selectivity to a silicon oxide film. Further, from the viewpoint of reducing the parasitic capacitance between wirings, a silicon oxynitride (SiON) film or a silicon carbonitride (SiCN) film having a lower dielectric constant than the silicon nitride film may be used.

Next, as shown in FIG. 5, a barrier metal film 28 made of a titanium nitride film or the like is deposited on the insulating film 26 including the inside of the wiring groove 27 by a sputtering method. On top of the metal film 28, a Cu film 30a having a thickness larger than the depth of the wiring groove 27 is deposited by a sputtering method.

The barrier metal film 28 is formed by diffusing the Cu film 30a deposited inside the wiring groove 27 into the surrounding insulating film 26, and the adhesion between the Cu film 30a and the insulating film 26. It is formed in order to improve the quality. The rear metal film 28 can be made of a conductive film such as a tungsten nitride (WN) film, a tantalum nitride (TaN) film, or a titanium tungsten (TiW) film, in addition to a titanium nitride film.

When the Cu film 30a is formed by a sputtering method, the substrate 1 is subjected to a heat treatment in a non-oxidizing atmosphere (for example, a hydrogen atmosphere) after the film formation to reflow the Cu film 30a. In addition, as the sputtering method, a high-directional sputtering method such as a long throw sputtering method and a collimated sputtering method that can satisfactorily bury the Cu film 30a in the wiring groove 27 is used. preferable. The Cu film 30a can be formed by a CVD method, an electrolytic plating method, or an electroless plating method, in addition to the sputtering method. When the electrolytic plating method is used, a thin Cu seed layer is formed on the barrier metal film 28 by a sputtering method, and then the Cu film 3 is formed on the surface of the seed layer using a plating solution such as copper sulfate. Grow 0a. The thin film 303 may be made of a Cu alloy containing Cu as a main component in addition to a single Cu.

Next, as shown in FIG. 6, the Cu film 30a and the barrier metal film 28 outside the wiring groove 27 are removed by a chemical mechanical polishing method, so that the second inside of the wiring groove 27 is formed. A Cu wiring 30 serving as a wiring of the layer is formed. The Cu wiring 30 is electrically connected to the first-layer W wiring 20 via a metal plug 24 embedded in the through hole 23. Here, the Cu wiring 30 is formed by a so-called single damascene method in which the Cu film 30a is buried in the wiring groove 27, but the wiring groove 27 and the through hole 2 below the Cu wiring 30 are formed. The Cu wiring 30 may be formed by a so-called dual damascene method, in which a Cu film 30a is buried in the inside of 3 simultaneously.

The polishing of the Cu film 30a is mainly performed by using abrasive grains such as alumina and silica and an oxidizing agent such as a hydrogen peroxide solution or an aqueous ferric nitrate solution, and dispersing or dissolving them in pure water. A general-purpose polishing slurry may be used, but from the viewpoint of preventing micro scratches generated on the surface of the substrate 1, a slurry containing no abrasive (abrasive free) It is preferred to use (slurry).

The composition of the abrasive free slurry is a mixture of pure water with an oxidizing agent, an organic acid, and a corrosion inhibitor. As the oxidizing agent, hydrogen peroxide (H _₂ 0 _2), hydroxide Anmoniu厶, nitric Anmoniumu, can be exemplified a chloride Anmoniumu, as the organic acid, Kuen acid, malonic acid, fumaric acid, malic acid, Examples thereof include adipic acid, benzoic acid, phthalic acid, tartaric acid, lactic acid, succinic acid, and oxalic acid. Among the above oxidizing agents, hydrogen peroxide is a suitable oxidizing agent to be used for a slurry because it contains no metal component and is not a strong acid. Of the above organic acids, cunic acid is commonly used as a food additive and has low toxicity, low harm as a waste liquid, no odor, and high solubility in water. Preferred organic acids.

Examples of the anticorrosion agent include benzotriazole (BTA), BTA derivatives such as BTA carboxylic acid, dodecyl mercaptan, triazole, and tolyl triazole. Particularly, when benzotriazole is used, Cu A stable corrosion-resistant protective film can be formed on the surface of the wiring 30. The addition amount of the anticorrosive may be about 0.001-1% by weight of the total amount of the slurry. Further, in order to avoid a decrease in the polishing rate due to the addition of the P cariogenic agent, polyacrylic acid, polymethacrylic acid, an ammonium salt thereof, or ethylenediaminetetraacetic acid (EDTA) may be added as necessary.

When chemical mechanical polishing is performed using the above abrasive free slurry, first, the surface of the Cu film 30a is oxidized by an oxidizing agent to form a thin oxide layer (CuO). Next, when a substance for making the oxide water-soluble is supplied, a part of the oxidized layer is eluted as an aqueous solution, and the film thickness is reduced. Then, the thinned portion of the oxide layer on the surface of the Cu film 30a is again exposed to the oxidizing substance, and the thickness of the oxide layer increases. Chemical mechanical polishing of the Cu film 30a proceeds while repeating such a series of reactions.

As the polishing of the Cu film 30a progresses and the film thickness decreases, the surface of the barrier metal film 28 on the insulating film 26 is exposed. In order to polish the barrier metal film 28, a polishing slurry containing abrasive grains such as alumina and silica is used. It is better to use the one with increased number. By using such a polishing slurry, the inside of the wiring groove 27 can be The barrier metal film 28 on the insulating film 26 can be removed without excessively polishing the Cu film 30a.

Next, the surface of the Cu wiring 30 formed as described above is subjected to anticorrosion treatment. This anti-corrosion treatment is a treatment for forming a hydrophobic protective film on the surface of the Cu wiring 30. For example, a chemical solution containing an anti-corrosion agent such as benzotriazole (BTA) described above is applied to the substrate.

This is done by feeding on one surface.

Next, the substrate 1 on which the anticorrosion treatment has been completed is transported to the post-cleaning processing section, and the surface of the substrate 1, that is, the surface of the Cu wiring 30 or the insulating film 26 Removes foreign matter such as slurry attached to the surface.

The substrate 1 that has been subjected to the anticorrosion treatment is temporarily stored in the immersion treatment unit until it is transported to the post-cleaning treatment unit in order to prevent the oxidation of the Cu wiring 30 by drying. The immersion treatment section has a structure in which, for example, a predetermined number of substrates 1 are immersed and stored in an immersion tank (storage force) in which pure water overflows. Prevention of drying of the surface of the substrate 1 is not limited to the above-described method of storing in the immersion tank, as long as at least the surface of the substrate 1 can be kept in a wet state, for example, by supplying a pure water shower. . In addition, the transfer of the substrate 1 from the immersion processing section to the post-cleaning processing section is performed promptly while keeping the surface of the substrate 1 wet.

The post-cleaning process includes an alkali cleaning process and a subsequent acid cleaning process. The alkali cleaning is performed to neutralize an acidic slurry containing an oxidizing agent adhered to the surface of the substrate 1. For example, the surface of the substrate 1 is supplied while supplying a weak chemical solution having a pH of about 8. Scrub or brush wash. An example of the weak alkaline chemical solution is an aqueous solution containing about 0.01% of aminoethanol (DAE: Diluted Amino Ethanol).

The acid cleaning after the alkali cleaning is for the purpose of improving TDDB characteristics, removing residual metal, reducing dangling bonds on the surface of the insulating film 26, and removing irregularities on the surface of the insulating film 26. The surface of the substrate 1 while supplying a chemical containing an organic acid such as an acid, such as Electraclean (EC) (Applied Materials, Inc., pH 5.5) or Silex (CIREX, manufactured by Wako Pure Chemical). Scrub or brush clean. Instead of these cleaning methods, disk-type cleaning methods and pen-type cleaning methods A cleaning method may be used. Further, prior to or in parallel with the post-cleaning process, the surface of the substrate 1 is subjected to pure water scrub cleaning, pure water ultrasonic cleaning, pure water running water cleaning, or pure water spin cleaning, or the back surface of the substrate 1 is purified. Water scrub cleaning may be used.

The above post-cleaning treatment can be performed by a combination of alkali cleaning using ammonium hydroxide and acid cleaning using dilute hydrofluoric acid (DHF). In this case, since the hydrofluoric acid is an acid stronger than the organic acid, the thin oxide layer (CuO) on the surface of the Cu wiring 30 generated by the polishing treatment is removed. Hydrogen annealing can be simplified or omitted. When hydrofluoric acid is used, not only the oxide layer (CuO) on the surface of the Cu wiring 30 but also the Cu wiring 30 itself is etched, so the cross-sectional area of the Cu wiring 30 is reduced. There is a possibility that the electric resistance may increase if it is small. Therefore, especially when the line width of the Cu wiring 30 is fine, acid cleaning using an aqueous solution containing an organic acid is desirable.

On the other hand, when acid cleaning is performed using an aqueous solution containing an organic acid, the oxide layer (CuO) on the surface of the Cu wiring 30 is not removed, and thereafter, the oxide layer (CuO) is removed by performing a hydrogen annealing treatment. There is a need to. Further, even when the acid cleaning is performed using hydrofluoric acid, it is not desirable to completely remove the oxide layer (CuO) during the acid cleaning in order to prevent the Cu wiring 30 from being scraped. Therefore, in this case, it is preferable to stop the acid cleaning in a short time so that the oxide layer (CuO) is not completely removed, and to completely remove the remaining oxide layer (CuO) by hydrogen annealing.

Organic acids and dilute hydrofluoric acid (DHF) are used as acid cleaning chemicals to remove foreign matter remaining on the surface of the Cu wiring 30 and the surface of the insulating film 26 while minimizing scraping of the surface of the Cu wiring 30. ) Can also be used. The concentration of hydrofluoric acid in this chemical solution is set to about 0.1 to 1% in order to minimize scraping of the Cu wiring 30. The concentration of the organic acid should be about 0.1-1%, and the pH should be in the range of 2-6 (preferably about 3). Examples of the organic acid include citric acid, malic acid, oxalic acid, malonic acid, and formic acid. Further, by adding an anticorrosive such as benzotriazole (BTA) described above to the mixed aqueous solution and forming a protective film on the surface of the Cu wiring 30, etching of the Cu wiring 30 by F ions is suppressed. Is also good. Even when BTA is added in this way, 1 "1 is in the range of 2 to 6 (favorable). Adjust to about 3).

When the mixed aqueous solution having the above-described composition is used, the etching rate of Cu can be suppressed to 3 nmz or less, and the etching rate of silicon oxide forming the insulating film 26 can be 1 n or more. The foreign matter on the surface of the insulating film 26 can be lifted off while minimizing the scraping. As a result, the dependence of the TDDB life described later on the standing time can be made the same level (10 days) as the acid cleaning using hydrofluoric acid.

Further, an aqueous solution obtained by adding ammonia to the above-mentioned mixed aqueous solution of the organic acid and the diluted hydrofluoric acid (a mixed aqueous solution of the organic acid, the diluted hydrofluoric acid and ammonium hydroxide) can also be used. In this case, the concentration of each of the organic acid, hydrofluoric acid and ammonium hydroxide should be about 0.1 to 1%. Since this mixed aqueous solution has a pH of about 6 to 8, it is an aqueous solution that is closer to neutral than an acidic aqueous solution, so that the effect of protecting the surface of the Cu wiring 30 is better than when an acidic aqueous solution is used. Is improved. Further, by adding an anticorrosive such as benzotriazole (BTA) to the mixed aqueous solution, the effect of protecting the surface of the Cu wiring 30 is further improved. Even when BTA is added in this way, the pH is adjusted to about 6 to 8.

The above-mentioned% indicating the concentration of the aqueous solution to which hydrofluoric acid, organic acid and ammonia are added means weight%.

When hydrogen annealing is performed on the substrate 1 that has been subjected to the post-cleaning process, the surface moisture is sufficiently removed in advance by a drying process such as a spin drier.

In the hydrogen annealing process, for example, the oxide layer (CuO) on the surface of the Cu wiring 30 is reduced by heat-treating the substrate 1 in a hydrogen gas atmosphere at 200 ° C to 475 ° C for about 0.5 to 5 minutes. This is the process of removing. This hydrogen annealing treatment is desirably performed as soon as possible (preferably within half a day) after the post-cleaning treatment is completed. After the substrate 1 after the cleaning process is left in the clean room for a long time, the oxide layer (CuO) grows on the surface of the Cu wiring 30 that is in contact with the air in the clean room. However, even if hydrogen annealing is performed, the removal of the oxide layer (CuO) will be incomplete, and the TDDB life will be shortened.

Next, as shown in FIG. 7, a silicon nitride film is formed on the insulating film 26 by a CVD method. 0301233

The surface of the Cu wiring 30 is covered with the cap insulating film 3 "I by depositing a cap insulating film 31 made of the same material. In the cap insulating film 31, C C diffuses from the surface of the Cu wiring 30 to the surrounding insulating film. In order to reduce the TDD lifetime of the insulating film, the cap insulating film 31 is formed of a silicon nitride film (ε = 7.0) to reduce the parasitic capacitance between wirings. Lower dielectric constant than silicon carbonitride (SiCN) film (£ = 4.8), silicon carbide (S ί C) film (such as = 4.5), silicon oxynitride (SiON) film (ε = 4.2).

The cap insulating film 31 is deposited using, for example, a parallel plate type plasma CVD apparatus. Before the formation of the cap insulating film 31, ammonia (ΝΗ ₃ ) gas is supplied into the processing chamber of the plasma CVD apparatus. The surface of the substrate 1 may be subjected to an ammonia plasma treatment. Instead of this ammonia plasma treatment, or before or after the ammonia plasma treatment, a hydrogen gas may be supplied into the treatment chamber, and the surface of the substrate 1 may be subjected to the hydrogen plasma treatment.

By subjecting the surface of the substrate 1 to the plasma treatment using a reducing gas as described above, foreign matter on the surface of the substrate 1 that could not be removed by the preceding post-cleaning process or post-cleaning (particularly acid cleaning) Since the residue of organic substances sometimes attached to the surface of the substrate 1 or the oxide layer (Cu u) on the surface of the Cu wiring 30 that could not be removed by the subsequent hydrogen annealing treatment can be almost completely removed. The leakage current on the surface of the u wiring 30 can be reduced to further improve the TDDB life.

According to the knowledge obtained by the present inventor, in order to prevent the TDDB life from being shortened, a series of processes from the post-cleaning process after the above-described chemical mechanical polishing process to the deposition of the cap insulating film 31 are prescribed. It is desirable to perform within the time. That is, if the surface of the substrate 1 is exposed to the air in the clean room for a long time after the formation of the Cu wiring 30 and before the surface is covered with the cap insulating film 31, the TDDB life is reduced. Was clarified by the study of the present inventors.

Figure 8 shows a post-cleaning process after chemical mechanical polishing (CMP) using the above-mentioned aminoethanol aqueous solution (DAE) and CI REX, and then depositing a cap insulating film 31 composed of a silicon nitride film. The graph shows the relationship between the number of days that the substrate was left (horizontal axis) and the breakdown electric field strength (vertical axis). As shown in the figure, after leaving, It was found that the breakdown electric field strength began to decrease, and then decreased to about half of the initial value.

FIG. 9 is a graph showing the dependence of the TDDB life of the same sample on the standing time. As shown in the figure, the TDDB life is the same from the time immediately after standing to the 4th term, but it decreases by about 3 digits between the 4th and 5th days, and about 3 digits between the 5th and 6th days. It was found that the TDD B life decreased sharply after 4 days of standing, such as a decrease of about 3 digits between the 6th and the 11th day.

Next, FIG. 10 shows the result of performing similar measurements by changing the material of the cap insulating film 31 and the chemical solution for post-cleaning. From these results, (1) when the cap insulating film 31 is formed of a silicon carbonitride film, the TDDB life is less deteriorated (about one third) than when the cap insulating film 31 is formed of a silicon nitride film. ) When post-cleaning using hydrofluoric acid, there is not much change in the TDDB life.However, when post-cleaning using CI REX or EC, the TDDB will pass 10 days after standing. It was found that the life was shortened.

Based on the above measurement results, FIG. 11 shows a model of the degradation of the TDD DB life due to the standing time considered by the present inventors.

Observing the surface of the substrate 1 four days after the post-cleaning process using a transmission electron microscope (TEM), many fine Cu particles are generated on the surface of the insulating film 26 between the adjacent Cu wiring 30. Was. It is considered that the Cu particles were caused by the adhesion of moisture in the air to the surface of the Cu wiring 30 exposed to the air in the clean room, and the Cu ions were precipitated. In particular, when post-cleaning is performed using an organic acid such as CI REX or EC, the oxide layer (CuO) on the surface of the Cu wiring 30 is not removed, and thus, the oxidized layer reacts with moisture in the atmosphere and is corroded. Cu ions are easily generated from the layer (CuO). Further, it is considered that a slight potential difference is generated between the Cu wirings 30 formed on the substrate 1 for some reason such as charge-up during chemical mechanical polishing. As a result, it is presumed that the Cu particles flow out to the surface of the insulating film 26 due to the potential difference, causing the deterioration of the TDDB life and the leak between the lines. If post-cleaning is performed using a strong acid such as hydrofluoric acid, the oxide layer (CuO) is removed, and the surface of the Cu wiring 30 is oxidized again to form an oxide layer (CuO). This oxide layer (Cu It takes some time until Cu ions are generated from O). Therefore, in this case, it is considered that the TDDB degradation is less dependent on the standing time than when post-cleaning is performed using an organic acid.

From the above study results, the time from the post-cleaning process after the chemical mechanical polishing process to the deposition of the cap insulating film 31, that is, the time during which the wiring 30 is exposed to the oxygen or moisture in the atmosphere is within 4 words. It was concluded that That is, in an LSI manufacturing line having the above-described Cu wiring forming process, the design and management of the line are performed so that the process from the post-cleaning process to the deposition process of the cap insulating film 31 is completed within four days. It is desirable to do.

In addition, in an actual LSI manufacturing line, there may be a case where the manufacturing line must be temporarily stopped due to an unexpected situation such as equipment failure or occurrence of a defect. Therefore, even if the line is managed so that the process from the post-cleaning process to the deposition process of the cap insulating film 31 can be completed within 4 words, the above period will inevitably pass 4 days. Sometimes.

As a countermeasure, for example, as shown in Fig. 12, store the wafer case 40 containing the substrate (wafer) 1 after the post-cleaning process in the storage box 41 to avoid contact with oxygen and moisture. Therefore, a method of storing the substrate (wafer) 1 while supplying a non-oxidizing gas such as nitrogen substantially free of moisture into the storage box 41 is conceivable. In this case, if the dehumidifying agent 42 is put in the storage box 41 or the dehumidifying agent 42 is put in the wafer case 40 as shown in FIG. The progress of oxidation and corrosion can be more effectively suppressed. Even if the process from the post-cleaning process to the deposition of the cap insulating film 31 is completed within four days, if the surface of the Cu wiring 30 is exposed to the air in the clean room during that time, It is not preferable because it induces the generation of Cu ions described above. Therefore, even in this case, the method of storing the wafer case 40 containing the substrate (wafer) 1 in the storage box 41 as described above is effective.

As another countermeasure when the period from the post-cleaning process to the deposition process of the cap insulating film 31 has passed 4 days, as another measure, after the substrate 1 is transported again to the post-cleaning process and the surface is cleaned. The method of depositing the cap insulating film 31 is also effective. in this case, If the substrate 1 after re-cleaning is left in a clean room for a long time, the surface of the Cu wiring 30 is oxidized and corroded again, so this re-cleaning is performed immediately before the cap insulating film 31 is deposited. It is desirable to carry out. Even in the case where the substrate 1 after the re-cleaning process is unavoidably temporarily left behind, by storing it in the storage box 41 described above, reoxidation and corrosion of the surface of the Cu wiring 30 are minimized. Can be stopped.

Instead of the re-cleaning process, the hydrogen annealing process may be performed again to reduce the surface of the Cu wiring 30 and then the cap insulating film 31 may be deposited. At that time, if it is expected that the time for leaving the substrate 1 will be long, it is effective to repeat the hydrogen annealing every predetermined time. Further, the hydrogen annealing treatment may be performed in combination with the re-cleaning treatment, the reducing plasma treatment, or the like. Further, the substrate 1 is transported again to the chemical mechanical polishing step to polish the surface of the Cu wiring 30 thinly, and then the post-cleaning treatment and the hydrogen annealing treatment are performed, and then the cap insulating film 31 is deposited. May go. Alternatively, the cap insulating film 31 may be deposited after cleaning the substrate 1 with hydrofluoric acid (DHF) to remove oxides and Cu particles on the surface. However, when the chemical mechanical polishing method is performed again or the re-cleaning method using hydrofluoric acid is used, the Cu wiring 30 itself is also cut, so that the cross-sectional area becomes small and the electric resistance increases. Care must be taken because of the danger.

By subjecting the substrate 1 that has passed 4 days from the post-cleaning process to the deposition of the cap insulating film 31 to the regeneration process as described above, the deterioration of the TDDB life is minimized. , LSI reliability and production yield can be ensured. In the above-mentioned reproduction processing, any one of them may be performed alone, or a plurality of processing may be performed in combination.

As described above, in an actual LSI manufacturing line, a management system that allows the leaving period from the post-cleaning process to the deposition process of the cap insulating film 31 to be within four days is adopted, and the leaving period is four days. It is necessary to adopt a management system that immediately executes the above-mentioned regenerating process for the substrate 1 that has passed. In addition, when there are a plurality of LSI production lines having a Cu wiring formation process in a factory, each of the production lines ranges from a post-cleaning process to a deposition process of the cap insulating film 31. It is necessary to employ a management system in which the leaving period of the substrate is 4 days or less, and a management system in which the substrate 1 whose leaving period has passed 4 is subjected to a regenerating process.

As a method of managing the leaving time from the post-cleaning process to the deposition of the cap insulating film 31, for example, as shown in FIGS. 14 (a) and (b), the substrate (wafer) 1 after the post-cleaning process is completed. A normal process control card, a lot number display card, etc. and a standing time control card are stuck on the surface of the wafer case 40 or storage box 41 for storing It is conceivable to enter and manage the date and time when the post-cleaning process is completed and the remaining time.

In addition, in order to reliably prevent management mistakes and work mistakes, besides the idle time control card as described above, for example, as shown in Fig. 14 (c), the number of idle days and whether a regeneration process is in progress The number of days that can be left at a glance to determine whether or not it is possible.Z A reproduction display card, etc., has been created, and as shown in Figure 15, the number of days left in the wafer case storage area in the clean room that stores the wafer case 40 and storage box 41. It is effective to install a display card that describes the necessity of reproduction processing.

Also, as shown in Fig. 16, for example, a cap insulating film 31 is deposited on the host computer that manages all the production lines in the factory after the chemical mechanical polishing process and the post-cleaning process are completed. A data management system will be built in which data such as the idle time until and the presence or absence of playback processing can be entered, and these data can be displayed on a screen on a computer terminal that manages the progress of the lot.

For example, if the idle time has passed 4 times and the regeneration process has not been performed, a warning to prohibit the deposition of the cap insulating film 31 is displayed on the computer terminal. By providing the computer terminal with a function to indicate that it is close to the above and to emit a warning sound, management mistakes and work mistakes can be more reliably prevented.

As shown in FIG. 17, as a result of introducing the above-described management method of the present embodiment, it was possible to effectively suppress the deterioration of the TDBD life of the Cu distribution 30 line.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and does not depart from the gist of the invention. It goes without saying that various changes can be made within the range. Industrial applicability

After forming wiring containing copper as a main component in the opening of the insulating film using a chemical mechanical polishing method, when covering the surface of the wiring with a cap insulating film, the process from forming the wiring to depositing the cap insulating film is performed. By performing the process within four days, it is possible to suppress a decrease in the TDDB life of the Cu wiring.

Claims

The scope of the claims

1. (a) after forming a first insulating film on a semiconductor substrate, forming an opening for wiring embedding in the first insulating film;

(b) forming a conductive film containing copper as a main component on the first insulating film including the inside of the opening;

(c) forming a wiring made of the conductive film in the opening by chemically and mechanically polishing and leaving the conductive film in the opening;

(d) washing the surface of the semiconductor substrate after the step (c);

(e) after the step (d), forming a second insulating film on the semiconductor substrate to cover an upper surface of the wiring with the second insulating film,

A method for manufacturing a semiconductor integrated circuit device, wherein the step (e) is performed within 4 days after the step (d) is completed.

2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step of cleaning the surface of the semiconductor substrate includes an acid cleaning treatment using a chemical solution containing an organic acid.

3. The semiconductor integrated circuit device according to claim 2, further comprising a step of performing a hydrogen annealing treatment on the surface of the semiconductor substrate after the acid cleaning treatment and prior to the step (e). Method.

4. The semiconductor integrated circuit according to claim 1, further comprising a step of storing the semiconductor substrate in a non-oxidizing gas atmosphere from the end of the step (d) to the start of the step (e). A method for manufacturing a circuit device.

5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the non-oxidizing gas atmosphere does not substantially contain moisture.

6. The first insulating film is made of an insulating film containing silicon oxide as a main component, and the second insulating film is made of an insulating film containing silicon nitride, silicon carbonitride, silicon carbide, or silicon oxynitride as a main component. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein:

7. A method of manufacturing a semiconductor integrated circuit device including the following steps (a) to (f): (a) after forming a first insulating film on a semiconductor substrate, forming an opening for wiring embedding in the first insulating film;

(d) washing the surface of the semiconductor substrate after the step (c);

(e) after the step (d), a step of re-cleaning the surface of the semiconductor substrate;

(f) a step of, after the step (e), forming a second insulating film on the semiconductor substrate to cover an upper surface of the wiring with the second insulating film;

8. The semiconductor integrated circuit according to claim 7, wherein the step (e) is performed when five days or more elapse after the completion of the step (d) and before the start of the step (e). Device manufacturing method.

9. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the cleaning in the step (d) includes an acid cleaning treatment using a chemical solution containing an organic acid.

10. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the re-cleaning in the step (e) includes an acid cleaning treatment using a chemical solution containing hydrofluoric acid.

1 1. A method of manufacturing a semiconductor integrated circuit device including the following steps (a) to (f):

(a) after depositing a first insulating film on a semiconductor substrate, forming an opening for wiring embedding in the first insulating film;

(b) depositing a conductive film containing copper as a main component on the first insulating film including the inside of the opening;

(d) washing the surface of the semiconductor substrate after the step (c);

(e) after the step (d), a step of hydrogen annealing the surface of the semiconductor substrate

(f) a step of, after the step (e), depositing a second insulating film on the semiconductor substrate to cover an upper surface of the wiring with the second insulating film.

10. The semiconductor according to claim 10, wherein the step (e) is performed when five days or more elapse after the completion of the step (d) and before the start of the step (e). A method for manufacturing an integrated circuit device.

1 3. A method for manufacturing a semiconductor integrated circuit device including the following steps (a) to (g):

(b) a conductive film containing copper as a main component on the first insulating film including the inside of the opening;

(θ) forming a wiring made of the conductive film in the opening by chemically and mechanically polishing and leaving the conductive film in the opening;

(d) washing the surface of the semiconductor substrate after the step (c);

(e) a step of chemically and mechanically polishing the surface of the semiconductor substrate after the step (d);

(f) washing the surface of the semiconductor substrate after the step (e);

(g) After the step (f), a step of covering the upper surface of the wiring with the second insulating film by depositing a second insulating film on the semiconductor substrate.

1 4. The step (e) and the step (f) are carried out when five or more have passed after the completion of the step (d) and before the start of the step (e). 13. The method for manufacturing a semiconductor integrated circuit device according to claim 13.

15. The method of manufacturing a semiconductor integrated circuit device according to claim 7, 11 or 13, wherein copper deposited on a surface of the first insulating film is removed by the step (e).

1 6. The first insulating film is made of an insulating film containing silicon oxide as a main component, and the second insulating film is an insulating film containing silicon nitride, silicon carbonitride, silicon carbide or silicon oxynitride as a main component. 14. The method for manufacturing a semiconductor integrated circuit device according to claim 7, 11 or 13, wherein the method comprises a film.

17. The method according to claim 7, further comprising a step of storing the semiconductor substrate in a non-oxidizing gas atmosphere from the end of the step (d) to the start of the step (e). 13. The method for manufacturing a semiconductor integrated circuit device according to 1 or 13.

18. The method for manufacturing a semiconductor integrated circuit device according to claim 17, wherein the non-oxidizing gas atmosphere does not substantially contain moisture.

1 9. (a) forming an opening for wiring embedding in the first insulating film after depositing a first insulating film on a plurality of semiconductor substrates;

(d) washing the surface of the semiconductor substrate after the step (c);

(e) after the step (d), covering the upper surface of the wiring with the second insulating film by depositing a second insulating film on the semiconductor substrate,

Of the plurality of semiconductor substrates, a semiconductor substrate that performs the above-mentioned step (e) within a predetermined time after the completion of the step (d); A step of managing each of the semiconductor substrates for which the predetermined time has elapsed before the start of the semiconductor integrated circuit device.

20. The semiconductor integrated circuit device according to claim 19, wherein, when there are a plurality of manufacturing lines for performing the steps (a) to (e), the management is performed in each of the lines. Manufacturing method.

21. The method for manufacturing a semiconductor integrated circuit device according to claim 19, wherein the predetermined time is four days.

22. The method of manufacturing a semiconductor integrated circuit device according to claim 19, wherein the step (d) includes an acid cleaning treatment using a chemical solution containing an organic acid.

23. The semiconductor integrated circuit device according to claim 22, further comprising a step of performing a hydrogen annealing treatment on the surface of the semiconductor substrate after the acid cleaning treatment and prior to the step (e). Production method.

24. The first insulating film is made of an insulating film containing silicon oxide as a main component, and the second insulating film is made of an insulating film containing silicon nitride, silicon carbonitride, silicon carbide, or silicon oxynitride as a main component. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 19, comprising:

25. (a) after forming a first insulating film on a semiconductor substrate, forming an opening for wiring embedding in the first insulating film;

(d) washing the surface of the semiconductor substrate after the step (c);

A method for manufacturing a semiconductor integrated circuit device, comprising: storing the semiconductor substrate in a non-oxidizing gas atmosphere from the end of the step (d) to the start of the step (e).

26. The semiconductor device according to claim 25, wherein a period of time during which the semiconductor substrate is exposed to an oxidizing atmosphere within four days from the end of the step (d) to the start of the step (e). Of manufacturing a semiconductor integrated circuit device.

27. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the cleaning in the step (d) includes a pickling treatment using a chemical solution containing an organic acid and hydrofluoric acid.

28. The method for manufacturing a semiconductor integrated circuit device according to claim 27, wherein the chemical solution further contains ammonium hydroxide.