JP2001148385A - Semiconductor wafer and manufacturing method of semiconductor device - Google Patents
Semiconductor wafer and manufacturing method of semiconductor deviceInfo
- Publication number
- JP2001148385A JP2001148385A JP32932499A JP32932499A JP2001148385A JP 2001148385 A JP2001148385 A JP 2001148385A JP 32932499 A JP32932499 A JP 32932499A JP 32932499 A JP32932499 A JP 32932499A JP 2001148385 A JP2001148385 A JP 2001148385A
- Authority
- JP
- Japan
- Prior art keywords
- manufacturing
- copper
- compound
- semiconductor wafer
- anticorrosive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体ウェハの製
造方法、特に、銅または銅合金が露出した半導体装置の
洗浄工程を含む半導体ウェハの製造方法に関し、さらに
は、このような半導体ウェハを用いた半導体装置の製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor wafer, and more particularly to a method for manufacturing a semiconductor wafer including a step of cleaning a semiconductor device having copper or a copper alloy exposed. And a method for manufacturing a semiconductor device.
【0002】[0002]
【従来の技術】近年、半導体装置の金属配線の材料とし
て、銅または銅を80%以上含有する銅合金(以下、C
uと記す)が用いられつつある。Cuを用いた配線は、
一般に、ダマシン法により作製される。図7は、ダマシ
ンCu配線を作製する従来の半導体装置の製造方法の工
程を示す。また図8は、この製造工程における半導体ウ
ェハの部分断面を示す。2. Description of the Related Art In recent years, copper or a copper alloy containing 80% or more of copper (hereinafter referred to as C
u) are being used. Wiring using Cu
Generally, it is produced by a damascene method. FIG. 7 shows steps of a conventional method for manufacturing a semiconductor device for producing a damascene Cu wiring. FIG. 8 shows a partial cross section of the semiconductor wafer in this manufacturing process.
【0003】図8(A)に示すように、半導体基板10
または図示しない層間膜上にシリコン酸化膜(以下、S
iO2 膜と記す)などの絶縁膜12が形成され、絶縁膜
の一部に配線が形成される。配線溝の内側にTa,Ta
Nなどのバリア膜14が形成され、シード用のCu膜1
5がスパッタ法またはCVD法により形成され、電解メ
ッキによりCu16が付着される。[0003] As shown in FIG.
Alternatively, a silicon oxide film (hereinafter referred to as S
An insulating film 12 such as an iO 2 film) is formed, and wiring is formed in a part of the insulating film. Ta, Ta inside the wiring groove
A barrier film 14 such as N is formed, and the seed Cu film 1 is formed.
5 is formed by a sputtering method or a CVD method, and Cu16 is attached by electrolytic plating.
【0004】以上の半導体ウェハ1を洗浄装置にロード
して、図7のCu−CMP工程20で、配線溝内にCu
を残して、上部のCuを除去して、図8(B)に示すよ
うに、Cu配線17を形成する。The above-described semiconductor wafer 1 is loaded into a cleaning apparatus, and Cu-CMP step 20 shown in FIG.
, The upper Cu is removed, and a Cu wiring 17 is formed as shown in FIG.
【0005】次に、スクラブ洗浄工程22で、ブラシス
クラブ等の洗浄処理によって粒子汚染を除去し、続いて
スピン洗浄工程24で、カルボン酸系(シュウ酸等)の
洗浄液で金属汚染を除去する。続いて、スピンリンス・
乾燥工程26でリンス,乾燥して、洗浄装置からアンロ
ードされる。[0005] Next, in a scrub cleaning step 22, particle contamination is removed by a brush scrub or the like, and subsequently, in a spin cleaning step 24, metal contamination is removed with a carboxylic acid-based (oxalic acid) cleaning solution. Next, spin rinse
In the drying step 26, the wafer is rinsed and dried, and is unloaded from the cleaning device.
【0006】その後、成膜工程28で、半導体ウェハの
表面上に、シリコン窒化膜(以下、Si3 N4 膜と記
す),SiONなどのCu拡散抑止絶縁膜を成膜するた
めに、成膜装置に送られ、図8(C)に示すように、半
導体ウェハ表面に、例えばSi 3 N4 膜18が成膜され
る。その後、SiO2 などの層間膜19が成膜される。Then, in a film forming step 28, the semiconductor wafer
A silicon nitride film (hereinafter referred to as SiThree NFour Note as membrane
To form a Cu diffusion suppression insulating film such as SiON.
To the film forming apparatus, and as shown in FIG.
For example, Si Three NFour The film 18 is formed
You. After that, the SiOTwo Is formed.
【0007】以上の製造工程では、半導体ウェハが、C
MP後洗浄が終わって洗浄装置から取り出した後、Si
3 N4 成膜装置の真空室にロードされるまでの間、半導
体ウェハは大気中に放置される。この放置時間は、成膜
装置にロードされるまでの待ち時間に依存するが、実際
の製造現場においては日単位で待つことが想定される。In the above manufacturing process, the semiconductor wafer is
After the post-MP cleaning and removal from the cleaning device, the Si
Until it is loaded into the vacuum chamber of 3 N 4 film forming apparatus, the semiconductor wafer is left in the atmosphere. Although this waiting time depends on the waiting time until the film is loaded into the film forming apparatus, it is assumed that the actual manufacturing site waits on a daily basis.
【0008】[0008]
【発明が解決しようとする課題】上述した従来の半導体
装置の製造方法では、大気に曝された半導体ウェハにC
u拡散抑止絶縁膜を成膜するとCu表面とCu拡散抑止
絶縁膜との間の界面の密着性が劣化するという問題があ
った。In the above-mentioned conventional method for manufacturing a semiconductor device, the semiconductor wafer exposed to the air is exposed to C
When the u-diffusion suppressing insulating film is formed, there is a problem that the adhesion at the interface between the Cu surface and the Cu diffusion suppressing insulating film is deteriorated.
【0009】また、Cu拡散抑止絶縁膜の成膜中、また
はその後の工程において、膜の応力が加わったり熱処理
が施されたときに、Cu配線の表面にヒロック(hil
llock)が発生することがあった。During the formation of the Cu diffusion suppressing insulating film or during a subsequent process, when a stress of the film is applied or heat treatment is performed, a hillock (hill) is formed on the surface of the Cu wiring.
lllock) sometimes occurred.
【0010】前述したようなCu/Cu拡散抑止絶縁膜
界面の密着不良があると、Cu配線に電流が流れたとき
の電流ストレスにより、CuがCu配線とCu拡散抑止
絶縁膜との間の隙間に入り込み、隣りの配線との間でシ
ョートを発生し、半導体装置の信頼性を低下させるとい
う問題を生じる。また、Cu配線表面にヒロックが発生
すると、半導体装置の信頼性を低下させる。If there is a poor adhesion at the interface of the Cu / Cu diffusion suppressing insulating film as described above, the current stress generated when a current flows through the Cu wiring causes Cu to form a gap between the Cu wiring and the Cu diffusion suppressing insulating film. And a short circuit occurs between the wiring and an adjacent wiring, which causes a problem of lowering the reliability of the semiconductor device. Further, when hillocks are generated on the surface of the Cu wiring, the reliability of the semiconductor device is reduced.
【0011】本出願の発明者らは、その原因を究明した
ところ、次のようなことがわかった。すなわち、CMP
後洗浄後、Cu拡散抑止絶縁膜の成膜前にウェハが大気
に曝されると、Cu配線の表面が酸化されてCuOx
(以下、CuOと記す)が形成され、これが密着性の不
良の原因となっていることである。また、Cu配線の表
面上にCuOが不均一に形成される、すなわち形成され
た箇所と形成されない箇所が分布して存在するような場
合に、ヒロックが発生することがある。The inventors of the present application have investigated the cause and found the following. That is, CMP
If the wafer is exposed to the air after the post-cleaning and before the formation of the Cu diffusion suppressing insulating film, the surface of the Cu wiring is oxidized and CuOx
(Hereinafter referred to as CuO), which is a cause of poor adhesion. Further, when CuO is unevenly formed on the surface of the Cu wiring, that is, in a case where a formed portion and a non-formed portion exist in a distributed manner, hillocks may be generated.
【0012】したがって、本出願の発明者らは、Cu拡
散抑止絶縁膜の成膜前に、半導体ウェハが大気に曝され
ても、Cu配線表面が酸化されず、したがってCu配線
表面にCuOが形成されないようにすれば良いことに思
い到った。Therefore, the inventors of the present application have found that even if the semiconductor wafer is exposed to the atmosphere before the formation of the Cu diffusion suppressing insulating film, the Cu wiring surface is not oxidized, and thus CuO is formed on the Cu wiring surface. I came up with something that should not be done.
【0013】したがって本発明の目的は、大気に曝され
ても、Cu配線の表面が酸化されない半導体ウェハを提
供することにある。Accordingly, an object of the present invention is to provide a semiconductor wafer in which the surface of a Cu wiring is not oxidized even when exposed to the atmosphere.
【0014】本発明の他の目的は、このような半導体ウ
ェハの製造方法を提供することにある。Another object of the present invention is to provide a method for manufacturing such a semiconductor wafer.
【0015】本発明のさらに他の目的は、Cu拡散防止
絶縁膜との密着性不良の問題を解決した半導体装置の製
造方法を提供することにある。Still another object of the present invention is to provide a method for manufacturing a semiconductor device which solves the problem of poor adhesion to a Cu diffusion preventing insulating film.
【0016】本発明のさらに他の目的は、ヒロックの発
生を防止した半導体装置の製造方法を提供することにあ
る。Still another object of the present invention is to provide a method of manufacturing a semiconductor device in which hillocks are prevented from occurring.
【0017】[0017]
【課題を解決するための手段】本発明の半導体ウェハの
製造方法によれば、ダマシンCu配線を形成するための
Cu−CMP後の洗浄処理工程の中で、防食剤を添加し
た水溶液で処理することにより、Cu配線表面にCuと
防食剤との化合物よりなる防食膜を形成する。この膜が
存在することにより、Cu配線表面の酸化の防止を図る
ことができる。したがって、次工程のCu拡散抑止膜を
成膜する工程の前に、半導体ウェハが大気に曝されて
も、Cu配線表面が酸化されないので、成膜されたCu
拡散抑止絶縁膜の密着性が良好となる。また、CuO膜
が形成されないので、熱処理工程によりCu配線表面に
ヒロックが生じることはない。According to the method of manufacturing a semiconductor wafer of the present invention, in a cleaning process after Cu-CMP for forming damascene Cu wiring, the semiconductor wafer is treated with an aqueous solution containing an anticorrosive agent. Thus, an anticorrosion film made of a compound of Cu and an anticorrosive is formed on the surface of the Cu wiring. The presence of this film can prevent oxidation of the Cu wiring surface. Therefore, even before the semiconductor wafer is exposed to the atmosphere, the Cu wiring surface is not oxidized before the next step of forming the Cu diffusion suppressing film, so that the formed Cu
The adhesion of the diffusion suppressing insulating film is improved. Further, since the CuO film is not formed, hillocks do not occur on the Cu wiring surface due to the heat treatment process.
【0018】Cu配線からCuの拡散を抑止するために
は、配線上に被覆される絶縁膜は、Si3 N4 ,SiO
N,SiO2 などがある。In order to suppress the diffusion of Cu from the Cu wiring, the insulating film coated on the wiring is made of Si 3 N 4 , SiO 2
N, SiO 2 and the like.
【0019】Cuの防食剤として代表的なものはベンゾ
トリアゾール(BTA)が知られている。BTAを半導
体装置の配線形成の際に用いる技術は、特開平8−64
594「配線の形成方法」、および特開平11−405
26号公報「配線形成方法及び半導体装置の製造方法」
に既に開示されている。これら技術は、CMPと同時
に、あるいはCMP直後にBTAをCu表面に接触させ
て、防食の効果を上げている。Benzotriazole (BTA) is known as a typical anticorrosive for Cu. A technique using BTA when forming wiring in a semiconductor device is disclosed in
594, "Method of forming wiring", and JP-A-11-405.
No. 26, “Wiring forming method and semiconductor device manufacturing method”
Has already been disclosed. In these techniques, BTA is brought into contact with the Cu surface at the same time as or immediately after CMP to enhance the anticorrosion effect.
【0020】本発明は、これら従来技術とは異なり、C
MP後の洗浄処理の工程の中で、防食剤を添加した水溶
液で金属配線表面を処理することを特徴としている。The present invention differs from these prior arts in that C
In the cleaning process after the MP, the surface of the metal wiring is treated with an aqueous solution containing an anticorrosive agent.
【0021】さらに本発明者らは、防食剤として、窒素
2個の四員環化合物、または窒素3個の複素五員環もし
くは六員環化合物、またはその誘導体のいずれか1種、
またはこれらの2種以上の混合物よりなる防食剤が有効
であることを確かめた。Further, the present inventors have proposed, as an anticorrosive, a four-membered ring compound having two nitrogen atoms, a five- or six-membered heterocyclic ring compound having three nitrogen atoms, or a derivative thereof,
Alternatively, it was confirmed that an anticorrosive composed of a mixture of two or more of these was effective.
【0022】窒素3個の複素五員環化合物はトリアゾー
ル系化合物であり、窒素3個の複素六員環化合物はトリ
アジン系化合物である。トリアゾール系化合物として
は、前述のベンゾトリアゾール以外に、o−トリルトリ
アゾール、m−トリルトリアゾール、p−トリルトリア
ゾール、カルボキシベンゾトリアゾール、1−ヒドロキ
シベンゾトリアゾール、ニトロベンゾトリアゾール、ジ
ヒドロキシプロピルベンゾトリアゾール等を挙げること
ができる。さらには、ベンゾトリアゾールの誘導体、例
えば、チバ・スペシャリティー・ケミカルズ社から市販
されているイルガメットシリーズ、具体的には、イルガ
メット42(2,2’−[[(メチル−1H−ベンゾト
リアゾール−1−イル)メチル]イミノ]ビス−エタノ
ール)等も好適に使用される。The three-nitrogen hetero five-membered ring compound is a triazole-based compound, and the three-nitrogen hetero six-membered ring compound is a triazine-based compound. Examples of the triazole-based compound include, in addition to the above-mentioned benzotriazole, o-tolyltriazole, m-tolyltriazole, p-tolyltriazole, carboxybenzotriazole, 1-hydroxybenzotriazole, nitrobenzotriazole, dihydroxypropylbenzotriazole, and the like. Can be. Furthermore, derivatives of benzotriazole, for example, Irgamet series commercially available from Ciba Specialty Chemicals, specifically Irgamet 42 (2,2 '-[[(methyl-1H-benzotriazole-1) -Yl) methyl] imino] bis-ethanol) and the like are also suitably used.
【0023】これら防食剤の添加率は、1ppm以上で
効果を示すことが確認された。また、BTA等は環境上
の問題と溶解度から、最大の添加率は、5%とするのが
好ましい。It has been confirmed that the effect of adding these anticorrosives is 1 ppm or more. The maximum addition ratio of BTA and the like is preferably set to 5% in view of environmental problems and solubility.
【0024】この他の防食剤としては、酸化抑制剤であ
る、芳香族ベンゼン環を有する化合物のガリック酸,タ
ンニン酸等も用いることができる。これらの添加率は、
BTAなどの防食剤と同様の考えで、0.01〜5%と
するのが好適である。As other anticorrosive agents, compounds having an aromatic benzene ring, such as gallic acid and tannic acid, which are oxidation inhibitors, can also be used. These addition rates are
It is preferable to set the content to 0.01 to 5% based on the same idea as the anticorrosive such as BTA.
【0025】以上のような防食剤を添加した水溶液(防
食液)による処理は、CMP後洗浄装置の中で、連続シ
ーケンスとして行う必要がある。というのは、例えば、
金属汚染除去のためのスピン洗浄後に続いて、防食処理
を行うが、この工程間に時間の不連続があると、金属表
面にCuOが形成されるおそれがあるからである。The treatment with the aqueous solution (anticorrosion liquid) to which the anticorrosive agent is added as described above must be performed as a continuous sequence in a post-CMP cleaning apparatus. Because, for example,
The anticorrosion treatment is performed after the spin cleaning for removing metal contamination. If there is a discontinuity in time between the steps, CuO may be formed on the metal surface.
【0026】このような問題を避けるためには、金属汚
染除去のためのスピン洗浄時に、洗浄液に防食液を混合
して、洗浄と防食処理を同時に施すようにしてもよい。In order to avoid such a problem, at the time of spin cleaning for removing metal contamination, an anticorrosive solution may be mixed with the cleaning solution so that the cleaning and the anticorrosion treatment are performed simultaneously.
【0027】[0027]
【0028】[0028]
【第1の実施形態】図1は、本発明の第1の実施形態で
ある半導体装置の製造方法を示す工程図である。図7の
従来の製造方法と異なる点は、防食処理工程25が付加
されたことである。したがって、図1において図7と同
じ工程は、同一の参照番号を付して示している。なお、
この実施形態において製造される半導体装置は、図8で
説明したものと同一ものとする。First Embodiment FIG. 1 is a process chart showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention. The difference from the conventional manufacturing method of FIG. 7 is that an anticorrosion treatment step 25 is added. Therefore, in FIG. 1, the same steps as those in FIG. 7 are denoted by the same reference numerals. In addition,
The semiconductor device manufactured in this embodiment is the same as that described with reference to FIG.
【0029】Cu−CMP工程20では、図8(A)の
構造の半導体ウェハ1に形成された絶縁膜12上のCu
(シードCu15,メッキCu16)とバリア膜14を
CMPで研磨して除去し、Cu配線17を形成する(図
8(B)参照)。なお、CMPのスラリーにBTAなど
の防食剤を添加して、Cu表面が酸化されるのを防止す
ることが知られている。In the Cu-CMP step 20, Cu-CMP on the insulating film 12 formed on the semiconductor wafer 1 having the structure shown in FIG.
(Seed Cu 15, plating Cu 16) and the barrier film 14 are polished and removed by CMP to form a Cu wiring 17 (see FIG. 8B). It is known that an anticorrosive such as BTA is added to the CMP slurry to prevent the Cu surface from being oxidized.
【0030】Cu−CMP後は、半導体ウェハ表面は、
研磨砥粒および研磨屑などの粒子、金属,スラリーなど
が付着し、汚染されている。After Cu-CMP, the surface of the semiconductor wafer becomes
Particles such as abrasive grains and polishing debris, metals, slurries, etc. adhere and are contaminated.
【0031】スクラブ洗浄工程22では、まず、回転す
るブラシに電解イオン水,溶存水素水などの洗浄液をか
けながら、ブラシを移動させて、粒子汚染を除去する。In the scrub cleaning step 22, first, the brush is moved while applying a cleaning liquid such as electrolytic ionic water or dissolved hydrogen water to the rotating brush to remove particle contamination.
【0032】次に、スピン洗浄工程24では、半導体ウ
ェハを回転させながら、カルボン酸系であるシュウ酸の
0.03%水溶液よりなる洗浄液を10秒間吹きかけ、
金属汚染すなわち表面のCuOを除去し、純水でリンス
する。なお、シュウ酸の濃度は0.01〜1%水溶液で
あってもよく、水溶液を吹きかける時間は10〜30秒
であってもよい。シュウ酸以外に、クエン酸等の有機酸
を使用してもよい。Next, in a spin cleaning step 24, a cleaning liquid composed of a 0.03% aqueous solution of oxalic acid, which is a carboxylic acid, is sprayed for 10 seconds while rotating the semiconductor wafer.
Metal contamination, that is, CuO on the surface is removed and rinsed with pure water. The concentration of oxalic acid may be a 0.01 to 1% aqueous solution, and the time for spraying the aqueous solution may be 10 to 30 seconds. In addition to oxalic acid, an organic acid such as citric acid may be used.
【0033】次に、防食処理工程25で、ウェハ表面を
処理し、Cu配線17の防食を行う。防食液は、1%の
BTAを添加したBTA水溶液を用意し、半導体ウェハ
1を回転させながら、BTA水溶液を1リットル/分の
流量で10秒間、ウェハ表面に吹きかけ、Cu膜の防食
を行った。Next, in the anticorrosion treatment step 25, the surface of the wafer is treated to prevent the Cu wiring 17 from being corroded. As the anticorrosion solution, a BTA aqueous solution to which 1% BTA was added was prepared, and while rotating the semiconductor wafer 1, the BTA aqueous solution was sprayed onto the wafer surface at a flow rate of 1 liter / min for 10 seconds to perform corrosion prevention of the Cu film. .
【0034】次のスピンリンス・乾燥工程26で、純水
で15秒間リンスを行った後、乾燥させた。In the next spin rinsing / drying step 26, the substrate was rinsed with pure water for 15 seconds and then dried.
【0035】さらに本発明者らは、防食剤として、窒素
2個の複素四員環化合物、または窒素3個の複素五員環
もしくは六員環化合物、またはその誘導体のいずれか1
種、またはこれらの2種以上の混合物よりなる防食剤が
有効であることを確かめた。Further, the present inventors have proposed, as an anticorrosive, any one of a nitrogen four-membered heterocyclic compound, a nitrogen three-membered five- or six-membered ring compound, and a derivative thereof.
It was confirmed that an anticorrosive consisting of a seed or a mixture of two or more of these was effective.
【0036】窒素3個の複素五員環化合物はトリアゾー
ル系化合物であり、窒素3個の複素六員環化合物はトリ
アジン系化合物である。トリアゾール系化合物として
は、前述のベンゾトリアゾール以外に、o−トリルトリ
アゾール、m−トリルトリアゾール、p−トリルトリア
ゾール、カルボキシベンゾトリアゾール、1−ヒドロキ
シベンゾトリアゾール、ニトロベンゾトリアゾール、ジ
ヒドロキシプロピルベンゾトリアゾール等を挙げること
ができる。さらには、ベンゾトリアゾールの誘導体、例
えば、チバ・スペシャリティー・ケミカルズ社から市販
されているイルガメットシリーズ、具体的には、イルガ
メット42(2,2’−[[(メチル−1H−ベンゾト
リアゾール−1−イル)メチル]イミノ]ビス−エタノ
ール)等も好適に使用される。The five-membered heterocyclic compound having three nitrogen atoms is a triazole compound, and the six-membered heterocyclic compound having three nitrogen atoms is a triazine compound. Examples of the triazole-based compound include, in addition to the above-mentioned benzotriazole, o-tolyltriazole, m-tolyltriazole, p-tolyltriazole, carboxybenzotriazole, 1-hydroxybenzotriazole, nitrobenzotriazole, dihydroxypropylbenzotriazole, and the like. Can be. Furthermore, derivatives of benzotriazole, for example, Irgamet series commercially available from Ciba Specialty Chemicals, specifically Irgamet 42 (2,2 '-[[(methyl-1H-benzotriazole-1) -Yl) methyl] imino] bis-ethanol) and the like are also suitably used.
【0037】これら防食剤の添加率は、1ppm%以上
で効果を示すことが確認された。また、BTA等は環境
上の問題と溶解度から、最大の添加率は、5%とするの
が好ましい。It was confirmed that the effect of adding these anticorrosives was 1 ppm% or more. The maximum addition ratio of BTA and the like is preferably set to 5% in view of environmental problems and solubility.
【0038】この他の防食剤としては、酸化抑制剤であ
る、芳香族ベンゼン環を有する化合物のガリック酸,タ
ンニン酸等も用いることができる。これらの添加率は、
BTAなどの防食剤と同様の考えで、0.01〜5%と
するのが好適である。As other anticorrosive agents, compounds having an aromatic benzene ring, such as gallic acid and tannic acid, which are oxidation inhibitors, can also be used. These addition rates are
It is preferable to set the content to 0.01 to 5% based on the same idea as the anticorrosive such as BTA.
【0039】以上のようにして得られた半導体ウェハ
を、数時間〜数日間、大気の下に放置した後、成膜工程
28で、Si3 N4 膜18をCVD法により400℃で
10〜15秒処理し、50nmの膜厚のSi3 N4 膜1
8を成膜し、その上に、プラズマ酸化膜を400℃,7
0秒間処理して層間膜19を1.1μm成膜した(図8
(C)参照)。After the semiconductor wafer obtained as described above is allowed to stand in the air for several hours to several days, in a film forming step 28, a Si 3 N 4 film 18 is formed at 400 ° C. by a CVD method for 10 to 10 days. Treated for 15 seconds, Si 3 N 4 film 1 with a thickness of 50 nm
8 was formed, and a plasma oxide film was formed thereon at 400 ° C. for 7 minutes.
By treating for 0 seconds, an interlayer film 19 was formed to a thickness of 1.1 μm (FIG. 8
(C)).
【0040】比較例として、上述の工程において、防食
処理を行わない半導体ウェハを作製し、同様に数時間〜
数日間、大気の下に放置した後、Si3 N4 膜を成膜し
た。As a comparative example, a semiconductor wafer which was not subjected to the anti-corrosion treatment in the above-mentioned process was manufactured, and the same process was performed for several hours.
After being left in the air for several days, a Si 3 N 4 film was formed.
【0041】本実施形態による製造の過程と、比較例の
ための製造の過程とにおいて、化学状態解析装置の一種
であるTOF−SIMS(Time of Fligh
t−Secondary Ion Mass Spec
troscopy)を用いて表面を観察し、酸化膜であ
るCuOおよび防食膜としてのCu−BTAの生成状態
を調べた。TOF−SIMSは、試料(半導体ウェハ
1)の表面に1次イオンをパルス状に照射して試料表面
から2次イオンを発生させ、この2次イオンの質量とイ
オン数を計数することで、試料表面の化学的結合を壊さ
ずに試料表面の化学的状態を解析する装置である。In the manufacturing process according to the present embodiment and the manufacturing process for the comparative example, TOF-SIMS (Time of Flight), which is a kind of chemical state analyzer, is used.
t-Secondary Ion Mass Spec
(troscopy), the surface was observed, and the generation state of CuO as an oxide film and Cu-BTA as an anticorrosion film was examined. The TOF-SIMS irradiates the surface of a sample (semiconductor wafer 1) with primary ions in a pulsed manner to generate secondary ions from the sample surface, and counts the mass and the number of the secondary ions to obtain a sample. This device analyzes the chemical state of the sample surface without breaking the chemical bonds on the surface.
【0042】Cu−BTA,CuOについては、スピン
リンス・乾燥工程26の後で、かつ、Si3 N4 成膜工
程28の前の状態のウェハを調べた。この結果を、図2
〜図4に示す。図2(A),(B)は、それぞれCu
O,図3は大気中に存在する有機物やイオン性物質、図
4はCu−BTAについてのTOF−SIMS測定結果
である。図2(A),図4において、縦軸は強度(イオ
ンカウント数を任意単位(AU)で表したもの)を、横
軸は質量数を示している。With respect to Cu-BTA and CuO, the wafer after the spin rinsing / drying step 26 and before the Si 3 N 4 film forming step 28 was examined. The result is shown in FIG.
4 to FIG. FIGS. 2A and 2B each show Cu
O, FIG. 3 shows TOF-SIMS measurement results for organic and ionic substances present in the atmosphere, and FIG. 4 shows the results of TOF-SIMS measurement for Cu-BTA. In FIGS. 2A and 4, the vertical axis represents intensity (the ion count number is expressed in arbitrary units (AU)), and the horizontal axis represents the mass number.
【0043】図2(A)は、スピンリンス・乾燥(図1
の工程26)した半導体ウェハ1を7日間大気中に放置
した後、TOF−SIMSによりCuO強度を測定した
ものである。図2(A)の測定結果からわかるように、
本発明により防食処理(BTA処理)した半導体ウェハ
は、CuOの形成が抑制されていることがわかる。ま
た、比較例(BTA処理なし)に示されるように、BT
Aが含まれるスラリーでCMPした半導体ウェハ1であ
っても、防食効果は少ないことがわかる。FIG. 2A shows a spin rinse / dry (FIG. 1)
After the semiconductor wafer 1 obtained in step 26) was left in the atmosphere for 7 days, the CuO strength was measured by TOF-SIMS. As can be seen from the measurement results of FIG.
It can be seen that the formation of CuO is suppressed in the semiconductor wafer subjected to the anticorrosion treatment (BTA treatment) according to the present invention. Further, as shown in the comparative example (without BTA processing), the BT
It can be seen that even the semiconductor wafer 1 CMPed with the slurry containing A has little anticorrosion effect.
【0044】図2(B)は、半導体ウェハ1をスピンリ
ンス・乾燥(図1の工程26)した後、大気中に放置し
た放置日数とCuO強度との関係を示すものである。図
2(B)に示すように、比較例(BTA処理なし)は、
放置日数の増加とともにCuO強度が増加し、Cuの酸
化が進行しやすいことが判る。これに対して、実施例
(BTA処理あり)は、放置日数が増加してもCuO強
度の増加が緩やかであり、Cuの酸化が進行しにくいこ
とが判る。FIG. 2B shows the relationship between the number of days that the semiconductor wafer 1 is left in the air after spin rinsing and drying (step 26 in FIG. 1) and the CuO strength. As shown in FIG. 2B, the comparative example (without BTA processing)
It can be seen that the CuO strength increases as the number of days of standing increases, and that the oxidation of Cu easily proceeds. On the other hand, in the example (with BTA treatment), the increase in the CuO strength is gradual even when the number of days of standing is increased, and it can be seen that the oxidation of Cu is difficult to proceed.
【0045】また、図3は、半導体ウェハ1をスピンリ
ンス・乾燥(図1の工程26)した後、大気中に放置し
た放置日数と有機物強度との関係を示すものである。こ
こで、有機物とはクリーンルーム内の大気中に浮遊して
いる物質であり、壁や製造装置の塗料、あるいは製造装
置の可動部分に付いている潤滑剤などから発生したもの
と推定される。FIG. 3 shows the relationship between the number of days that the semiconductor wafer 1 is left in the air after spin rinsing and drying (step 26 in FIG. 1) and the strength of organic substances. Here, the organic matter is a substance floating in the air in the clean room, and is presumed to be generated from a paint on a wall or a manufacturing apparatus, a lubricant attached to a movable portion of the manufacturing apparatus, or the like.
【0046】図3の比較例(BTA処理なし)に示され
るように、BTAが含有されるスラリーでCMPした半
導体ウェハ1であっても、有機物が付着しやすく、放置
日数の増加とともに有機物の付着量が大幅に増加するこ
とが判る。As shown in the comparative example (without BTA treatment) in FIG. 3, even in the semiconductor wafer 1 which has been subjected to CMP with the slurry containing BTA, the organic matter easily adheres, and as the number of days of standing increases, the organic matter adheres. It can be seen that the amount increases significantly.
【0047】これに対して、実施例(BTA処理あり)
は、放置日数が増加しても有機物強度の増加が緩やかで
あり、半導体ウェハ1の製造に有害な有機物やイオン性
汚染物の付着を大幅に抑制できることが判る。On the other hand, the embodiment (with BTA processing)
It can be seen that the increase in the strength of the organic substance is gradual even when the number of days of standing increases, and that the adhesion of organic substances and ionic contaminants harmful to the manufacture of the semiconductor wafer 1 can be significantly suppressed.
【0048】図4は、スピンリンス・乾燥(図1の工程
26)した半導体ウェハ1を7日間大気中に放置した
後、TOF−SIMSによりCu−BTA強度を測定し
たものである。FIG. 4 shows the result of measuring the Cu-BTA intensity by TOF-SIMS after leaving the semiconductor wafer 1 spin-rinsed and dried (step 26 in FIG. 1) in the air for 7 days.
【0049】図4の測定結果から明らかなように、防食
処理した半導体ウェハ1については、防食膜としてのC
u−BTAの存在が確認できた。また、比較例(BTA
処理なし)に示されるように、BTAが含まれるスラリ
ーでCMPした半導体ウェハ1であっても、Cu−BT
Aの残存量は少ないことが判る。さらに、図2の結果と
合わせると、CuOがCu表面に形成されていると、C
u−BTAが形成されにくいことが判る。As is clear from the measurement results of FIG. 4, the semiconductor wafer 1 subjected to the anticorrosion treatment has a C as an anticorrosion film.
The presence of u-BTA was confirmed. In addition, a comparative example (BTA
As shown in (No treatment), even if the semiconductor wafer 1 is CMP-processed with a slurry containing BTA, the Cu-BT
It turns out that the residual amount of A is small. Furthermore, when combined with the results of FIG. 2, when CuO is formed on the Cu surface, C
It turns out that u-BTA is hard to be formed.
【0050】次に、本実施形態により防食処理した半導
体ウェハと、比較例として作製した前述の半導体ウェハ
であって、スピンリンス・乾燥工程26を行った後、1
日放置後に、3日放置後に、7日放置後にSi3 N4 を
成膜したものについて、Cu/Si3 N4 界面の密着性
の試験を行った。この試験は、1mmピッチで桝目状に
ラインが入れられたSi3 N4 膜上に粘着テープを張り
付けてこれを引き剥がし、100個の桝目の中にウェハ
から剥がれたSi3 N4 膜の桝目の数を計数した。Next, the semiconductor wafer subjected to the anti-corrosion treatment according to the present embodiment and the above-described semiconductor wafer manufactured as a comparative example,
After standing for three days, after standing for three days, and after standing for seven days, a film of Si 3 N 4 was subjected to an adhesion test at the Cu / Si 3 N 4 interface. In this test, an adhesive tape was stuck on a Si 3 N 4 film in which lines were formed in a grid pattern at a pitch of 1 mm, and this was peeled off, and the cells of the Si 3 N 4 film peeled from the wafer in 100 cells Was counted.
【0051】試験結果を、表1に示す。これから明らか
なように、BTA処理なしのものについては、いずれの
ものについてもSi3 N4 膜の剥がれが生じ、スピンリ
ンス・乾燥工程26を行った後、大気中に放置してSi
3 N4 膜を成膜するまでの期間が長くなればなるほど、
剥がれ数が多くなり、Cu/Si3 N4 界面の密着性が
悪くなっていることがわかる。一方、BTA処理ありの
ものについては、7日放置後にSi3 N4 膜上を成膜し
たものであっても、Si3 N4 膜の剥がれはなく、Cu
/Si3 N4 膜の密着性が良好であることがわかる。Table 1 shows the test results. As is clear from the above, in any of the samples without the BTA treatment, peeling of the Si 3 N 4 film occurred, and after performing the spin rinsing / drying step 26, the Si 3 N 4 film was left in the air to stand.
3 N 4 film The longer the period until the formation of the,
It can be seen that the number of peeling increases and the adhesion at the Cu / Si 3 N 4 interface is deteriorated. On the other hand, those located BTA treatment, be those obtained by forming a Si 3 N 4 Makujo after standing 7 days, Si 3 N 4 film peeling not, Cu
It can be seen that the adhesion of the / Si 3 N 4 film is good.
【0052】[0052]
【表1】 [Table 1]
【0053】表2にBTA濃度とSi3 N4 膜の剥がれ
数との関係を示す。密着性試験の方法は、各濃度のBT
A水溶液に半導体ウェハ1を10秒間浸漬した後、上述
のように粘着テープにSi3 N4 膜が付着した桝目の数
を計数した。表2に示されるように、BTA濃度が1p
pm〜1%において、Si3 N4 膜の剥がれはなく、C
uとSi3 N4 膜との密着性が良好であることがわか
る。BTA濃度は1%以上でも同様な効果が得られる
が、BTAは水に対して2〜5%以上は溶解しない。Table 2 shows the relationship between the BTA concentration and the number of peeled Si 3 N 4 films. The method of the adhesion test is as follows.
After immersing the semiconductor wafer 1 in the aqueous solution A for 10 seconds, the number of cells where the Si 3 N 4 film adhered to the adhesive tape was counted as described above. As shown in Table 2, the BTA concentration was 1 p.
At pm to 1%, there was no peeling of the Si 3 N 4 film and C
It can be seen that the adhesion between u and the Si 3 N 4 film is good. The same effect can be obtained when the BTA concentration is 1% or more, but BTA does not dissolve in water at 2 to 5% or more.
【0054】[0054]
【表2】 [Table 2]
【0055】表3に、スピン洗浄(シュウ酸処理)24
と防食処理(BTA処理)25との工程有無と、Si3
N4 膜の剥がれ数との関係を試験した例を示す。試験に
使用した半導体ウェハ1は、スピンリンス・乾燥26を
行い、これを7日間大気中に放置した後にSi3 N4 膜
を成膜したものを使用した。Table 3 shows that the spin cleaning (oxalic acid treatment) 24
Process of anti-corrosion treatment (BTA treatment) 25 and Si 3
An example of testing the relationship between the number of peeling of N 4 film. The semiconductor wafer 1 used in the test was subjected to spin rinsing / drying 26, allowed to stand in the air for 7 days, and then formed with a Si 3 N 4 film.
【0056】[0056]
【表3】 [Table 3]
【0057】表3の試験結果から、金属汚染の除去(シ
ュウ酸処理)が行われていない半導体ウェハ1をBTA
処理しても、Si3 N4 膜の密着性は改善できない。ま
た、金属汚染の除去が行われた半導体ウェハ1であって
も、BTA処理しなければ、Si3 N4 膜の密着性は改
善できない。このように、防食処理25はCu表面が清
浄処理された状態、すなわち、CuOや金属汚染などを
除去した後で為されないと効果がないことが判る。From the test results shown in Table 3, the semiconductor wafer 1 on which metal contamination has not been removed (oxalic acid treatment) has been
The treatment cannot improve the adhesion of the Si 3 N 4 film. Further, even if the semiconductor wafer 1 has been subjected to metal contamination removal, the adhesion of the Si 3 N 4 film cannot be improved unless the BTA treatment is performed. Thus, it can be seen that the anti-corrosion treatment 25 has no effect unless it is performed after the Cu surface is cleaned, that is, after removing CuO and metal contamination.
【0058】また、他の防食剤として、酸化抑制効果の
あるガリック酸の1%水溶液をBTA水溶液の代わりに
用いて、半導体ウェハを作製し、大気中に1日,3日,
7日放置したものについて、Cu配線のシート抵抗を測
定した。比較のために、0.1%BTA水溶液,1%B
TA水溶液で防食処理したもの、防食処理をしなかった
ものについて、シート抵抗の変化率を測定した。As another anticorrosive, a 1% aqueous solution of gallic acid having an oxidation inhibiting effect was used in place of the BTA aqueous solution to prepare a semiconductor wafer, and the wafer was exposed to the air for 1 day, 3 days, and 3 days.
The sheet resistance of the Cu wiring was measured for those left for 7 days. For comparison, 0.1% BTA aqueous solution, 1% B
The rate of change of the sheet resistance was measured for those subjected to the anticorrosion treatment with the TA aqueous solution and those not subjected to the anticorrosion treatment.
【0059】測定結果を、図5に示す。未処理の半導体
ウェハについては、大気中に放置する時間が長くなるに
従ってCu配線のシート抵抗の変化が大きくなるが、B
TA水溶液およびガリック酸水溶液で防食処理した半導
体ウェハについては、シート抵抗の変化は小さかった。
このことから、BTA水溶液およびガリック酸水溶液は
いずれも、Cu配線の腐食を阻止し、シート抵抗の劣化
に効果があることがわかる。FIG. 5 shows the measurement results. As for the unprocessed semiconductor wafer, the change in the sheet resistance of the Cu wiring increases as the time in which the wafer is left in the air increases.
The change in sheet resistance of the semiconductor wafers subjected to the anticorrosion treatment with the TA aqueous solution and the gallic acid aqueous solution was small.
From this, it is understood that both the BTA aqueous solution and the gallic acid aqueous solution prevent corrosion of the Cu wiring and are effective in reducing the sheet resistance.
【0060】また、BTA水溶液およびガリック酸水溶
液で防食処理した半導体装置について、Si3 N4 膜成
膜、あるいはシリコン酸化膜などの層間膜成膜時に40
0℃で5分間の熱処理を行っても、ヒロックの発生は確
認されなかった。In the case of a semiconductor device which has been subjected to anticorrosion treatment with a BTA aqueous solution and a gallic acid aqueous solution, the formation of an Si 3 N 4 film or the formation of an interlayer film such as a silicon oxide film is reduced by 40%.
Even after a heat treatment at 0 ° C. for 5 minutes, generation of hillocks was not confirmed.
【0061】[0061]
【第2実施形態】図6は、本発明の第2の実施形態であ
る半導体装置の製造方法を示す工程図である。第1の実
施の形態と異なる点は、金属汚染を除去するスピン洗浄
の際に、シュウ酸水溶液にBTAを添加することによ
り、図1の防食処理工程25を省略したものである。図
6では、スピン洗浄(金属汚染防止処理+防食処理)工
程を30で示している。その他の工程で、図1と同じ工
程には、図1と同じ参照番号を付して示してある。Second Embodiment FIG. 6 is a process chart showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention. The difference from the first embodiment is that the anticorrosion treatment step 25 in FIG. 1 is omitted by adding BTA to the oxalic acid aqueous solution during spin cleaning for removing metal contamination. In FIG. 6, reference numeral 30 denotes a spin cleaning (metal contamination prevention process + corrosion prevention process). In other steps, the same steps as those in FIG. 1 are denoted by the same reference numerals as those in FIG.
【0062】工程30では、例えば、0.03%のシュ
ウ酸と、0.5%のBTAとを添加した水溶液を、半導
体ウェハを回転させながら吹きかけ、その後、工程26
でスピンリンスし、乾燥させた。ここで、シュウ酸はC
MPで半導体ウェハ1に付着した金属汚染物および表面
のCuO膜を除去する機能を有する。また、BTAは第
1の実施形態と同様、防食機能を有し、BTAだけでな
く、さらに本発明者らは、防食剤として、窒素2個の複
素四員環化合物、または窒素3個の複素五員環もしくは
六員環化合物、またはその誘導体のいずれか1種、また
はこれらの2種以上の混合物よりなる防食剤が有効であ
ることを確かめた。In step 30, for example, an aqueous solution containing 0.03% oxalic acid and 0.5% BTA is sprayed while rotating the semiconductor wafer.
And rinsed. Here, oxalic acid is C
It has a function of removing metal contaminants adhering to the semiconductor wafer 1 by MP and a CuO film on the surface. In addition, BTA has an anticorrosion function similarly to the first embodiment, and in addition to BTA, the present inventors furthermore, as an anticorrosion agent, a two-nitrogen four-membered ring compound or a three-nitrogen complex compound. It was confirmed that an anticorrosive composed of one of a five-membered or six-membered ring compound or a derivative thereof, or a mixture of two or more thereof was effective.
【0063】複素四員環化合物の一例は、インダゾール
である。One example of a heterocyclic four-membered ring compound is indazole.
【0064】窒素3個の複素五員環化合物はトリアゾー
ル系化合物であり、窒素3個の複素六員環化合物はトリ
アジン系化合物である。トリアゾール系化合物として
は、前述のベンゾトリアゾール以外に、o−トリルトリ
アゾール、m−トリルトリアゾール、p−トリルトリア
ゾール、カルボキシベンゾトリアゾール、1−ヒドロキ
シベンゾトリアゾール、ニトロベンゾトリアゾール、ジ
ヒドロキシプロピルベンゾトリアゾール等を挙げること
ができる。さらには、ベンゾトリアゾールの誘導体、例
えば、チバ・スペシャリティー・ケミカルズ社から市販
されているイルガメットシリーズ、具体的には、イルガ
メット42(2,2’−[[(メチル−1H−ベンゾト
リアゾール−1−イル)メチル]イミノ]ビス−エタノ
ール)等も好適に使用される。The five-membered heterocyclic compound having three nitrogen atoms is a triazole compound, and the six-membered heterocyclic compound having three nitrogen atoms is a triazine compound. Examples of the triazole-based compound include, in addition to the above-mentioned benzotriazole, o-tolyltriazole, m-tolyltriazole, p-tolyltriazole, carboxybenzotriazole, 1-hydroxybenzotriazole, nitrobenzotriazole, dihydroxypropylbenzotriazole, and the like. Can be. Furthermore, derivatives of benzotriazole, for example, Irgamet series commercially available from Ciba Specialty Chemicals, specifically Irgamet 42 (2,2 '-[[(methyl-1H-benzotriazole-1) -Yl) methyl] imino] bis-ethanol) and the like are also suitably used.
【0065】これら防食剤の添加率は、1ppm%以上
で効果を示すことが確認された。また、BTA等は環境
上の問題と溶解度から、最大の添加率は、5%とするの
が好ましい。It was confirmed that the effect was exhibited at an addition rate of these anticorrosives of 1 ppm% or more. The maximum addition ratio of BTA and the like is preferably set to 5% in view of environmental problems and solubility.
【0066】この他の防食剤としては、酸化抑制剤であ
る、芳香族ベンゼン環を有する化合物のガリック酸,タ
ンニン酸等も用いることができる。これらの添加率は、
BTAなどの防食剤と同様の考えで、0.01〜5%と
するのが好適である。As other anticorrosive agents, compounds having an aromatic benzene ring, such as gallic acid and tannic acid, which are oxidation inhibitors, can also be used. These addition rates are
It is preferable to set the content to 0.01 to 5% based on the same idea as the anticorrosive such as BTA.
【0067】本実施形態においても、第1の実施形態と
同様に、Cu配線の表面上に防食膜が形成されることが
確認された。また、本実施形態によれば、工程数を増や
すことなく、Cu/Cu拡散抑止絶縁膜の密着性を改善
することができる。In this embodiment, it was confirmed that an anticorrosion film was formed on the surface of the Cu wiring, as in the first embodiment. Further, according to the present embodiment, it is possible to improve the adhesion of the Cu / Cu diffusion suppression insulating film without increasing the number of steps.
【0068】[0068]
【発明の効果】以上説明したように本発明によれば、C
uまたはCu合金よりなるダマシン金属配線の表面上に
Cu拡散抑止絶縁膜を成膜した半導体装置において、金
属配線とCu拡散抑止絶縁膜との間の密着性を改善する
ことができ、また、金属配線表面にヒロックが発生しな
いので、信頼性の良い半導体装置を提供することが可能
となった。As described above, according to the present invention, C
In a semiconductor device in which a Cu diffusion inhibiting insulating film is formed on the surface of a damascene metal interconnect made of u or Cu alloy, the adhesion between the metal interconnect and the Cu diffusion inhibiting insulating film can be improved, and Since no hillocks are generated on the wiring surface, a highly reliable semiconductor device can be provided.
【0069】本発明に係る防食処理は、層間絶縁膜とし
て低誘電率(Low−K)膜を使用し、このLow−K
膜中にCu配線を形成する場合に重要となる。一般に、
Low−K膜は、SiO2 膜に比べて水分を含みやす
く、従来の方法ではこの水分がCu配線に影響を及ぼ
し、Cu配線が酸化されやすくなる。しかし、本願発明
の方法によれば、Cu配線とSi3 N4 膜との密着性が
高いので水分が進入しにくく、さらに、Cu配線表面が
防食処理されているので、水分が進入しても酸化が抑制
できる。The anticorrosion treatment according to the present invention uses a low dielectric constant (Low-K) film as an interlayer insulating film.
This is important when a Cu wiring is formed in the film. In general,
The Low-K film easily contains moisture as compared with the SiO 2 film, and in the conventional method, the moisture affects the Cu wiring, and the Cu wiring is easily oxidized. However, according to the method of the present invention, since the adhesion between the Cu wiring and the Si 3 N 4 film is high, it is difficult for moisture to enter. Further, since the Cu wiring surface is subjected to anticorrosion treatment, even if moisture enters, Oxidation can be suppressed.
【図1】本発明の第1の実施形態である半導体装置の製
造方法を示す工程図である。FIG. 1 is a process chart showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
【図2】CuOについてのTOF−SIMS測定結果を
示すグラフである。FIG. 2 is a graph showing the results of TOF-SIMS measurement of CuO.
【図3】有機物についてのTOF−SIMS測定結果を
示すグラフである。FIG. 3 is a graph showing a result of TOF-SIMS measurement for an organic substance.
【図4】Cu−BTAについてのTOF−SIMS測定
結果を示すグラフである。FIG. 4 is a graph showing TOF-SIMS measurement results for Cu-BTA.
【図5】シート抵抗の測定結果を示す図である。FIG. 5 is a diagram showing measurement results of sheet resistance.
【図6】本発明の第2の実施形態である半導体装置の製
造方法を示す工程図である。FIG. 6 is a process chart showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
【図7】ダマシンCu配線を作製する従来の半導体装置
の製造方法の工程を示す図である。FIG. 7 is a diagram showing steps of a conventional method of manufacturing a semiconductor device for producing a damascene Cu wiring.
【図8】製造工程における半導体ウェハの部分断面であ
る。FIG. 8 is a partial cross section of a semiconductor wafer in a manufacturing process.
10 半導体基板 12 絶縁膜 14 バリア膜 15 Cu膜 16 メッキCu 17 Cu配線 18 Si3 N4 膜 19 層間膜 20 Cu−CMP工程 22 スクラブ洗浄工程 24 スピン洗浄工程 26 スピンリンス・乾燥工程 28 成膜工程 29 層間膜成膜工程 30 (スピン洗浄+防食処理)工程Reference Signs List 10 semiconductor substrate 12 insulating film 14 barrier film 15 Cu film 16 plated Cu 17 Cu wiring 18 Si 3 N 4 film 19 interlayer film 20 Cu-CMP process 22 scrub cleaning process 24 spin cleaning process 26 spin rinsing / drying process 28 film forming process 29 Interlayer film formation process 30 (Spin cleaning + anticorrosion treatment) process
フロントページの続き Fターム(参考) 5F033 HH11 HH12 HH21 HH32 MM01 MM12 MM13 NN06 NN07 PP06 PP15 PP27 PP33 QQ37 QQ48 QQ91 RR04 RR06 RR08 SS11 SS15 XX16 XX18 XX20 Continued on the front page F term (reference) 5F033 HH11 HH12 HH21 HH32 MM01 MM12 MM13 NN06 NN07 PP06 PP15 PP27 PP33 QQ37 QQ48 QQ91 RR04 RR06 RR08 SS11 SS15 XX16 XX18 XX20
Claims (27)
面に銅拡散抑止絶縁膜を成膜する前に、防食剤を添加し
た水溶液で防食処理することを特徴とする半導体装置の
製造方法。1. A method for manufacturing a semiconductor device, comprising: performing a corrosion prevention treatment with an aqueous solution containing a corrosion inhibitor before forming a copper diffusion suppressing insulating film on a surface of a semiconductor substrate where copper or a copper alloy is exposed.
は、ダマシン法により銅または銅合金よりなる金属配線
が形成された半導体基板であることを特徴とする請求項
1記載の半導体装置の製造方法。2. The manufacturing method of a semiconductor device according to claim 1, wherein said semiconductor substrate having copper or copper alloy exposed thereon is a semiconductor substrate on which metal wiring made of copper or copper alloy is formed by a damascene method. Method.
P)した後の洗浄工程の間に、前記防食処理を行うこと
を特徴とする請求項1または2記載の半導体装置の製造
方法。3. The copper or copper alloy is subjected to chemical mechanical polishing (CM).
3. The method of manufacturing a semiconductor device according to claim 1, wherein the anticorrosion treatment is performed during a cleaning step after P).
浄液で処理した直後に行うことを特徴とする請求項1,
2または3のいずれかに記載の半導体装置の製造方法。4. The method according to claim 1, wherein the anticorrosion treatment is performed immediately after the treatment with a cleaning solution for removing metal contamination.
4. The method for manufacturing a semiconductor device according to any one of 2 and 3.
浄の際に、その洗浄液に防食剤を添加し、洗浄と同時に
行うことを特徴とする請求項1,2または3記載の半導
体装置の製造方法。5. The semiconductor device according to claim 1, wherein the anticorrosion treatment is performed simultaneously with the cleaning by adding an anticorrosive to the cleaning liquid during cleaning for removing metal contamination. Manufacturing method.
ことを特徴とする請求項4または5記載の半導体装置の
製造方法。6. The method according to claim 4, wherein the cleaning liquid is a carboxylic acid cleaning liquid.
物、または窒素3個の複素五員環もしくは六員環化合
物、またはその誘導体のいずれか1種、またはこれらの
2種以上の混合物よりなることを特徴とする請求項1〜
6のいずれかに記載の半導体装置の製造方法。7. The anticorrosion agent is a heterocyclic four-membered compound having two nitrogen atoms, a five- or six-membered heterocyclic compound having three nitrogen atoms, or a derivative thereof, or two or more of these compounds. A mixture of:
7. The method for manufacturing a semiconductor device according to any one of 6.
はその誘導体であることを特徴とする請求項7記載の半
導体装置の製造方法。8. The method according to claim 7, wherein said four-membered heterocyclic compound is indazole or a derivative thereof.
ール、o−トリルトリアゾール、m−トリルトリアゾー
ル、p−トリルトリアゾール、カルボキシベンゾトリア
ゾール、1−ヒドロキシベンゾトリアゾール、ニトロベ
ンゾトリアゾール、またはジヒドロキシプロピルベンゾ
トリアゾールであることを特徴とする請求項7記載の半
導体装置の製造方法。9. The five-membered heterocyclic compound is benzotriazole, o-tolyltriazole, m-tolyltriazole, p-tolyltriazole, carboxybenzotriazole, 1-hydroxybenzotriazole, nitrobenzotriazole, or dihydroxypropylbenzotriazole. 8. The method for manufacturing a semiconductor device according to claim 7, wherein
であることを特徴とする請求項1〜9のいずれかに記載
の半導体装置の製造方法。10. The addition rate of said anticorrosive is 1 ppm to 5%.
The method of manufacturing a semiconductor device according to claim 1, wherein:
る化合物、またはその誘導体のいずれか1種、またはこ
れらの2種以上の混合物よりなることを特徴とする請求
項1〜6のいずれかに記載の半導体装置の製造方法。11. The anticorrosive according to claim 1, wherein the anticorrosive comprises a compound having an aromatic benzene ring, a derivative thereof, or a mixture of two or more of them. 13. The method for manufacturing a semiconductor device according to item 5.
は、ガリック酸またはタンニン酸であることを特徴とす
る請求項11記載の半導体装置の製造方法。12. The method according to claim 11, wherein the compound having an aromatic benzene ring is gallic acid or tannic acid.
率は、0.01〜5%であることを特徴とする請求項1
2記載の半導体装置の製造方法。13. The method according to claim 1, wherein an addition ratio of said gallic acid or tannic acid is 0.01 to 5%.
3. The method for manufacturing a semiconductor device according to item 2.
たはSiONであることを特徴とする請求項1〜13の
いずれかに記載の半導体装置の製造方法。14. The method of manufacturing a semiconductor device according to claim 1, wherein said copper diffusion suppressing insulating film is made of Si 3 N 4 or SiON.
る半導体ウェハをダマシン法により製造する方法におい
て、 金属をCMP処理して、前記金属配線を形成する工程
と、 前記CMP処理の後に洗浄する間に、防食剤を添加した
水溶液で、前記金属配線の表面を、防食処理する工程
と、を含むことを特徴とする半導体ウェハの製造方法。15. A method for manufacturing a semiconductor wafer having metal wiring made of copper or a copper alloy by a damascene method, comprising: a step of forming a metal wiring by performing a CMP process on a metal; and a step of cleaning after the CMP processing. And a step of subjecting the surface of the metal wiring to anticorrosion treatment with an aqueous solution to which an anticorrosive agent has been added.
洗浄の直後に行うことを特徴とする請求項15記載の半
導体ウェハの製造方法。16. The method according to claim 15, wherein the anticorrosion treatment is performed immediately after cleaning for removing metal contamination.
洗浄の際に、その洗浄液に防食剤を添加し、洗浄と同時
に行うことを特徴とする請求項16記載の半導体ウェハ
の製造方法。17. The method of manufacturing a semiconductor wafer according to claim 16, wherein the anticorrosion treatment is performed simultaneously with the cleaning by adding an anticorrosive to the cleaning liquid during cleaning for removing metal contamination.
ることを特徴とする請求項17記載の半導体ウェハの製
造方法。18. The method according to claim 17, wherein the cleaning liquid is a carboxylic acid-based cleaning liquid.
物、または窒素3個の複素五員環もしくは六員環化合
物、またはその誘導体のいずれか1種、またはこれらの
2種以上の混合物よりなることを特徴とする請求項15
〜18のいずれかに記載の半導体ウェハの製造方法。19. The anticorrosive may be a four-membered ring compound having two nitrogen atoms, a five-membered or six-membered ring compound having three nitrogen atoms, or a derivative thereof, or a combination of two or more thereof. 16. A mixture comprising a mixture.
19. The method for manufacturing a semiconductor wafer according to any one of items 18 to 18.
その誘導体であることを特徴とする請求項19記載の半
導体ウェハの製造方法。20. The method according to claim 19, wherein the four-membered ring compound is indazole or a derivative thereof.
ゾール、o−トリルトリアゾール、m−トリルトリアゾ
ール、p−トリルトリアゾール、カルボキシベンゾトリ
アゾール、1−ヒドロキシベンゾトリアゾール、ニトロ
ベンゾトリアゾール、またはジヒドロキシプロピルベン
ゾトリアゾールであることを特徴とする請求項19記載
の半導体ウェハの製造方法。21. The five-membered heterocyclic compound is benzotriazole, o-tolyltriazole, m-tolyltriazole, p-tolyltriazole, carboxybenzotriazole, 1-hydroxybenzotriazole, nitrobenzotriazole, or dihydroxypropylbenzotriazole. 20. The method for manufacturing a semiconductor wafer according to claim 19, wherein
であることを特徴とする請求項15〜21のいずれかに
記載の半導体ウェハの製造方法。22. The addition rate of the anticorrosive is 1 ppm to 5%.
22. The method of manufacturing a semiconductor wafer according to claim 15, wherein:
る化合物、またはその誘導体のいずれか1種、またはこ
れらの2種以上の混合物よりなることを特徴とする請求
項15〜18のいずれかに記載の半導体ウェハの製造方
法。23. The anticorrosive according to claim 15, wherein the anticorrosive comprises a compound having an aromatic benzene ring, a derivative thereof, or a mixture of two or more of them. 3. The method for manufacturing a semiconductor wafer according to 1.
は、ガリック酸またはタンニン酸であることを特徴とす
る請求項23記載の半導体装置の製造方法。24. The method according to claim 23, wherein the compound having an aromatic benzene ring is gallic acid or tannic acid.
率は、0.01〜5%であることを特徴とする請求項2
4記載の半導体ウェハの製造方法。25. The method according to claim 2, wherein the addition ratio of said gallic acid or tannic acid is 0.01 to 5%.
5. The method for manufacturing a semiconductor wafer according to 4.
法により製造された半導体ウェハであって、 前記金属配線の表面に、銅と前記防食剤との化合物より
なる防食膜が形成されていることを特徴とする半導体ウ
ェハ。26. A semiconductor wafer manufactured by the method according to claim 15, wherein an anticorrosion film made of a compound of copper and the anticorrosive is formed on a surface of the metal wiring. A semiconductor wafer.
(BTA)の化合物である銅−BTAであることを特徴
とする請求項26記載の半導体ウェハ。27. The semiconductor wafer according to claim 26, wherein said compound is copper-BTA which is a compound of copper and benzotriazole (BTA).
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP32932499A JP3705724B2 (en) | 1999-11-19 | 1999-11-19 | Manufacturing method of semiconductor device |
US09/715,000 US6897150B1 (en) | 1999-11-19 | 2000-11-20 | Semiconductor wafer surface and method of treating a semiconductor wafer surface |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32932499A JP3705724B2 (en) | 1999-11-19 | 1999-11-19 | Manufacturing method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001148385A true JP2001148385A (en) | 2001-05-29 |
JP3705724B2 JP3705724B2 (en) | 2005-10-12 |
Family
ID=18220191
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JP32932499A Expired - Fee Related JP3705724B2 (en) | 1999-11-19 | 1999-11-19 | Manufacturing method of semiconductor device |
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US (1) | US6897150B1 (en) |
JP (1) | JP3705724B2 (en) |
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JP2002270561A (en) * | 2001-03-14 | 2002-09-20 | Ebara Corp | Method and apparatus for treating substrate |
WO2003079429A1 (en) * | 2002-03-15 | 2003-09-25 | Renesas Technology Corp. | Production method for semiconductor integrated circuit device |
JP2004182773A (en) * | 2002-11-29 | 2004-07-02 | Nec Electronics Corp | Liquid composition for cleaning hydrophobic substrate |
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US6274478B1 (en) * | 1999-07-13 | 2001-08-14 | Motorola, Inc. | Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process |
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KR20020068470A (en) * | 2001-02-21 | 2002-08-27 | 닛뽕덴끼 가부시끼가이샤 | Manufacturing method of semiconductor device |
JP2002270561A (en) * | 2001-03-14 | 2002-09-20 | Ebara Corp | Method and apparatus for treating substrate |
WO2003079429A1 (en) * | 2002-03-15 | 2003-09-25 | Renesas Technology Corp. | Production method for semiconductor integrated circuit device |
JP2004182773A (en) * | 2002-11-29 | 2004-07-02 | Nec Electronics Corp | Liquid composition for cleaning hydrophobic substrate |
JP2008166751A (en) * | 2006-12-08 | 2008-07-17 | Nec Electronics Corp | Method for manufacturing semiconductor device |
US8329584B2 (en) | 2006-12-08 | 2012-12-11 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
US8822396B2 (en) | 2007-08-22 | 2014-09-02 | Daikin Industries, Ltd. | Solution for removing residue after semiconductor dry process and method of removing the residue using the same |
US8187966B2 (en) | 2008-03-26 | 2012-05-29 | Renesas Electronics Corporation | Manufacturing method for semiconductor integrated circuit device |
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JP3705724B2 (en) | 2005-10-12 |
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