JP2003347299A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress or prevent stress migration defects of a semiconductor integrated circuit device having embedded wirings. <P>SOLUTION: Wiring grooves 16a are formed in insulating films 15a, 11b, 12b and 15b, and in the wiring grooves 16a, embedded second layer wirings L2 each having a conductive barrier film 17a and a main conductive film 18a containing copper as a main component by the CMP method. Subsequently, after cleaning and ammonia plasma treatment are performed, the CMP surface of a wafer 1W is exposed to an inorganic silane compound gas, such as mono- silane or the like, so as to subject a microvolume of silicon to a solid solution in the outer layer of the main conductive film 18a in the embedded second layer wirings L2. Then, an insulating film 15b of a wiring cap, which mainly contains a material having a smaller dielectric constant than silicon nitride, is deposited on the principal plane of the wafer 1W by CVD method using an organic silane compound gas as film-forming gas. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a method for manufacturing a semiconductor integrated circuit device using a conductor film containing copper as a main wiring material as a buried wiring. And effective technology.

[0002]

2. Description of the Related Art The buried wiring technology studied by the present inventors is, for example, as follows. First, after forming a wiring opening such as a wiring groove or a hole in an insulating film, a conductive barrier film and a conductive film containing copper as a main component are sequentially deposited from below on the insulating film including the inside of the wiring opening. . Subsequently, a buried wiring is formed in the wiring opening by polishing the excess conductive film and conductive barrier film containing copper as a main component by a chemical mechanical polishing method or the like. Thereafter, after performing a cleaning process, a wiring cap insulating film made of, for example, a silicon nitride film or the like is formed on the upper surface of the insulating film and the buried wiring.

[0003] For example, Japanese Patent Application Laid-Open No. 2001-160558.
In the publication, when forming an insulating film such as a silicon nitride film on copper, a pretreatment for improving the adhesion between copper and the insulating film is performed in an insulating film forming process chamber. There is disclosed a technique performed at a temperature lower than the film forming temperature. In addition, for example,
JP-A-01-77192 discloses a technique in which a silicon oxynitride film is used as a copper diffusion preventing layer and an etching stopper layer. Further, for example, Japanese Patent Application Laid-Open No. 9-3210
No. 45 discloses a technique of selectively forming a copper silicide layer only in a portion of a copper wiring where copper is exposed.
Further, for example, US Pat. No. 5,447,887 discloses a technique of forming a copper silicide layer on the surface of a copper wiring without performing plasma processing after forming the copper wiring. Further, for example, US Pat. No. 6,174,810, US Pat. No. 6,165,894, or JP-A-6-283520 describes ammonia plasma treatment of a semiconductor integrated circuit device having a copper wiring structure. Also, for example, Japanese Patent Application Laid-Open No. 2001-60584 discloses a technique in which an exposed surface of a carbon-containing material is treated with an oxygen-containing plasma such as helium, argon, or another inert gas plasma or nitric oxide plasma. .

[0004]

However, the inventor has found that the above-mentioned buried wiring technology has the following problems.

That is, there is a problem that stress migration failure occurs at the bottom of the through hole connecting the wiring layers. This problem is particularly conspicuous when the width of the lower wiring is wider than the width of the upper wiring.

An object of the present invention is to provide a technique capable of suppressing or preventing stress migration failure of a semiconductor integrated circuit device having a wiring in a wiring opening.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the present invention, a first atom for suppressing or preventing the diffusion of copper is dissolved in a surface layer of a wiring mainly composed of copper formed in a wiring opening and then formed as a film forming gas. The method includes a step of depositing an insulating film on the wiring by a chemical vapor deposition method using an organic silane compound gas.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the present embodiment in detail, the meanings of terms in the present embodiment will be described as follows.

1. TDDB (Time Dependence on Diele
The ctric breakdown life is a measure for objectively measuring the time dependency of dielectric breakdown, and is a predetermined temperature (for example, 14
0 ° C.), a relatively high voltage is applied between the electrodes under the measurement conditions
A graph in which the time from voltage application to dielectric breakdown is plotted against the applied electric field is created, and the time (life) obtained by extrapolating from this graph to the actual used electric field strength (for example, 0.2 MV / cm).

1 to 3 show an example of a sample used for TDDB life measurement according to the present embodiment. FIG. 1 is a plan view, and FIGS. 2 and 3 are cross-sectional views taken along the line BB 'in FIG. −
The cross sections along line C ′ are shown. This sample can actually be formed in the TEG (Test Equipment Group) region of the wafer. As shown in the figure, a pair of comb-shaped wirings L are connected to a second wiring layer M2.
And connected to the uppermost pads P1 and P2, respectively.
An electric field is applied between the comb-shaped wirings L, and a current is measured.
Pads P1 and P2 are measurement terminals. The wiring width, wiring interval, and wiring thickness of the comb-shaped wiring L are all 0.5 μm. The wiring facing length was 1.58 × 10 ⁵ μm.

FIG. 4 is an explanatory diagram showing an outline of the measurement. The sample is held on the measurement stage S, and the pads P1, P
A current / voltage measuring device (I / V measuring device) is connected between the two. The measurement stage S is heated by the heater H and the sample temperature is 140 ° C.
It is adjusted to. The TDDB life measurement includes a constant voltage stress method and a low current stress method. In this embodiment, the constant voltage stress method in which the average electric field applied to the insulating film is constant is used. After the voltage is applied, the current density decreases over time, and then a sharp increase in current (dielectric breakdown) is observed. Here, the leak current density is 1 μA / cm
^The time to reach ² was defined as the TDDB life (TDDB life at 5 MV / cm). In the present embodiment,
The TDDB life is 0.2 MV / c unless otherwise specified.
m means the breakdown time (lifetime), and in a broad sense, the TDDB
The term life may be used. Unless otherwise specified, the TDDB life refers to a case where the sample temperature is 140 ° C.
Further, the TDDB life refers to the case where the comb-shaped wiring L is measured, but it goes without saying that the TDDB life reflects the actual breakdown life between the wirings.

2. Plasma processing is a process in which the surface of a substrate or a member such as an insulating film or a metal film is formed on a substrate in an environment that is in a plasma state. It refers to the process of applying the chemical and mechanical (bombardment) action of plasma to the surface. Generally, plasma is a specific gas (processing gas)
The gas is generated by ionizing the gas by the action of a high-frequency electric field or the like while replenishing the processing chamber as necessary with the processing gas as needed. However, in reality, it cannot be completely replaced with the processing gas. Therefore, in the present embodiment, even if it is referred to as ammonia plasma, for example, it is not intended to be complete ammonia plasma, and the presence of impurity gas (nitrogen, oxygen, carbon dioxide, water vapor, etc.) contained in the plasma is excluded. It does not do. Similarly, it goes without saying that the inclusion of other diluent gas or additional gas in the plasma is not excluded.

3. Plasma in a reducing atmosphere is a reducing action, that is, a radical having an action of extracting oxygen,
It refers to a plasma environment in which reactive species such as ions, atoms, and molecules are predominantly present. Radicals and ions include atoms or molecular radicals or ions. Further, the environment may include not only a single reactive species but also a plurality of reactive species. For example, an environment in which hydrogen radicals and NH ₃ radicals are simultaneously present may be used.

4. In the present embodiment, for example, when expressed as being made of copper, it is intended that copper is used as a main component. That is, it is natural that even high-purity copper generally contains impurities, and it does not exclude that additives and impurities are also included in the member made of copper. This applies not only to copper but also to other metals (such as titanium nitride).

5. Chemical mechanical polishing (CMP: Chemical Mec)
In general, hanical polishing is a process in which a surface to be polished is brought into contact with a polishing pad made of a relatively soft cloth-like sheet material or the like, and is relatively moved in a surface direction while supplying a slurry to perform polishing. In the present embodiment, in addition, a CML (Chemical Mechanical) that performs polishing by relatively moving the surface to be polished with respect to the surface of a hard grindstone is used.
ical Lapping), those using other fixed abrasives, and abrasive-free CMP without the use of abrasives.

6. Abrasive-free chemical mechanical polishing generally has a weight concentration of abrasive grains of less than 0.5% by weight (more preferably, less than 0.5% by weight).
(1% by weight, more preferably less than 0.01% by weight) refers to chemical mechanical polishing using a slurry, and abrasive chemical mechanical polishing means that the weight concentration of abrasive grains is higher than 0.5% by weight. This refers to chemical mechanical polishing using a slurry. However, these are relative, and if the polishing in the first step is abrasive-free chemical mechanical polishing and the subsequent polishing in the second step is abrasive chemical mechanical polishing, the polishing concentration in the first step is Second
When the polishing concentration is lower by one digit or more, preferably by two digits or more than the polishing concentration in the step, the polishing in the first step may be called abrasive-free chemical mechanical polishing. In this specification, when the term "abrasive-free chemical mechanical polishing" is used, in addition to the case where the entire unit planarization process of the target metal film is performed by abrasive-free chemical mechanical polishing, the main process is abrasive-free chemical mechanical polishing. And a case where the secondary process is performed by abrasive chemical mechanical polishing.

[7] The polishing liquid (slurry) generally refers to a suspension in which abrasive grains are mixed with a chemical etching agent, and in the present application, due to the properties of the invention, those containing no abrasive grains are included.

8. The abrasive grains (slurry particles) generally refer to powders such as alumina and silica contained in the slurry.

9. An anticorrosion agent is an agent that prevents or suppresses the progress of polishing by CMP by forming a protective film having corrosion resistance and / or hydrophobicity on the surface of the metal, and is generally a benzotriazole (B
TA) or the like (for details, see JP-A-8-6459).
No. 4).

10. Scratch-free is the above CMP
A state in which no defect of a predetermined size or more is detected in the entire surface of the polished surface of the wafer polished by the method or in a predetermined unit area. Since the predetermined size varies depending on the generation and type of the semiconductor device, it cannot be unconditionally determined. However, in the present embodiment, in the in-line comparative defect inspection, for example, 0.3 μm
The above-mentioned defect is not detected.

11. In general, a conductive barrier film (or a conductive copper diffusion barrier film) is a diffusion film formed relatively thinly on the side surface or bottom surface of an embedded wiring in order to prevent copper from diffusing into or below an interlayer insulating film. A conductive film having a barrier property. Generally, titanium nitride (TiN), tantalum (T
a), a refractory metal such as tantalum nitride (TaN) or a nitride thereof is used.

12. Embedded wiring or embedded metal wiring is generally a conductive film inside a wiring opening such as a groove or a hole formed in an insulating film, such as a single damascene or a dual damascene. Embedded in the insulating film, and is a wiring patterned by a wiring forming technique for removing an unnecessary conductive film on the insulating film. In general, a single damascene is a plug metal,
This refers to an embedded wiring process of embedding in two stages with wiring metal. Similarly, dual damascene generally refers to an embedded wiring process in which plug metal and wiring metal are embedded at once. In general, copper embedded wiring is often used in a multilayer structure.

13. In this embodiment, a semiconductor integrated circuit device is not limited to a device formed on a single-crystal silicon substrate, but unless otherwise specified, a SOI (Silicon On Insulator) substrate or a TFT is used.
(Thin Film Transistor) Includes those made on other substrates such as substrates for manufacturing liquid crystals.

14. A wafer is a silicon or other semiconductor single crystal substrate (generally a generally disk-shaped or semiconductor wafer) used for manufacturing a semiconductor integrated circuit, a sapphire substrate, a glass substrate, other insulating, anti-insulating or semiconductor substrates, and a composite thereof. Say the substrate.

15. A semiconductor integrated circuit chip or a semiconductor chip (hereinafter, referred to as a chip) refers to a wafer obtained by completing a wafer process (wafer process or previous process) divided into unit circuit groups.

16. The term “silicon nitride, silicon nitride, or silicon nitride film” includes not only Si ₃ N ₄ but also an insulating film of silicon nitride having a similar composition.

Examples of the silicon nitride insulating barrier film (or insulating copper diffusion barrier film) include SiN (including SiNH), SiON, SiCN, and the like. These are silicon oxide based insulating films (normal silicon oxide film, plasma CV
D silicon oxide film, PSG, BPSG, inorganic SO
Insulating etching stop film (or insulating etching stopper) for etching of a G-based coating-based silicon oxide film, an organic SOG-based coating-based silicon oxide film, and a siloxane-based organic silica glass-based coating system or a CVD-based silicon oxide film) Film), that is, a silicon nitride-based insulating etching stopper film.

Further, an insulating barrier film (insulating etching stop film) having a lower dielectric constant than SiN, ie, Si ₃ N ₄ , that is, SiC, SiCN, SiON or the like is formed of a low dielectric insulating barrier film (low dielectric insulating film). Insulating etching stop film).

17. A low dielectric constant insulating film (Low-K insulating film) is a silicon oxide film (for example, TEOS (Tetraethoxysilane) oxide film) included in a passivation film.
An insulating film having a dielectric constant lower than that of the above. Generally, the relative dielectric constant ε of the TEOS oxide film is 4.1.
About 4.2 or less (in a narrow sense, relative permittivity ε = 3.0 or less,
(2.7 or less in a narrow sense) is called a low dielectric constant insulating film.

In the following embodiments, for the sake of convenience, the description will be made by dividing into a plurality of sections or embodiments, but they are not irrelevant to each other, unless otherwise specified. One has a relationship of some or all of the other, the details, the supplementary explanation, and the like.

In the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), the number is particularly limited, and is limited to a specific number in principle. Except for cases, the number is not limited to the specific number, and may be more than or less than the specific number.

Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential unless otherwise specified and in cases considered to be essential in principle. Needless to say, there is nothing.

Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of the constituent elements, etc., unless otherwise specified, and unless otherwise apparently in principle, it is substantially the same. And those similar or similar to the shape or the like. This is the same for the above numerical values and ranges.

In all the drawings for describing the present embodiment, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

In the drawings used in the present embodiment, hatching may be used even in a plan view so as to make the drawings easy to see.

Further, in the present embodiment, a MIS • FET (Metal Insula
tor Semiconductor Field Effect Transistor)
S is abbreviated, p-channel MIS • FET is abbreviated as pMIS, and n-channel MIS • FET is abbreviated as nMIS.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1) First, the problems studied by the present inventors will be described. At present, stress migration (hereinafter referred to as S
M). According to the study of the present inventors, the problem of SM is remarkable in the wiring structure as shown in FIGS. FIG. 33 shows a case where the width of the embedded wiring 50 in the lower layer is wider than the width of the embedded wiring 51 in the upper layer. The upper and lower embedded wirings 50 and 51 are electrically connected through through holes 52. FIG. 34 shows the embedded wiring 5 of the upper and lower layers.
This is the case where the widths of 0 and 53 are almost equal. The common feature is that the embedded wiring 50 in the lower layer to which the through hole 52 is connected is connected.
Is large (for example, about 4 μm or more), and in each case, a void 54 due to SM is generated at the bottom of the through hole 52 as shown in FIG. FIG. 36 shows that the void 54 is likely to be generated in the wide buried wiring 50.
As shown in (1), in the case of the wide buried wiring 50, the reason is that the triple point 55 in which voids, impurities and the like are concentrated tends to be formed. Further, the void 54 is easily formed at the bottom of the through hole 52 because the through hole 52 is arranged at the center in the width direction of the embedded wiring 50 where stress is easily concentrated, and the upper part of the wiring is etched when the through hole 52 is formed. And that it is a portion where different metals (conductive barrier films) come into contact. The generation of voids due to such SM causes an increase in resistivity at the through-hole 52. Since the diameter of the through-hole 52 tends to become smaller and smaller, the generation of a small void causes a large increase in the resistivity, leading to a reduction in the yield, reliability and performance of the semiconductor integrated circuit device.

Therefore, the present inventor has investigated the cause of the generation of voids due to SM, and has found that the generation of voids is caused by the diffusion phenomenon of copper oxide, copper and oxygen in the buried wiring surface layer. In particular, in the formation of the embedded wiring by the damascene process, the cause of void generation by the SM has the following reasons in the process. That is, the embedded wiring is subjected to chemical mechanical polishing (CM).
The organic acid used in the post-CMP cleaning after the formation by the P) method is as follows:
Since the copper film itself is not etched much, the surface of the copper film is in a state of much copper oxide (CuO). Also, CM
The hydrogen annealing after P is performed at a high temperature for a long time (for example, 300 to
At 400 ° C. for 2 to 120 minutes), deterioration due to SM occurs, so it is necessary to perform at a low temperature (for example, 200 ° C. or lower), and the above copper oxide cannot be sufficiently reduced. In addition, this copper oxide is not easily reduced even if it is subjected to an ammonia (NH ₃ ) plasma treatment which is optimized from the viewpoint of TDDB life and hillocks. Therefore, at present, an insulating film for a wiring cap is deposited without reducing the copper oxide film, and as a result, the copper oxide is taken into the copper wiring. It is known that this copper oxide film is generally unstable electrically and thermally and is easily diffused.
Affects life. Moreover, as described above, there are restrictions on the hydrogen annealing conditions and the ammonia plasma conditions,
Sufficient treatment cannot be performed to reduce copper oxide. Therefore,
In the first embodiment, the stabilization of the SM was attempted by devising the set flow (degassing process until the raw material gas used for film formation is stabilized) before the deposition of the wiring cap insulating film.

Next, a specific example of the method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS. 6 to 17 along the manufacturing flow of FIG. FIG. 5 shows a manufacturing flowchart of the semiconductor integrated circuit device according to the first embodiment. A broken line SA in FIG. 5 indicates a process in the same processing chamber.

First, FIG. 6 is a plan view of a main part of a semiconductor integrated circuit device according to the first embodiment during a manufacturing process, and FIG. 7 is a sectional view taken along line X1-X1 of FIG. The semiconductor substrate (hereinafter, referred to as a substrate) 1S constituting the wafer 1W is, for example, 1 to
It is made of p-type single crystal silicon having a specific resistance of about 10 Ωcm. On the main surface (device formation surface) of the substrate 1S, a groove-shaped separation portion (Shallow Groove Isolation (SGI) or Shallow Trench Isolation (STI)) 2 is formed. The groove-shaped separation portion 2 is formed by, for example, burying a silicon oxide film in a groove formed on the main surface of the substrate 1S. On the main surface side of the substrate 1S, a p-type well PWL and an n-type well NWL are formed. For example, boron is introduced into the p-type well PWL,
For example, phosphorus is introduced into the n-type well NWL.
NMISQn and pMISQp are formed in the active regions of the p-type well PWL and the n-type well NWL surrounded by the isolation part 2.

The gate insulating films 3 of the nMISQn and the pMISQp are made of, for example, a silicon oxide film having a thickness of about 6 nm. The thickness of the gate insulating film 3 here is a thickness equivalent to silicon dioxide (hereinafter referred to as a reduced thickness), and may not coincide with an actual thickness. The gate insulating film 3
Instead of the silicon oxide film, a silicon oxynitride film may be used. That is, a structure in which nitrogen is segregated at the interface between the gate insulating film 3 and the substrate 1S may be adopted. Since the silicon oxynitride film has a higher effect of suppressing the generation of interface states and reducing electron traps in the film than the silicon oxide film, the hot carrier resistance of the gate insulating film 3 can be improved, Resistance can be improved. In addition, since the silicon oxynitride film does not easily penetrate impurities as compared with the silicon oxide film, the use of the silicon oxynitride film allows the threshold in the gate electrode material due to the diffusion of impurities into the substrate 1S side. Voltage fluctuation can be suppressed.
In order to form a silicon oxynitride film, for example, the wafer 1W may be heat-treated in a nitrogen-containing gas atmosphere such as NO, NO ₂ or NH ₃ . After the gate insulating film 3 made of silicon oxide is formed on each surface of the p-type well PWL and the n-type well NWL, the wafer 1W is heat-treated in the above-mentioned nitrogen-containing gas atmosphere, and the gate insulating film 3 and the substrate 1
The same effect as described above can be obtained by segregating nitrogen at the interface with S.

The gate insulating film 3 may be formed of, for example, a silicon nitride film or a composite insulating film of a silicon oxide film and a silicon nitride film. If the thickness of the gate insulating film 3 made of a silicon oxide film is reduced to less than 5 nm, particularly less than 3 nm in terms of silicon dioxide, a decrease in dielectric breakdown voltage due to generation of direct tunnel current or hot carriers due to stress becomes apparent. Since the silicon nitride film has a higher dielectric constant than the silicon oxide film, its reduced thickness is smaller than the actual thickness. That is, when a silicon nitride film is provided, a capacity equivalent to a relatively thin silicon dioxide film can be obtained even if it is physically thick. Therefore,
Since the gate insulating film 3 is composed of a single silicon nitride film or a composite film of the silicon nitride film and the silicon oxide film, the effective film thickness can be made larger than that of the gate insulating film composed of the silicon oxide film. In addition, it is possible to improve the occurrence of a tunnel leakage current and a decrease in dielectric breakdown voltage due to hot carriers.

The gate electrodes 4 of the nMISQn and the pMISQp are formed by stacking, for example, a titanium silicide (TiSi _x ) layer or a cobalt silicide (CoSi _x ) layer on a low-resistance polycrystalline silicon film, for example. However, the gate electrode structure is not limited to this, and is, for example, a so-called polymetal gate structure composed of a laminated film of a low-resistance polycrystalline silicon film, a WN (tungsten nitride) film, and a W (tungsten) film. Is also good. A side wall 5 made of, for example, silicon oxide is formed on a side surface of the gate electrode 4.

The semiconductor regions 6 for the source and drain of nMISQn is, n adjacent channels ^- -type semiconductor region, n ^- is connected to the semiconductor region, and, n ^- a position separated from the semiconductor region amount corresponding channel And an n ⁺ -type semiconductor region provided. n ⁻ type semiconductor region and n ⁺
For example, phosphorus or arsenic is introduced into the type semiconductor region. On the other hand, the semiconductor regions 7 for the source and drain of pMISQp is, p is adjacent to the channel ^- -type semiconductor region, p ^- is connected to the semiconductor region, and, p ^- provided in a position away from the semiconductor region amount corresponding channel P ⁺ type semiconductor region. p ^- type semiconductor region and p ⁺
For example, boron is introduced into the type semiconductor region. A silicide layer such as a titanium silicide layer or a cobalt silicide layer is formed on a part of the upper surfaces of the semiconductor regions 6 and 7, for example.

An insulating film 8 is deposited on the main surface of the substrate 1S of such a wafer 1W. The insulating film 8 is a film having a high reflow property capable of filling a narrow space between the adjacent gate electrodes 4 and 4, for example, a BPSG (Boron-doped).
Phospho Silicate Glass) film. Further, it may be constituted by an SOG (Spin On Glass) film formed by a spin coating method. A contact hole 9 is formed in the insulating film 8. Part of the upper surface of the semiconductor regions 6 and 7 is exposed from the bottom of the contact hole 9. A plug 10 is formed in the contact hole 9. The plug 10 is formed, for example, by depositing a titanium nitride (TiN) film and a tungsten (W) film on the insulating film 8 including the inside of the contact hole 9 by a CVD method or the like, and then removing the unnecessary titanium nitride film and tungsten on the insulating film 8. The film is formed by removing the films by the CMP method or the etch-back method and leaving these films only in the contact holes 9.

On the insulating film 8, a first layer wiring L1 made of, for example, tungsten is formed. First layer wiring L1
Are nMISQn and pMISQ through the plug 10
It is electrically connected to the source and drain semiconductor regions 6 and 7 and the gate electrode 4. The material of the first layer wiring L1 is not limited to tungsten, and can be variously changed. For example, at least one of a single metal film such as aluminum (Al) or an aluminum alloy or an upper and lower layer of these single metal films is made of titanium ( It may be a laminated metal film on which a metal film such as Ti) or titanium nitride (TiN) is formed.

Further, an insulating film 11a is deposited on the insulating film 8 so as to cover the first layer wiring L1. Insulating film 1
1a is made of a low dielectric constant material (a so-called Low-K material) such as an organic polymer or an organic silica glass. Examples of the organic polymer (completely organic low dielectric interlayer insulating film) include SiLK (The Dow Chemical Co., USA)
Dielectric constant = 2.7, heat-resistant temperature = 490 ° C. or higher, dielectric breakdown voltage = 4.0-5.0 MV / Vm) or polyallyl ether (PAE) based material FLARE (Honeywel, USA)
l Electronic materials, relative permittivity = 2.8, heat-resistant temperature = 400 ° C or higher). This PAE-based material is characterized by high basic performance and excellent mechanical strength, thermal stability and low cost. As the organic silica glass (SiOC-based material), for example, HSG-R7
(Hitachi Chemical Industries, relative permittivity = 2.8, heat resistant temperature = 65
0 ° C), Black Diamond (Applied Mater, USA)
ials, Inc., relative permittivity = 3.0-2.4, heat resistant temperature =
450 ° C.) or p-MTES (manufactured by Hitachi, relative permittivity = 3.2). As other SiOC-based materials, for example, CORAL (manufactured by Novellus Systems, Inc. of the United States, relative permittivity = 2.7 to 2.4, heat-resistant temperature = 500 ° C.), Au
Rora 2.7 (manufactured by ASM Japan Co., Ltd., relative dielectric constant = 2.7, heat-resistant temperature = 450 ° C.) and the like.

The low dielectric constant material of the insulating film 11a is, for example, a completely organic SiOF material such as FSG, HSQ (hydrogen silsesquioxane) material, MS
Q (methyl silsesquioxane) material, porous HSQ
A system material, a porous MSQ material, or a porous organic material can also be used.

As the HSQ-based material, for example, OCD
T-12 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 3.4-2.
9. Heat resistant temperature = 450 ° C), FOx (US Dow Corning Co.)
rp. Made, relative permittivity = 2.9) or OCL T-32
(Tokyo Ohka Kogyo Co., Ltd., dielectric constant = 2.5, heat-resistant temperature = 45
0 ° C.).

As the MSQ-based material, for example, OCD
T-9 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative permittivity = 2.7, heat-resistant temperature = 600 ° C.), LKD-T200 (manufactured by JSR, relative permittivity = 2.7-2.5, heat-resistant temperature = 450 ° C.), HOSP
(Honeywell Electronic Materials, USA, dielectric constant =
2.5, heat-resistant temperature = 550 ° C), HSG-RZ25 (manufactured by Hitachi Chemical, relative permittivity = 2.5, heat-resistant temperature = 650)
° C), OCL T-31 (manufactured by Tokyo Ohka Kogyo, relative permittivity =
2.3, heat-resistant temperature = 500 ° C) or LKD-T400
(Manufactured by JSR, relative permittivity = 2.2-2, heat resistant temperature = 450
° C).

As the porous HSQ-based material, for example, XLK (manufactured by Dow Corning Corp., US; relative dielectric constant = 2.5)
2), OCL T-72 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.2-1.9, heat-resistant temperature = 450 ° C.), Nanog
glass (Honeywell Electronic Materials, USA, relative dielectric constant = 2.2-1.8, heat-resistant temperature = 500 ° C. or more) or MesoELK (Air Products and Chemicals, USA)
c, relative permittivity = 2 or less).

As the porous MSQ material, for example, HSG-6221X (manufactured by Hitachi Chemical Co., Ltd., relative permittivity =
2.4, heat-resistant temperature = 650 ° C), ALCAP-S (manufactured by Asahi Kasei Corporation, relative permittivity = 2.3 to 1.8, heat-resistant temperature = 45)
OCL T-77 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.2-1.9, heat resistant temperature = 600 ° C.), HSG-6
210X (manufactured by Hitachi Chemical Co., Ltd., relative permittivity = 2.1, heat-resistant temperature = 650 ° C.) or silica aerogel
(Manufactured by Kobe Steel, relative permittivity of 1.4 to 1.1).

Examples of the porous organic materials include PolyELK (Air Products and Chemicals, Inc., USA)
(Dielectric constant = 2 or less, heat resistant temperature = 490 ° C.).

Further, an organic silicon glass film such as silicon oxynitride (SiON) may be used as another material of the insulating film 11a.

The above-mentioned SiOC-based material and SiOF-based material are as follows:
For example, it is formed by a CVD method (Chemical Vapor Deposition). For example, the above Black Diamond
nd is formed by a CVD method or the like using a mixed gas of trimethylsilane and oxygen. In addition, the above p-MTE
S is formed by, for example, a CVD method using a mixed gas of methyltriethoxysilane and N ₂ O. The other low dielectric constant insulating materials are formed by, for example, a coating method.

On the insulating film 11a made of such a Low-K material, a Low-K cap insulating film 12a is deposited. This insulating film 12a is made of silicon oxide (Si) typified by, for example, silicon dioxide (SiO ₂ ).
_Ox ) film, for example, a chemical mechanical polishing process (CMP; C
Insulating film 11 during chemical mechanical polishing
It has functions such as ensuring mechanical strength, surface protection and moisture resistance of a. The thickness of the insulating film 12a is relatively thinner than the insulating film 11a, for example, 25 nm to 10 nm.
It is about 0 nm, preferably about 50 nm, for example.
However, the insulating film 12a is can be variously modified without being limited to the silicon oxide film, for example, silicon nitride (Si _x N _y) film, a silicon carbide (SiC) film or a silicon carbonitride (SiCN) films using May be. These silicon nitride film, silicon carbide film or silicon carbonitride film can be formed by, for example, a plasma CVD method. As the silicon carbide film formed by the plasma CVD method, for example, BLOk (manufactured by AMAT, relative permittivity =
4.3). In the formation, for example, a mixed gas of trimethylsilane and helium (or N ₂ , NH ₃ ) is used. The insulating films 11a and 12a have the first
A through hole 13 exposing a part of the layer wiring L1 is formed. A plug 14 made of, for example, tungsten or the like is embedded in the through hole 13.

First, in the first embodiment, an insulating film (first insulating film) is formed on the insulating film 12a and the plug 14.
15a is deposited by a plasma CVD method or the like. The insulating film 15a is made of a Low-K material such as silicon carbonitride (SiCN), and has a thickness of, for example, 2.
It is about 5 nm to 50 nm, preferably about 50 nm, for example. The insulating film 15a of the case, for example, trimethylsilane; using a mixed gas of _{(3MS Si (CH 3) 3H} ) and ammonia (NH ₃₎ as a carrier gas (helium (He) or nitrogen (N ₂₎₎ Plasma It was formed by a CVD method. Further, as another material of the insulating film 15a, for example, silicon carbide (SiC) or silicon oxynitride (SiON) may be used. When the insulating film 15a is made of silicon carbide, for example, a plasma CV using a mixed gas of trimethylsilane and a carrier gas (helium) is used.
Formed by Method D. When the insulating film 15a is made of silicon oxynitride, for example, trimethoxysilane (TM)
S; formed by a plasma CVD method using a mixed gas of SiH (OCH ₃ ) ₃ ) and nitrogen oxide (N ₂ O). As silicon oxynitride, for example, PE-TMS (Canon
And dielectric constant = 3.9). Generally, the insulating film 15a
Is formed of a silicon nitride film or the like. In the first embodiment, the dielectric constant can be significantly reduced by using silicon carbonitride, silicon carbide, silicon oxynitride, or the like. The operating speed of the semiconductor integrated circuit device can be improved.

Subsequently, the insulating film 11 is formed on the insulating film 15a.
b and 12b are sequentially deposited from the lower layer. The insulating film 11b
It is made of the same low dielectric constant insulating film as the insulating film 11a. The upper insulating film 12b is made of the same insulating film as the insulating film 12a, and functions as an insulating film for the same Low-K cap. Thereafter, the insulating films 11b and 12b are formed by dry etching using a photoresist film as a mask.
Is selectively removed to form a wiring groove (wiring opening) 16a (step 100 in FIG. 5). In order to form the wiring groove 16a, the insulating films 11b and 12 exposed from the photoresist film are formed.
When removing b, the insulating films 11b and 12b and the insulating film 1
By increasing the etching selectivity with respect to 5a, the insulating film 15a functions as an etching stopper. That is, after the etching is temporarily stopped on the surface of the insulating film 15a, the insulating film 15a is selectively etched away.
Thus, the accuracy of the formation depth of the wiring groove 16a can be improved, and excessive digging of the wiring groove 16a can be prevented. Such a wiring groove 16a has, for example, a band shape as shown in FIG. The upper surface of the plug 14 is exposed from the bottom surface of the wiring groove 16a. FIG. 6 illustrates a case where the rightmost wiring groove 16a is wider than the other wiring grooves 16a.

FIG. 8 is a sectional view of a portion corresponding to the line X1-X1 in FIG. 6 during the manufacturing process of the semiconductor integrated circuit device following FIG. FIG. 9 is a cross-sectional view of the semiconductor integrated circuit device taken along the line X1 in FIG.
It is sectional drawing of the part corresponding to -X1 line.

First, as shown in FIG. 8, a thin conductive barrier film (first conductive film) made of, for example, titanium nitride (TiN) having a thickness of about 50 nm is formed on the entire main surface of the wafer 1W.
17a is deposited by a sputtering method or the like (step 1 in FIG. 5).
01). The conductive barrier film 17a has, for example, a function of preventing diffusion of copper for forming a main conductor film described later, a function of improving adhesion between the main conductor film and the insulating films 11b, 12a, 12b, 15a, and a function of the main conductor film. It has a function of improving the wettability of copper when the film is reflowed. As such a conductive barrier film 17a, it is preferable to use a high melting point metal nitride such as tungsten nitride (WN) or tantalum nitride (TaN), which hardly reacts with copper, instead of titanium nitride. In addition, instead of the titanium nitride, a material obtained by adding silicon (Si) to a refractory metal nitride,
A high melting point metal such as tantalum (Ta), titanium (Ti), tungsten (W), titanium tungsten (TiW) alloy, or the like, which does not easily react with copper can be used. According to the first embodiment, good TDDB characteristics can be obtained even when the thickness of the conductive barrier film 17a is, for example, 10 nm, which is smaller than 6 to 7 nm, or 5 nm or less.

Subsequently, a main conductor film (second conductor film) 18a made of copper and having a relatively large thickness of, for example, about 800 to 1600 nm is deposited on the conductive barrier film 17a (step 102 in FIG. 5). In the first embodiment, the main conductor film 18a
Was formed by, for example, a plating method. By using the plating method, the main conductor film 18a having good film quality can be formed with good embedding property and at low cost. In this case, first, a thin conductor film made of copper is deposited on the conductive barrier film 17a by a sputtering method, and then a relatively thick conductor film made of copper is formed thereon by, for example, an electrolytic plating method or an electroless plating method. The main conductor film 18a was deposited by growing by a method. In this plating process, for example, a plating solution based on copper sulfate was used. However, the main conductor film 18a can also be formed by a sputtering method.
As a sputtering method for forming the conductive barrier film 17a and the main conductor film 18a, a normal sputtering method may be used. It is preferable to use a sputtering method having a high directivity as described above. Also, the main conductor film 18
a can also be formed by a CVD method. Thereafter, the main conductor film 18a is reflowed by subjecting the substrate 1S to a heat treatment in a non-oxidizing atmosphere (for example, a hydrogen atmosphere) at, for example, about 475 ° C., and copper is buried without gaps in the wiring grooves 16a.

Next, the main conductor film 18a and the conductive barrier film 17a are polished by the CMP method (Step 10 in FIG. 5).
3). In the first embodiment, as the CMP method, for example, a two-step CMP method of the above-mentioned abrasive-free CMP (first step) and abrasive-grained CMP (second step) is used. That is, for example, as follows.

First, the first step aims at selectively polishing the main conductor film 18a made of copper. The polishing liquid (slurry) contains an anticorrosive for forming a protective film, an oxidizing agent for copper, and a component for etching a copper oxide film, but does not contain abrasive grains. The content of the abrasive grains in the polishing liquid is, for example, preferably 0.5% by weight or less or 0.1% by weight or less, particularly preferably 0.05% by weight or less or 0.1% by weight or less.
Those having a content of 01% by weight or less are more preferred. However, abrasive grains may be contained in an amount of about 3 to 4% of the entire abrasive. As the polishing liquid, a polishing liquid whose pH is adjusted so as to belong to a corrosive region of copper is used, and the polishing selection ratio of the main conductor film 18a to the conductive barrier film 17a is, for example, at least 5
A composition whose composition is adjusted as described above is used. As such a polishing liquid, a slurry containing an oxidizing agent and an organic acid can be exemplified. Examples of the oxidizing agent include hydrogen peroxide (H ₂ O ₂ ), ammonium hydroxide, ammonium nitrate, and ammonium chloride.
Examples of the organic acid include citric acid, malonic acid, fumaric acid, malic acid, adipic acid, benzoic acid, phthalic acid, tartaric acid, lactic acid, succinic acid, and oxalic acid.
Of these, hydrogen peroxide does not contain metal components and is not a strong acid, so it is a suitable oxidizing agent for use in polishing liquids.
In addition, citric acid is also commonly used as a food additive, has low toxicity, has low harm as a waste liquid, has no odor, and has high solubility in water, so it is a suitable organic acid for use in a polishing liquid. . In this embodiment, for example, 5% by volume in pure water
Of hydrogen peroxide and 0.03% by weight of citric acid to reduce the content of abrasive grains to less than 0.01% by weight. As the anticorrosion agent, for example, BTA is used.

In the abrasive grain-free CMP of the first step, the main conductor film 18a is mainly polished with a chemical element while producing both the protection effect and the etching effect of the main conductor film 18a. That is, when the chemical mechanical polishing is performed with the polishing liquid, the copper surface is first oxidized by the oxidizing agent, and a thin oxide layer is formed on the surface. Next, when a substance for making the oxide water-soluble is supplied, the oxide layer is eluted as an aqueous solution, and the thickness of the oxide layer is reduced. The portion where the oxide layer has become thinner is again exposed to an oxidizing substance to increase the thickness of the oxide layer. This reaction is repeated, and chemical mechanical polishing proceeds. The removal of the protective film is mainly performed by contact with the polishing pad.

The polishing conditions are, for example, a load = 250 g.
/ cm ² , wafer carrier rotation speed = 30 rpm, surface plate rotation speed =
The polishing pad was, for example, a hard pad (Rodel, USA) (IC: 25 rpm, slurry flow rate = 150 cc / min).
1400) was used. This polishing pad employs a hard pad from the viewpoint of improving flatness, but may use a soft pad. The end point of the polishing is a point in time when the main conductive film 18a is removed and the underlying conductive barrier film 17a is exposed,
The end point is detected by detecting the rotational torque signal intensity of the surface plate or the wafer carrier that changes when the polishing target changes from the main conductor film 18a to the conductive barrier film 17a. Also, a hole is made in a part of the polishing pad, and the wafer 1W
The end point may be detected based on the change in the light reflection spectrum from the surface, or the end point may be detected based on the change in the optical spectrum of the slurry.

In such a polishing process, the polishing rate of the main conductor film 18a made of copper is, for example, 500 nm / mi.
n, the polishing rate of the conductive barrier film 18a is, for example, 3
It is about nm / min. The polishing time depends on the main conductor film 18a.
Although it cannot be said unconditionally because it differs depending on the film thickness of, for example, the above film thickness is about 2 to 4 minutes.

The subsequent second step is to form the conductive barrier film 17.
It is intended to selectively polish a. This second
In the step, the conductive barrier film 17a is polished mainly by mechanical elements by contact with a polishing pad. Here, abrasive grains are contained in addition to the corrosion inhibitor, the oxidizing agent, and the component for etching the oxide film as a polishing liquid. In the first embodiment, for example, 5% by volume of hydrogen peroxide, 0.03% by weight of citric acid, and 0.5 to
A mixture of 0.8% by weight of abrasive grains is used, but is not limited thereto. The added amount of the abrasive grains is set to an amount that does not mainly remove the underlying insulating film 12b, and the amount is, for example, 1% by weight or less. As the abrasive, for example, colloidal silica (Si
O ₂ ) is used. By using colloidal silica as the abrasive, the insulating film 12 formed by the CMP process can be used.
The damage to the polished surface b can be greatly reduced, and scratch-free can be realized. In the second step, the amount of the oxidizing agent is smaller than that in the first step.
That is, the amount of the corrosion inhibitor in the polishing liquid is relatively increased. Then, the main conductor film 1 with respect to the conductive barrier film 17a
Polishing is performed under the condition that the polishing selection ratio of 8a is lower than that of the above-mentioned abrasive-free chemical mechanical polishing, for example, the selection ratio is 3 or less. By polishing under such conditions, in the second step, protection can be strengthened while suppressing oxidation of the main conductor film 18a made of copper.
a can be prevented from being excessively polished, and dishing and erosion can be suppressed or prevented. As a result, an increase or variation in wiring resistance can be suppressed or prevented, so that the performance of the semiconductor integrated circuit device can be improved.

The polishing conditions in the second step are, for example, a load = 120 g / cm ² , a wafer carrier rotation speed = 30 rpm.
, Platen rotation speed = 25rpm, slurry flow rate = 150cc / min
The polishing pad is, for example, IC 1400 manufactured by Rodale.
It was used. The polishing amount is equivalent to the film thickness of the conductive barrier film 17a, and the polishing end point is controlled by the time calculated from the film thickness of the conductive barrier film 17a and the polishing rate.

In such a polishing treatment, the polishing rate of the conductive barrier film 17a is, for example, about 80 nm / min, and the polishing rate of the main conductor film 18a made of copper is, for example, 7 nm.
The polishing rate of the underlying insulating film 12b is about nm / min.
For example, it is about 3 nm / min. The polishing time varies depending on the thickness of the conductive barrier film 17a and cannot be unconditionally determined, but is, for example, about 1 minute at the above-described thickness. In addition, the above-mentioned abrasive grains are made of alumina (Al) instead of colloidal silica.
₂ O ₃ ) can also be used. The chemical mechanical polishing using the above abrasive-free polishing liquid is disclosed in Japanese Patent Application Nos. 9-299937, 10-317233, US Pat. No. 6,117,775, US Pat.
No. 6,326,299.

By the above-described CMP process, as shown in FIG. 9, a buried second layer wiring L2 is formed in the wiring groove 16a. The buried second layer wiring L2 has a relatively thin conductive barrier film 17a and a relatively thick main conductor film 18a, and is electrically connected to the first layer wiring L1 through the plug 14. I have. According to the first embodiment, in the polishing process for forming the buried second layer wiring L2, damage to the polished surface of the insulating film 12b due to the CMP process is greatly reduced by employing the above-described CMP method. And the above scratch-free polishing becomes possible. In the above example, Lo
The insulating film 12b for the insulating cap is provided on the insulating film 11b of the wK material. However, according to the CMP method of the first embodiment, since the scratch-free polishing can be performed, the insulating film 12b for the insulating cap is formed. It is also possible to adopt a structure not provided. That is, a structure in which the insulating film 11b is exposed on the CMP surface may be employed. FIG. 9 illustrates a case where the rightmost embedded second-layer wiring L2 is wider (eg, 4 μm or more in width) than the other embedded second-layer wiring L2. . Note that a taper is formed on the side surface of the buried second layer wiring L2 so that the wiring width gradually increases in a direction away from the main surface of the substrate 1S. The angle formed between the side surface of the buried second layer wiring L2 and the upper surface of the insulating film 11a is, for example, in the range of 80 ° to 90 °, specifically,
For example, it is about 88.7 °. The width on the upper side of the buried second layer wiring L2 (the upper side width of the wiring groove 16a) and the interval on the upper side of the buried second layer wiring L2 adjacent to each other (for the buried second layer wiring L2 buried adjacent to each other) The distance between the upper corners) is, for example, 0.25 μm or less, or 0.2 μm or less. The minimum adjacent pitch between the buried second layer wirings L2 adjacent to each other is, for example, 0.5 μm or less. The aspect ratio of the wiring groove 16a is, for example, 1.

The wafer 1W that has been polished as described above is subjected to anticorrosion treatment on its surface. The anti-corrosion processing section has a configuration similar to the configuration of the polishing processing section. Here, first, the main surface of the wafer 1W is pressed against a polishing pad attached to the surface of a polishing board (platen), and a polishing slurry is mechanically formed. After removal, eg benzotriazole (BTA)
By supplying a chemical containing an anticorrosive agent to the main surface of the wafer 1W, a hydrophobic protective film is formed on the surface of the copper wiring formed on the main surface of the wafer 1W.

The wafer 1W which has been subjected to the anticorrosion treatment is temporarily stored in an immersion treatment section in order to prevent the surface from drying. The immersion processing section is for maintaining the surface of the wafer 1W after the anticorrosion processing is not dried until the wafer 1W is post-cleaned, and is, for example, placed in a immersion tank (stocker) in which pure water overflows. The number of wafers 1W is soaked and stored. At this time, by supplying pure water cooled to such a low temperature that the electrochemical corrosion reaction of the buried second layer wiring L2 does not substantially proceed, the corrosion of the buried second layer wiring L2 can be further improved. This can be prevented more reliably. The prevention of drying of the wafer 1W may be performed by a method other than the above-described storage in the immersion tank as long as at least the surface of the wafer 1W can be maintained in a wet state, for example, by supplying a pure water shower. .

Thereafter, immediately after the surface of the wafer 1W is kept wet, the process proceeds to the post-CMP cleaning process (FIG. 5).
Step 104). First, an alkali cleaning process is performed on the wafer 1W. This processing has the purpose of removing foreign substances such as slurry during the CMP processing, neutralizes the acidic slurry attached to the wafer 1W by the CMP processing, and removes the wafer 1S.
In order to equalize the zeta potentials of the foreign matter, the foreign matter, and the brush for cleaning, and to eliminate the attraction force between them, for example, p
The surface of the wafer 1W is scrub-cleaned (or brush-cleaned) while supplying a weak alkaline chemical solution of about H (pH: hydrogen ion index) of about 8 or more. As the alkaline chemical, for example, aminoethanol (DAE (Diluted Am
ino Ethanol), composition: 2-Aminoethanol, H ₂ NCH ₂
CH ₂ OH, concentration: about 0.001 to 0.1%, preferably 0.01%) was used. This chemical has a small copper etching effect and has the same detergency as NH ₄ OH.
In this cleaning process, a roll-type cleaning method was employed. However, the present invention is not limited to this, and various changes can be made. For example, a disk-type cleaning method can be adopted for alkali cleaning. In addition, a disk-type cleaning method or a pen-type cleaning method can be used for acid cleaning.

Next, FIG. 10 is a cross-sectional view of a portion corresponding to the line X1-X1 in FIG. 6 during the manufacturing process of the semiconductor integrated circuit device following FIG. Here, first, the wafer 1W
A reduction process is performed on the CMP polished surface where the buried second layer wiring L2 is exposed. That is, the wafer 1W (particularly C
The MP polishing surface) was subjected to a heat treatment in a hydrogen gas atmosphere, for example, at 200 to 475 ° C., preferably 300 ° C., for example, for 0.5 to 5 minutes, and preferably for about 2 minutes (hydrogen (H ₂ )). Annealing treatment: Step 105 in FIG. 5). Thereby, the copper oxide film on the surface of the buried second layer wiring L2 generated during the CMP can be reduced to copper, and the etching of the buried second layer wiring L2 due to the subsequent acid cleaning can be suppressed or prevented. . For this reason, it is possible to simultaneously suppress or prevent the increase in the wiring resistance, the variation in the wiring resistance, and the occurrence of the step, and also to suppress or prevent the occurrence of the etch corrosion. If no reduction treatment is performed, CMP
In some cases, organic substances such as BTA attached to the surface of the wafer 1W at the time of processing serve as a mask during the cleaning processing, and the surface layer of the insulating film 12b cannot be satisfactorily removed. By doing, CM
Since organic substances such as BTA attached at the time of P can be removed, the surface layer of the insulating film 12b can be sufficiently and uniformly removed. As a result, the TDDB life of the semiconductor integrated circuit device can be significantly improved. In some cases, it may not be necessary to perform the hydrogen annealing as described above.

Subsequently, an acid cleaning process is performed on the wafer 1W (Step 106 in FIG. 5). This treatment has the purpose of improving TDDB characteristics, removing residual metal, reducing dangling bonds on the surface of the insulating film 12b, removing irregularities on the surface of the insulating film 12b, and supplying an aqueous hydrofluoric acid solution to the surface of the wafer 1W. Then, foreign particles (particles) are removed by etching. The TDDB characteristic can be improved only by inserting hydrofluoric acid cleaning. This is probably because the acid treatment removed the damaged layer on the surface and improved the adhesion at the interface. For the hydrofluoric acid (HF) cleaning, for example, brush scrub cleaning is used, and the conditions of an HF concentration of 0.5% and a cleaning time of 20 seconds can be selected.

According to the experiments of the present inventors, the TDDB of the sequence of alkali cleaning, hydrogen annealing and acid cleaning
The characteristic is the T of continuous sequence of alkali cleaning and acid cleaning.
It was clarified that the DDB characteristic was improved by about two orders of magnitude. Considering the reliability of a buried copper wiring structure using an insulating material having a low dielectric constant for the interlayer insulating film, the improvement of the TDDB life by two digits is a very effective process. By inserting hydrogen annealing between alkali cleaning and acid cleaning,
The reason why the TDDB life is improved may be that organic substances such as BTA attached during CMP are removed.
If acid cleaning is performed with organic substances adhered, cleaning (lift-off) of the surface of the adjacent insulating film which affects the TDDB life
Is estimated to be insufficient. On the other hand, Embodiment 1
Since the cleaning treatment is performed after the hydrogen annealing treatment, the surface layer of the insulating film can be lifted off sufficiently and uniformly, and the TDDB life can be improved.

In the above example, the case where the alkali cleaning treatment is performed, the reduction treatment is performed, and then the acid cleaning is performed has been described. For example, after the CMP process, the reduction process is performed,
Thereafter, post-cleaning treatment may be performed in the order of alkali cleaning treatment and acid cleaning treatment. Alternatively, only acid cleaning may be performed without performing alkali cleaning. That is, a sequence of a CMP process, a reduction process, and an acid cleaning process may be used. The TDDB characteristic is improved only by performing only acid cleaning. This is presumably because removal of the damaged layer improved the characteristics of the interface. On the contrary, there is a case where the above acid cleaning treatment does not need to be performed only by alkali cleaning. Prior to or in parallel with the post-CMP cleaning process, the surface of the wafer 1W may be subjected to pure water scrub cleaning, pure water ultrasonic cleaning, pure water running water cleaning, or pure water spin cleaning, or the back surface of the wafer 1W may be pure water scrubbed. You may wash it.

In the first embodiment, the CMP
The entire chamber including the processing section and the subsequent chambers such as the transfer chamber, the anticorrosion processing chamber, the immersion processing chamber (stocker), the reduction processing chamber, the cleaning processing chamber, and the like has a light shielding structure. This is CMP
When light is irradiated on the processed wafer 1W, the metal of the wafer 1W (here, the buried second layer wiring L2) is corroded by an electrochemical action, so that the corrosion is suppressed or prevented. In particular, this phenomenon is likely to occur until the wafer 1W is removed from the CMP apparatus after the CMP processing and the cleaning processing is performed. By providing a light-shielding structure in the CMP processing section and each chamber in the subsequent process, it is possible to prevent illumination light or the like from irradiating the surface of the wafer 1W after the CMP processing. Can be prevented, and metal corrosion can be suppressed or prevented. To realize such a light shielding structure, specifically, C
The illuminance inside each chamber is at least 500 lux (lx.) Or less, preferably 300 lux or less, or 100 lux or less, more preferably 50 lux or less, by covering the periphery of the MP apparatus and the subsequent processing chamber with a light shielding sheet or the like. Lux or less. The technique of shielding the CMP processing chamber and each chamber in the subsequent steps from light is described in, for example, USSN. 09 / 356,707.

After the above-described cleaning process, a drying process such as a spin drier is performed on the wafer 1W, and the process proceeds to the next step. FIG. 11 is a cross-sectional view of a part corresponding to the line X1-X1 of FIG. 6 during a manufacturing step of the semiconductor integrated circuit device subsequent to FIG. Here, the above CMP
After the post-cleaning process (including the final drying process using a spin dryer or the like), the wafer 1W is placed on a stage in a plasma processing chamber with its main surface facing upward.
Is subjected to, for example, the following reducing plasma treatment. That is, ammonia (NH) is applied to the main surface of the wafer 1W (particularly, the CMP surface where the embedded
₃ ) Perform plasma processing (step 107 in FIG. 5). The ammonia plasma processing conditions include, for example, when the diameter of the wafer 1W is 8 inches (= about 200 mm), the processing pressure is 0.5 to 1.0 Torr (= 666.6612 to 133.
332 Pa), the applied power of the upper electrode of the plasma processing apparatus is about 500 to 1000 W, the applied power of the lower electrode of the plasma processing apparatus is about 0 to 1000 W (preferably 0), and the substrate (wafer) temperature is 300 ° C. to 400 ° C. degree,
Ammonia gas flow rate 500 ~ 1500cm ³ / min
And the processing time was about 5 to 60 seconds. The distance between the electrodes is 300 to 600 mils (7.62 mm to 15.24 m).
m).

In such an ammonia plasma treatment,
Copper oxide (CuO, Cu) on the surface of copper wiring oxidized by CMP
O ₂ ) is reduced to copper (Cu). Further, a copper nitride (CuN) layer for preventing the formation of silicide of copper during the set flow is formed on the surface (extremely thin region) of the buried second layer wiring L2. On the upper surface (extremely thin region) of the insulating film 12b between the wirings, Si
N or SiH is advanced to compensate for dangling bonds on the surface of the insulating film 12b, and to improve the adhesion between the cap insulating film described later and the buried second layer wiring L2 and the insulating film 12b. As a result, the leakage current at the interface can be reduced. The TDDB life can be improved by such an effect.

The above-described reducing plasma processing conditions are not limited to these exemplified conditions. Investigations by the present inventors have revealed that the higher the pressure, the more the plasma damage can be reduced, and the higher the substrate temperature, the more the TDDB life can be reduced in the substrate and the longer the life can be. It has also been found that hillocks are more likely to be generated on the copper surface as the substrate (wafer) temperature is higher, the RF power is higher, and the processing time is longer. Considering these findings and the variation in conditions due to the device configuration and the like, for example, the processing pressure is 0.5 to 6 Torr (= 0.66661 × 10 ² ).
7.99932 × 10 ² Pa), RF power is 300-6
00W, substrate (wafer) temperature 350-450 ° C., hydrogen gas flow rate 50-1000 cm ³ / min, ammonia gas flow rate 20-500 cm ³ / min, processing time 5
~ 180 seconds, distance between electrodes 150 ~ 1000mils
(3.81 to 25.4 mm). The ammonia plasma treatment for the inside of the wiring opening is described in Japanese Patent Application Laid-Open No. 11-1691 by the present inventors.
2, Japanese Patent Application No. 11-226876, Japanese Patent Application 2000-3
00853 and JP-A-2001-291720. Further, the mechanism of the copper diffusion phenomenon and the deterioration of the TDDB life, the ammonia (NH ₃ ) plasma treatment for suppressing or preventing the phenomenon, and the deterioration of the TDDB life of the copper wiring in the Low-K insulating film are described in, for example, IEEE. 00CH37059.38 ^th Annual International Reliabi
lity Physics Symposium, San Jose, Californias, 2000
Pp. 339-343 on the TDDB Improvement in Cu Metalliza
tion under Bias Stress ”
IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 48, NO.
7, `` Effect of NH <sub>3</sub> -Plasm '' on p1340-p1345 of JULY 2001
a Treatment and CMP Modification on TDDB Improveme
nt in Cu Metallization ”
IEEE 01CH37167.39 <sup>th</sup> Annual International Reliabili
ty Physics Symposium, Orlando Florida, 2001, p355
−See p.359, `` Impact of Low-K Dielectrics and Barrier
A paper entitled "Metals on TDDB Lifetime of Cu Interconnects" is described by the present inventor.

FIG. 12 is a cross-sectional view of a part corresponding to the line X1-X1 of FIG. 6 during the manufacturing process of the semiconductor integrated circuit device following FIG. FIG. 13 is a cross-sectional view of the semiconductor integrated circuit device taken along the line X1-X in FIG.
It is sectional drawing of the part corresponding to one line. Here, first,
As shown in FIG. 12, after the ammonia plasma treatment,
In the plasma processing chamber in which the ammonia plasma processing has been performed, the wafer 1 is continuously released while maintaining a vacuum state without opening to the atmosphere.
W main surface, especially buried second layer wiring L2 and insulating film 12b
Is exposed to an atmosphere of an inorganic silane compound gas such as a monosilane gas (SiH ₄ ) (step 108 in FIG. 5). Thereby, silicon (first atom) is dissolved in the surface layer of the main conductor film 18a of the buried second layer wiring L2.
Specifically, for example, the following is performed. First, the pressure in the processing chamber is set to, for example, 3.0 Torr (399.967 Pa).
About 300 ° C. to 450 ° C.
℃, as a carrier gas in the processing chamber,
For example, a set flow of this processing is started by flowing helium gas. Subsequently, 20 seconds after the start of the flow of the carrier gas, a monosilane gas is flown into the processing chamber while the carrier gas is flowing, and the inorganic silane compound gas treatment is started. This state is continued for, for example, about 10 seconds, and silicon is dissolved in the surface layer of the main conductor film 18a of the buried second-layer wiring L2 to complete the process. At this time, the flow rate of the silane gas is, for example, about 400 cm ³ / min, and the flow rate of the helium gas is:
For example, it is about 900 cm ³ / min. The amount of solid solution of silicon is set so as not to change the crystal system of the main conductor film 18a of the buried second layer wiring L2, and specifically, is set to about 5% or less of the entire main conductor film 18a. Preferably. Through such processing, holes (through holes)
It is possible to suppress or prevent the occurrence of voids due to SM in the upper portion of the embedded wiring corresponding to the bottom. This is because copper oxide on the surface layer of the embedded wiring was reduced to copper by monosilane because the reducing ability of monosilane gas was higher than that of organic silane compound gas such as trimethylsilane. In other words, a small amount of silicon dissolved in the embedded wiring surface layer
SiO— that suppresses or prevents grain boundary diffusion by gettering (bonding with oxygen) oxygen in the surface layer of the buried wiring
As a result of the formation of the (Cu) bond, the diffusion of copper (or copper oxide) in the buried wiring surface layer can be suppressed or prevented, so that the SM failure can be suppressed or prevented. In the first embodiment, this inorganic silane compound gas treatment is performed as follows.
It is positioned as a part of a set flow of a subsequent wiring cap film deposition process. Therefore, the addition of the inorganic silane compound gas treatment does not increase the production time, nor does the control and the production apparatus become complicated. Further, it is easy to adjust the processing atmosphere in the process of depositing the insulating film for the wiring cap from the ammonia plasma processing,
Since the processing can be stabilized, the reliability of the processing and the reproducibility of the processing result can be improved. Of course, the inorganic silane compound treatment can be positioned as a separate and independent step without being positioned as a part of the set flow of the wiring cap film deposition process.

Then, as shown in FIG. 13, after the above-mentioned inorganic silane compound gas treatment, the embedded second-layer wiring is continuously maintained in the plasma treatment chamber where the treatment was performed without opening to the atmosphere and maintaining a vacuum state. An insulating film (second insulating film) 15b for wiring cap is deposited on the upper surface of L2 and the insulating film 12b by a plasma CVD method or the like (Step 10 in FIG. 5).
9). The insulating film 15b is deposited using the same material and the same film forming method as the above-described insulating film 15a. In particular, in the first embodiment, a plasma CVD method using an organic silane compound gas as a film forming gas when forming the insulating film 15b is employed. That is, the insulating film 15b is deposited by a plasma CVD method that does not include an inorganic silane compound gas such as monosilane in the deposition gas. As a material of the insulating film 15b thus formed, for example, silicon carbonitride (S
iCN), silicon carbide (SiC) or silicon oxynitride (SiON). Since each of the materials has a lower dielectric constant than the silicon nitride film, the wiring capacitance can be reduced, and the operation speed of the semiconductor integrated circuit device can be improved.

The material for the insulating film 15b is silicon carbonitride (S
In the case of iCN), for example, deposition is performed as follows. First, the pressure in the processing chamber is set to, for example, 3.0 Torr (39
At a substrate (wafer) temperature of, for example, about 9.967 Pa) and a temperature of, for example, about 300 ° C. to 450 ° C., a helium gas, for example, as a carrier gas is introduced into the processing chamber to start the set flow of this deposition process. The flow rate of the helium gas at this time is, for example, about 900 cm ³ / min. Subsequently, 20 seconds after the start of the flow of the carrier gas, the trimethylsilane gas and the ammonia gas (NH ₃ ) flow into the processing chamber with the flow of the carrier gas. The flow rate of the helium gas at this time is, for example, 400 cm ³ /
The flow rate of trimethylsilane gas is, for example, about 160 cm ³ / min, and the flow rate of ammonia gas is, for example, about 325 cm ³ / min. continue,
For example, film formation is started by forming plasma when about 10 seconds have elapsed, and the state is continued for about 30 seconds, for example, so that the insulating film 15b containing silicon carbonitride as a main component is formed on the main surface of the wafer 1W. accumulate.

The material of the insulating film 15b is silicon carbide (Si)
In the case of C), for example, deposition is performed as follows. First,
The pressure in the processing chamber is, for example, 8.7 Torr (1159.
90Pa), the substrate (wafer) temperature is, for example, 300
At a temperature of about 450 ° C. to 450 ° C., helium gas, for example, is introduced as a carrier gas into the processing chamber to start the set flow of the deposition process. The flow rate of the helium gas at this time is, for example, about 1200 cm ³ / min. Subsequently, 20 seconds after the start of the flow of the carrier gas, the trimethylsilane gas flows into the processing chamber with the flow of the carrier gas. The flow rate of the helium gas at this time is, for example, about 800 cm ³ / min, and the flow rate of the trimethylsilane gas is, for example, about 320 cm ³ / min. Subsequently, film formation is started by forming plasma when, for example, about 10 seconds have elapsed, and the state is changed to, for example, 30 seconds.
By continuing for about seconds, the insulating film 15b containing silicon carbide as a main component is deposited on the main surface of the wafer 1W.

The material of the insulating film 15b is PE-TMS (Ca
In the case of silicon oxynitride (SiON) such as non-manufactured, dielectric constant = 3.9), for example, by a plasma CVD method using a mixed gas of a trimethoxysilane gas and a nitrogen oxide (N ₂ O) gas or the like. accumulate. This silicon oxynitride contains nitrogen (N) of 5 atm% or less, preferably about 1 or 2 atm%. This is because the inclusion of about 1 or 2 atm% of nitrogen can provide a sufficient barrier property against copper, and the nitrogen content of 5 atm%
Even if the number is increased, no improvement in characteristics can be expected, and the dielectric constant becomes higher than that of silicon carbide, and the meaning of using silicon oxynitride diminishes. When the material of the insulating film 15b is PE-TMS (manufactured by Canon) or the like,
Since excellent moisture resistance can be obtained, reliability and performance of the semiconductor integrated circuit device can be improved.

FIG. 14 is a cross-sectional view of a part corresponding to the line X1-X1 of FIG. 6 during the manufacturing process of the semiconductor integrated circuit device, following FIG. Here, the wafer 1 having undergone the interlayer insulating film deposition step and the insulating cap film deposition step
5 is a sectional view of a main part of W (steps 110 and 1 in FIG. 5).
11). An insulating film 11c is deposited on the wiring cap insulating film 15b. The material and forming method of the insulating film 11c are as follows.
a, 11b. On this insulating film 11c, an insulating film 12c is deposited. The material, forming method and function of the insulating film 12c are the same as those of the insulating films 12a and 12b. On this insulating film 12c, an insulating film 15c is deposited. The material, forming method and function of the insulating film 15c are the same as those of the insulating films 15a and 15b. On this insulating film 15c, an insulating film 11d is deposited. The material and forming method of the insulating film 11d are the same as those of the insulating films 11a to 11c made of the Low-K material. On this insulating film 11d, an insulating film 12d is deposited.
The material, forming method and function of the insulating film 12d are the same as those of the insulating films 12a to 12c.

FIG. 15 is a plan view of a main part of the semiconductor integrated circuit device during the manufacturing process following FIG. 14, and FIG.
FIG. 5 is a sectional view taken along line X2-X2 of FIG. Here, the insulating film 1
A flat strip-shaped wiring groove (wiring opening) 16b is formed in each of 5c, 11d, and 12d. Here, FIGS. 15 and 16
In the example, the width of the second wiring groove 16b from the left is wider than the wiring groove 16a immediately below. The rightmost wiring groove 16 in FIGS.
The case where the width of b is narrower than the wiring groove 16a immediately below is illustrated. Further, a through hole (wiring opening) 19 having a plane circular shape such that a part of the upper surface of the buried second layer wiring L2 is exposed is formed at the bottom of the desired wiring groove 16b. The diameter of the through hole 19 is, for example, about 0.18 μm.

FIG. 17 is a fragmentary cross-sectional view of a part corresponding to the line X2-X2 of FIG. 15 during the manufacturing process of the semiconductor integrated circuit device continued from FIG. Here, the wiring groove 16
b and the through hole 19 are buried with the conductive barrier film 17b and the main conductor film 18b so that the buried third layer wiring L
Form 3 The buried third layer wiring L3 is formed by a dual damascene method. That is, the insulating film 1
After forming a wiring groove 16b in 5c, 11d, and 12d and forming a through hole 19 in the insulating films 15b, 11c, and 12c, the conductive barrier film (first conductive film) 17b and the conductive barrier film 17b are thicker. Main conductor film (second conductor film)
18b are sequentially deposited. That is, the wiring groove 16b and the through hole 19 are simultaneously filled with the conductive barrier film 17b and the main conductor film 18b. The deposition method and material of the conductive barrier film 17b and the main conductor film 18b are the same as those of the conductive barrier film 17a and the main conductor film 18a of the buried second layer wiring. Thereafter, the conductive barrier film 17b and the main conductor film 18b are polished by the CMP method in the same manner as the formation of the buried second layer wiring L2, thereby forming a buried third layer wiring L3. The buried third layer wiring L3 is electrically connected to the buried second layer wiring L2 through the conductive barrier film 17b and the main conductor film 18b buried in the through hole 19. Thereafter, steps 104 to 10 of FIG.
8, an insulating film (second insulating film) 15 d for wiring caps made of the same material as the insulating film 15 b is formed on the insulating film 12 d and the buried third-layer wiring L 3 similarly to the insulating film 15 b. accumulate. Here, 2 from the left in FIG.
The case where the width of the third buried third-layer wiring L3 is wider than that of the buried second-layer wiring L2 immediately below which is electrically connected through the through hole 19 is illustrated. In addition, the width of the rightmost embedded third-layer wiring L3 in FIG.
Buried second layer wiring L immediately below electrically connected through
The case where it is narrower than 2 is illustrated. In the first embodiment, the generation of voids at the bottom of the through hole 19 can be suppressed or prevented in any of the wiring connection structures. That is, the occurrence of SM failure could be suppressed or prevented.

FIG. 18 shows the rate of increase in resistance in the hole (through hole 19) connecting the wiring layers. The case where the substrate (wafer) temperature is set to, for example, 175 ° C. and left for, for example, 141 hours is shown. Sign R1
(A black triangle) shows a case where the above-mentioned inorganic silane compound gas treatment of the first embodiment is performed, and a reference symbol R0 (white square) is a technique studied by the present inventor and represents the above-mentioned inorganic silane compound gas treatment. Is not applied.
From this result, it is understood that in the case of the first embodiment, the resistivity hardly deteriorates (does not increase). FIG.
8, if the resistivity of the hole exceeds about 4-5%, voids are generated in the wiring portion at the bottom of the hole due to further thermal stress, and poor connection occurs between the hole and the wiring. Has been empirically found from various experiments performed repeatedly.

FIG. 19 shows the results of measuring the diffusion coefficient of copper when silicon is dissolved in the surface layer of copper wiring by the above-mentioned inorganic silane compound gas treatment. The measurement point of the black triangle in FIG. % Indicates the diffusion state of silicon in the copper crystal containing copper, the white square measurement point indicates the diffusion state of copper in the pure copper crystal, and the white triangle measurement point indicates that silicon has 1 at. 2 shows the state of diffusion of copper in a copper crystal containing 0.1%. On the other hand, FIG. 20 shows the measured diffusion coefficient of copper when oxygen is mixed into the surface layer of the copper wiring. The measurement point of the black triangle in FIG.
at. % Indicates the diffusion state of oxygen in the copper crystal, and white square measurement points indicate the diffusion state of copper in the pure copper crystal.
The measurement point of the white triangle indicates that oxygen is 1 at. 2 shows the state of diffusion of copper in a copper crystal containing 0.1%. From these two figures, it can be seen that when silicon is dissolved in the surface layer of copper wiring, copper is hardly diffused, whereas when oxygen is mixed into the surface layer of copper wiring, copper is diffused. I understand.

As described above, in the first embodiment, even when a material having a lower dielectric constant than silicon nitride is used as the material of the insulating film for the wiring cap, the SM failure in the embedded wiring can be suppressed or prevented. Therefore, the dielectric constant of the insulating film for the wiring cap can be reduced, so that the operation speed of the semiconductor integrated circuit device can be improved, the performance of the semiconductor integrated circuit device can be improved, and the SM failure can be improved. Since the occurrence can be suppressed or prevented, the resistance at the hole connecting the different wiring layers can be reduced, and the performance, reliability and yield of the semiconductor integrated circuit device can be improved.

(Embodiment 2) The reducing plasma treatment reduces the copper oxide on the surface of the copper wiring to copper and improves the chemical stability of the surface layer. However, if the surface of the copper wiring is excessively stabilized by the reducing plasma treatment, silicon may not be able to form a solid solution on the surface of the copper wiring in the subsequent inorganic silane compound treatment. For this reason, the object of the inorganic silane compound gas treatment of suppressing or preventing the diffusion of copper (copper oxide, oxygen) on the surface of the copper wiring by dissolving silicon on the surface of the copper wiring cannot be achieved. . For example, according to the study of the present inventor, when silicon carbonitride is used as an insulating film for a wiring cap, the ammonia plasma processing conditions include, for example, the flow rates of ammonia gas and nitrogen gas of 400 cm ³ / min, 45 cm, respectively.
When the power was about 300 cm ³ / min, the power was 300 W, and the processing time was 20 seconds, a very good result could not be obtained in obtaining the effects of the monosilane. Similarly, the ammonia plasma processing conditions are as follows: ammonia gas alone is about 400 cm ³ / min;
W, even when the treatment time was 30 seconds, good results could not be obtained in obtaining the effects of the monosilane.

Therefore, in the second embodiment, the condition of the reducing plasma treatment performed before the above-mentioned inorganic silane compound gas treatment is such that silicon is solid-dissolved in the surface layer of the embedded wiring in the above-mentioned inorganic silane compound gas treatment. Set to make it easier. Thereby, the effect of the inorganic silane compound gas treatment can be made more effective. For example, the above conditions suggest that the following conditions are good. First, it is better that the carrier gas in the processing gas during the reducing plasma processing is relatively large. Second, the power should be relatively low (e.g., lower if 600 W is high power). Third, the processing time varies depending on the above conditions, but is preferably shorter. According to the study of the present inventor, the inflow amount of nitrogen gas in the above-described ammonia plasma processing is about 20% or less, or 10% or less, of the total gas amount flowing into the processing chamber.
Or less. The power is, for example, 400 W
Or less, or 300 W or less. Further, the processing time is preferably, for example, 25 seconds or less, or 20 seconds or less. Specifically, for example, the following is performed.

FIG. 21 is a flow chart in the case where a silicon carbonitride film having a thickness of, for example, about 50 nm is deposited on the main surface of a wafer as an insulating film for wiring caps (the insulating films 15b and 15d in the first embodiment). FIG. In this case, in the ammonia plasma process, first, the pressure in the processing chamber is set to, for example, about 4.2 Torr (559.954 Pa), and the substrate (wafer) temperature is set to, for example, 300 ° C. to 450 ° C.
In this state, for example, ammonia gas (NH ₃ ) and nitrogen gas (N ₂ ) flow into the processing chamber. The flow rate of the ammonia gas is, for example, about 75 cm ³ / min. The flow rate of the nitrogen gas is larger than the flow rate of the ammonia gas, for example, about 5000 cm ³ / min. Subsequently, a voltage is applied between the upper and lower electrodes for plasma formation after about 20 seconds have elapsed from the start of the flow of the gas while flowing the gas into the processing chamber at the above-mentioned flow rate, whereby plasma is formed in the processing chamber. Then, a plasma process mainly using ammonia is performed on the main surface (CMP surface) of the wafer for about 30 seconds. The power at this time is lower than the power during general ammonia plasma processing (for example, about 600 W), and is, for example, about 150 W. In addition,
In this case, the processing conditions before and after the ammonia plasma processing are the same as those in the first embodiment, and a description thereof will be omitted.

FIG. 22 shows a case where a silicon carbide film having a thickness of, for example, about 50 nm is deposited on the main surface of the wafer as an insulating film for wiring caps (the insulating films 15b and 15d of the first embodiment). FIG. 4 shows a flow diagram. In this case, in the case of the ammonia plasma treatment, when the silicon carbonitride described with reference to FIG. 21 is used as the insulating film for the wiring cap, the nitrogen gas is merely helium gas (He). Is the same as In this case, according to the study of the present inventor, the inflow amount of helium gas in the above-described ammonia plasma processing is preferably about 20% or less or about 10% or less of the total gas amount flowing into the processing chamber. Preferred numerical examples of the power and the processing time are the same as those described in the case where the insulating film for the wiring cap is made of silicon carbonitride. In this case, the conditions of the treatment with the monosilane gas and the deposition of the insulating films 15b and 15d for the wiring cap are also the same as those described in the first embodiment, and the description is omitted.

(Embodiment 3) A method of manufacturing a semiconductor integrated circuit device according to Embodiment 3 will be described with reference to FIGS.

FIG. 23 is an explanatory diagram showing an example of the overall configuration of a CMP apparatus used for forming an embedded wiring containing copper as a main component. The CMP apparatus 31 has a polishing section 31a and a post-cleaning section 31b provided at a subsequent stage. The polishing processing section 31a has two surface plates (first surface plate 31c1 and second surface plate 31c2) for polishing the wafer 1W, preliminarily cleaning the polished wafer 1W, and performing anticorrosion treatment on the surface thereof. And a rotating arm 31g for moving the substrate 1 between the loader 31e, the first base plate 31c1, the second base plate 31c2, the clean station 31d, and the unloader 31f.

In the subsequent stage of the polishing processing section 31a, a post-cleaning section 3 for scrub-cleaning the surface of the wafer 1W which has been subjected to the preliminary cleaning.
1b is provided. The post-cleaning unit 31b includes a loader 3
1h, a first cleaning unit 31i1, a second cleaning unit 31i2, a spin dryer 31j, an unloader 31k, and the like are provided. Further, the polishing processing section 31a and the post-cleaning section 31b
In order to prevent the surface of the wafer 1W being cleaned from being irradiated with light, the whole is surrounded by a light-shielding wall 31m, and the interior is in a dark room state of 180 lux, preferably 100 lux or less, more preferably 50 lux or less. ing. This is because when the wafer 1W having the polishing liquid adhered to the surface is irradiated with light in a wet state, a short-circuit current flows through the pn junction due to the photoelectromotive force of silicon, and the wafer 1W is connected to the p-side (+ side) of the pn junction. This is to prevent Cu ions from dissociating from the surface of the Cu wiring and causing corrosion of the wiring. In particular, since such photocorrosion is highly likely to occur between immediately after the wafer is removed from the CMP table and before the wafer is transferred to the post-cleaning unit 31b, not only the post-cleaning unit 31b but also the polishing processing unit 31a is required. Are also surrounded by a light shielding wall 31m to form a dark room state.

As shown in FIG. 24, the first platen 31c1
Is rotationally driven in a horizontal plane by a driving mechanism 31n provided thereunder. A polishing pad 31p formed by uniformly applying a synthetic resin such as polyurethane having a large number of pores is attached to the upper surface of the first base plate 31c1. The drive mechanism 31 is provided above the first surface plate 31c1.
A wafer carrier 31r that is moved up and down by q and rotated in a horizontal plane is provided. The wafer 1W is held with its main surface (polished surface = CMP surface) downward by a wafer chuck 31s and a retainer ring 31t provided at the lower end of the wafer carrier 31r.
It is pressed against the polishing pad 31p with a predetermined load. A slurry (polishing liquid) Sr is supplied between the surface of the polishing pad 31p and the surface to be polished of the wafer 1W through a slurry supply pipe 31u, and the surface to be polished of the wafer 1W is chemically and mechanically polished. A dresser 31w is provided above the first surface plate 31c1 to be vertically moved by a driving mechanism 31v and to be rotationally driven in a horizontal plane. A base material on which diamond particles are electrodeposited is attached to the lower end of the dresser 31w, and the surface of the polishing pad 31p is periodically cut by the base material in order to prevent clogging by abrasive grains. The second surface plate 31c2 has substantially the same configuration as the first surface plate 31c1, except that two slurry supply pipes 31u and 31u are provided.

In order to form a buried wiring mainly composed of copper by using the CMP apparatus 31, the wafer 1W accommodated in the loader 31e is loaded into the polishing processing section 31a by using the rotating arm 31g. The wafer 1W has undergone the same steps as those described with reference to FIGS. And
First, as shown in FIG.
On c1, chemical mechanical polishing (abrasive-free chemical mechanical polishing) using a slurry containing no abrasive grains (CMP in the first step) is performed, as shown in FIGS. 26 and 27.
The main conductor film 18a made of copper outside the wiring groove 16a is removed.

Here, the abrasive grain-free chemical mechanical polishing means that the content of abrasive grains made of a powder such as alumina or silica is 0.5%.
It means chemical mechanical polishing using a polishing liquid (slurry) of not more than% by weight.
% By weight or less, more preferably 0.05% by weight or less or 0.01% by weight or less.

As the polishing liquid, a polishing liquid whose pH has been adjusted so as to belong to the corrosive zone of copper is used, and the polishing selectivity of the main conductor film 22a to the conductive barrier film 21a is at least 5 or more. The composition of which is adjusted as described above is used. As such a polishing liquid, a slurry containing an oxidizing agent and an organic acid can be exemplified.
Examples of the oxidizing agent include hydrogen peroxide, ammonium hydroxide, ammonium nitrate, and ammonium chloride. Examples of the organic acid include citric acid, malonic acid, fumaric acid, malic acid, adipic acid, benzoic acid, and phthalic acid. , Tartaric acid, lactic acid, succinic acid, oxalic acid and the like. Of these, hydrogen peroxide does not contain metal components,
Since it is not a strong acid, it is a suitable oxidizing agent for use in polishing liquids. In addition, citric acid is also commonly used as a food additive, has low toxicity, has low harm as a waste liquid, has no odor, and has high solubility in water, so it is a suitable organic acid for use in a polishing liquid. . In the third embodiment, for example, 5
A polishing liquid is used in which volume% of hydrogen peroxide and 0.03% by weight of citric acid are added to reduce the content of abrasive grains to less than 0.01% by weight.

When chemical mechanical polishing is performed with the above polishing liquid, first, the copper surface is oxidized by an oxidizing agent, and a thin oxide layer is formed on the surface. Next, when a substance for making the oxide water-soluble is supplied, the oxide layer is eluted as an aqueous solution, and the thickness of the oxide layer is reduced. The portion where the oxide layer has become thinner is again exposed to an oxidizing substance to increase the thickness of the oxide layer. This reaction is repeated, and chemical mechanical polishing proceeds. The chemical mechanical polishing using such an abrasive-free polishing liquid is disclosed in Japanese Patent Application Nos. 9-299937 and 1-1990 by the present inventors.
No. 0-317233.

The polishing conditions are, for example, a load = 250 g.
/ cm ² , wafer carrier rotation speed = 30 rpm, surface plate rotation speed =
The polishing pad was a hard pad (Rodell, USA) (IC140) at 25 rpm and a slurry flow rate of 150 cc / min.
0) is used. The polishing end point is a point in time when the main conductive film 18a is removed and the underlying conductive barrier film 17a is exposed. This is performed by detecting the intensity of the rotation torque signal of the surface plate or wafer carrier. Also, a hole is made in a part of the polishing pad, and the substrate 1
The end point may be detected based on a change in the light reflection spectrum from the surface, or the end point may be detected based on the change in the optical spectrum of the slurry.

By performing the above-mentioned abrasive-free chemical mechanical polishing, the main conductor film 18a outside the wiring groove 16a is almost completely removed and the lower conductive barrier film 17a is exposed. In the recesses (indicated by arrows) of the conductive barrier film 17a, the main conductor film 18a that cannot be completely removed by this polishing remains.

Next, in order to remove the conductive barrier film 17a outside the wiring groove 16a and the main conductor film 18a left locally on the upper surface thereof, the wafer 1W is removed from the wafer 1W as shown in FIGS.
Is transferred from the first surface plate 31c1 to the second surface plate 31c2, and a chemical mechanical polishing (abrasive grain chemical mechanical polishing) (a CMP in the second step) using a polishing liquid (slurry) containing abrasive grains is performed. Here, the abrasive grain chemical mechanical polishing means chemical mechanical polishing using a polishing liquid in which the content of abrasive grains made of a powder such as alumina or silica is more than 0.5% by weight. In the third embodiment, 5 vol% hydrogen peroxide, 0.03 wt% citric acid and 0.5 wt%
Is used, but the present invention is not limited to this. This polishing liquid is supplied to the slurry supply pipe 31.
The liquid is supplied to the polishing pad 31p of the second platen 31c2 through u.

In the abrasive grain chemical mechanical polishing, following the removal of the main conductive film 18a locally remaining on the upper surface of the conductive barrier film 17a, the conductive barrier film 17a outside the wiring groove 16a is removed. Remove. Therefore, polishing is performed under the condition that the polishing selection ratio of the main conductor film 18a to the conductive barrier film 17a is lower than that of the abrasive grain-free chemical mechanical polishing, for example, at a selection ratio of 3 or less. Polishing of the surface of the body film 18a is suppressed.

The polishing conditions are, for example, load = 120 g.
/ cm ² , wafer carrier rotation speed = 30 rpm, surface plate rotation speed =
At 25 rpm, the slurry flow rate is 150 cc / min, and the polishing pad uses an IC 1400 manufactured by Rodale. The polishing amount is equivalent to the film thickness of the conductive barrier film 17a.
It is controlled by the time calculated from the thickness and the polishing rate of the conductive barrier film 17a.

Next, as shown in FIGS. 28 and 29, by performing the above-mentioned abrasive grain chemical mechanical polishing, the conductive barrier film 17a outside the wiring groove 16a is almost removed, and the lower insulating film 12b is removed. Although exposed, a dent (indicated by an arrow) of the insulating film 12b caused by the step of the base may be:
The conductive barrier film 18a that could not be removed by the above polishing
Remain.

Next, the main conductor film 18 inside the wiring groove 16a is formed.
The conductive barrier film 17 locally remaining on the insulating film 12b outside the wiring groove 16a while suppressing the polishing of
Perform selective chemical mechanical polishing (CMP of the third step) to remove a. This selective chemical mechanical polishing is performed under the condition that the polishing selection ratio of the conductive barrier film 17a to the main conductor film 18a is at least 5 or more. In addition, this chemical mechanical polishing is performed by using the insulating film 1 with respect to the polishing rate of the main conductor film 18a.
The polishing is performed under the condition that the ratio of the polishing rates of 2b is larger than 1.

In order to carry out the above-mentioned selective chemical mechanical polishing, generally, a polishing liquid containing more than 0.5% by weight of abrasive grains, as used in the above-mentioned abrasive grain chemical mechanical polishing, obtained by adding an anticorrosive agent to the polishing liquid. Use The anticorrosion agent refers to a chemical agent that inhibits or suppresses the progress of polishing by forming a corrosion-resistant protective film on the surface of the main conductor film 18a. Triazole, tolyltriazole, and the like are used. In particular, when BTA is used, a stable protective film can be formed.

When BTA is used as an anticorrosive, its concentration depends on the type of slurry, but is usually 0.001 to 1
Sufficient effects can be obtained by adding 0.1% by weight, more preferably 0.01% to 1% by weight, and even more preferably 0.1% to 1% by weight (3 stages). In the third embodiment, a polishing liquid obtained by mixing 0.1% by weight of BTA as an anticorrosive with a polishing liquid used in the abrasive chemical mechanical polishing in the second step is used, but the present invention is not limited to this. Not something. Further, in order to avoid a decrease in the polishing rate due to the addition of the anticorrosive, polyacrylic acid, polymethacrylic acid, an ammonium salt thereof, ethylenediaminetetraacetic acid (EDTA) or the like may be added as necessary. The chemical mechanical polishing using a slurry containing such an anticorrosive is described in Japanese Patent Application Nos. 10-209857 and 9-209 filed by the present inventors.
No. 299937, Japanese Patent Application No. 10-317233 and U
SSN. 09 / 527,751.

This selective chemical mechanical polishing (third step CMP) is performed after the completion of the above-mentioned abrasive grain chemical mechanical polishing (second step CMP), followed by the CMP apparatus shown in FIGS. Is performed on the second platen 31c2.
The polishing liquid to which the anticorrosive has been added is supplied to the slurry supply pipe 31u.
Through the surface of the polishing pad 31p. The polishing conditions are, for example, load = 120 g / cm ² , wafer carrier rotation speed = 30 rpm, platen rotation speed = 25 rpm, and slurry flow rate = 190 cc / min.

Next, as shown in FIGS. 30 and 31, by performing the above-mentioned selective chemical mechanical polishing, all the conductive barrier film 17a outside the wiring groove 16a is removed and embedded in the wiring groove 16a. The embedded second-layer wiring L2 is formed. A slurry residue containing particles such as abrasive grains and metal particles such as Cu oxide adheres to the surface of the wafer 1W on which the formation of the buried second layer wiring L2 is completed. Therefore, in order to remove this slurry residue, first, in the clean station 31d shown in FIG.
The wafer 1W is washed with pure water containing A. At this time, high frequency vibration of 800 kHz or more is applied to the cleaning
Megasonic cleaning for releasing the slurry residue from the surface of the substrate may be used in combination. Next, the wafer 1W is transported from the polishing processing section 31a to the post-cleaning section 31b while keeping the wafer 1W in a wet state in order to prevent the surface from drying, and the cleaning liquid containing 0.1% by weight of NH 4 OH is washed in the first cleaning section 31i1. The used scrub cleaning is performed, and then the scrub cleaning using pure water is performed in the second cleaning unit 31i2. As described above, the post-cleaning portion 31b is entirely formed of the light shielding wall 31m in order to prevent the buried second layer wiring L2 from being corroded due to the irradiation of light on the surface of the wafer 1W being cleaned. Covered with.

After the scrub cleaning (post-cleaning) is completed, the wafer 1W is dried by the spin drier 31j and then transferred to the next step. Subsequent steps are the same as in the first embodiment. FIG. 32 is a flowchart showing a part of the formation process of the buried second layer wiring L2 described above. The other steps are the same as those of the first and second embodiments.

According to this embodiment, the TDDB life can be further improved as compared with the first and second embodiments. This is because, in the case of abrasive grains, the slurry has a particle size of 2-3 μm (2
Abrasive grains (e.g., alumina). The abrasive grains cause micro-scratch and damage the surface of the silicon oxide film (insulating film 16d). However, in the case where the abrasive grains are free, the abrasive grains are not contained in the slurry, or even if they are contained, the number is very small, so that the damage can be greatly reduced. Therefore, it is considered that the TDDB characteristics have been improved.

(Embodiment 4) In Embodiment 4, a case will be described in which hydrogen plasma processing is performed as the reducing plasma processing in place of the ammonia plasma processing of Embodiments 1 to 3. That is, in the fourth embodiment,
After the post-CMP cleaning process (including the final drying process using a spin dryer or the like), the main surface of the wafer 1W (particularly, the CMP surface where the embedded second-layer wiring L2 is exposed) is subjected to hydrogen plasma processing. Is applied. This hydrogen plasma processing condition is, for example, that the diameter of the wafer 1W is 8 inches (= about 200
mm), the processing pressure is 5.0 Torr (= 6.mm).
6661 × 10 ² Pa) and a high frequency (RF) power of 600
W, substrate temperature 400 ° C., hydrogen gas flow rate 500 cm ³
/ Min, and the processing time was 10 to 30 seconds. The distance between the electrodes was 600 mils (15.24 mm). As the processing gas, for example, a simple gas of hydrogen (H) or a mixed gas of hydrogen (H) and nitrogen (N) was used. Except for this, it is the same as the first to third embodiments.

By performing such a hydrogen plasma treatment, as described in Japanese Patent Application Nos. 11-226876 and 2000-300583 by the present inventors, the ability to remove organic compounds is extremely high (as described above). BTA, CMP, slurry components, organic acids used for post-CMP cleaning, and residual organic matter generated during the process are almost completely removed.
The leakage current at the interface can be reduced. As a result, the TDDB life can be further improved.

(Fifth Embodiment) In the fifth embodiment, a case will be described in which both the ammonia plasma treatment and the hydrogen plasma treatment are performed as the reducing plasma treatment. That is, here, in the first embodiment, after the post-CMP cleaning process (including the final drying process using a spin drier or the like), the wafer 1
Main surface of W (particularly, CMP in which buried second layer wiring L2 is exposed)
After applying hydrogen plasma treatment to the surface, ammonia gas treatment is performed by changing the gas in a vacuum state without opening to the atmosphere. Except for this, it is the same as the first to fourth embodiments. Further, the processing conditions of the hydrogen plasma and the ammonia plasma are the same as those in the first to fourth embodiments, and thus the description thereof is omitted. By performing the hydrogen plasma treatment and the ammonia plasma treatment in this order, reduction of the surface of the buried second-layer wiring L2 containing copper as a main component and formation of a silicide-resistant barrier layer, cleaning of the interface of the insulating film 12b, and The SiH effect and the SiN effect can be obtained, and the reliability can be further improved. In the case where the interlayer insulating film is formed by depositing a silicon nitride film formed by a plasma CVD method on a silicon oxide film formed by a plasma CVD method using TEOS (Tetraethoxysilane) gas, hydrogen The present inventors have clarified that the TDDB life of a sample obtained by combining plasma and ammonia plasma is improved by about two orders of magnitude as compared with the case of ammonia plasma treatment alone. Even when the above-described SiLK is used as the interlayer insulating film, when hydrogen plasma and ammonia plasma are used, for example, about 0.13 to 0.17 MV / c
The experiments by the present inventors have revealed that sufficient reliability can be ensured even in an operating environment of 10 years.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say,

For example, in the above-described embodiment, an inorganic silane compound gas treatment has been exemplified as a method for dissolving silicon in the surface layer of a wiring containing copper as a main component. However, the present invention is not limited to this. Silicon (Si) may be implanted into the surface of the wiring as a component by ion implantation to form a solid solution.

Further, in the above-described embodiment, a case has been described where the atom for suppressing or preventing the diffusion of copper is silicon. However, the present invention is not limited to this, and various changes can be made. For example, nickel (Ni) or ruthenium can be used. (R
u) or the like. In this case, when depositing a conductive film mainly containing copper for forming an embedded wiring on the main surface of the wafer by sputtering, atoms such as nickel or ruthenium are mixed in the target by about several%. . In this case, nickel and ruthenium are dispersed and dissolved in the entire buried wiring. Thereby, the diffusion of copper (copper oxide) in the embedded wiring can be suppressed or prevented, so that the generation of voids due to SM can be suppressed or prevented. Also, even if nickel or ruthenium is solid-dissolved by about several percent, the wiring resistance does not significantly increase.

In the above embodiment, the low level
Although the case where the −K material is used as the interlayer insulating film material has been described, the present invention is not limited to this, and a general buried wiring structure in which the interlayer insulating film is a silicon oxide film may be used.

Further, in the above embodiment, the case where the insulating film for the low-K cap is provided has been described. However, by employing the abrasive-free chemical mechanical polishing at the time of the CMP processing, the insulating film on the CMP surface can be formed. Since the polished surface can be made scratch-free, it is possible to adopt a structure in which an insulating film for a Low-K cap is eliminated. in this case,
Since the dielectric constant of the insulating film in the wiring layer can be significantly reduced and the wiring capacitance can be significantly reduced, the operation speed of the semiconductor device can be improved.

In the fifth embodiment, the case where the ammonia plasma treatment is performed after the hydrogen plasma treatment has been described. However, the present invention is not limited to this case, and various changes can be made. The process may be continuously shifted to the hydrogen plasma treatment while maintaining the same. Even in this case, the TDDB life can be improved.

In the above description, the invention made mainly by the present inventor is described in the CMI, which is a field of application which is the background of the invention.
The case where the present invention is applied to a method of manufacturing a semiconductor integrated circuit device having an S circuit has been described. However, the present invention is not limited to this. For example, a dynamic random access memory (DRAM)
y), SRAM (Static Random Access Memory) or flash memory (EEPROM; Electric Erasable)
A semiconductor integrated circuit device having a memory circuit such as a programmable read only memory (RAM), a semiconductor integrated circuit device having a logic circuit such as a microprocessor, or a mixed type in which the memory circuit and the logic circuit are provided on the same substrate. The present invention can be applied to a method of manufacturing another semiconductor integrated circuit device such as a semiconductor integrated circuit device. The present invention is applicable to a semiconductor integrated circuit device, an electronic circuit device, an electronic device, a micromachine, or the like having at least a buried copper wiring structure.

[0131]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

That is, after a first atom for suppressing or preventing the diffusion of copper is solid-dissolved on the surface of the wiring mainly composed of copper formed in the wiring opening, an organic silane compound is used as a film forming gas. By including a step of depositing an insulating film over a wiring by a chemical vapor deposition method using a gas, stress migration failure of a semiconductor integrated circuit device having a wiring containing copper as a main component can be suppressed or prevented. For this reason, it is possible to improve the reliability of a semiconductor integrated circuit device having a wiring containing copper as a main component.

[Brief description of the drawings]

FIG. 1 is a plan view of a sample used for TDDB life measurement according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line B-B 'of FIG.

FIG. 3 is a sectional view taken along line C-C 'of FIG.

FIG. 4 is an explanatory diagram showing an outline of measurement when the sample of FIG. 1 is used.

FIG. 5 is a flowchart of a manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 6 is a plan view of a principal part during a manufacturing step of the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 7 is a sectional view taken along line X1-X1 of FIG. 6;

8 is a cross-sectional view of a part corresponding to the line X1-X1 in FIG. 6 during a manufacturing step of the semiconductor integrated circuit device subsequent to FIG. 6;

9 is a cross-sectional view of a part corresponding to the line X1-X1 of FIG. 6 during a manufacturing step of the semiconductor integrated circuit device subsequent to FIG. 8;

10 is a cross-sectional view of a part corresponding to the line X1-X1 of FIG. 6 during a manufacturing step of the semiconductor integrated circuit device subsequent to FIG. 9;

11 is a cross-sectional view of a portion corresponding to the line X1-X1 in FIG. 6 during a manufacturing step of the semiconductor integrated circuit device, following FIG. 10;

12 is a cross-sectional view of a part corresponding to the line X1-X1 in FIG. 6 during a manufacturing step of the semiconductor integrated circuit device subsequent to FIG. 11;

13 is a cross-sectional view of a portion corresponding to the line X1-X1 of FIG. 6 during a manufacturing step of the semiconductor integrated circuit device, following FIG. 12;

14 is a cross-sectional view of a portion corresponding to the line X1-X1 of FIG. 6 during a manufacturing step of the semiconductor integrated circuit device, following FIG. 13;

15 is a fragmentary plan view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 14;

16 is a sectional view taken along line X2-X2 in FIG.

17 is a cross-sectional view of a portion corresponding to the line X2-X2 of FIG. 15 during a manufacturing step of the semiconductor integrated circuit device subsequent to FIG. 15;

FIG. 18 is a graph showing a rate of increase in resistance in a hole connecting between wiring layers.

FIG. 19 is a graph showing the measured diffusion coefficient of copper when silicon is dissolved in the surface layer of the copper wiring.

FIG. 20 is a graph illustrating the measured diffusion coefficient of copper when oxygen is mixed into the surface layer of a copper wiring.

FIG. 21 is a flowchart showing a part of the manufacturing process of the semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 22 is a flowchart showing a part of the manufacturing process of the semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 23 shows C used for forming a buried wiring containing copper as a main component.
FIG. 2 is an explanatory diagram illustrating an example of an overall configuration of an MP apparatus.

FIG. 24 is an explanatory diagram of a CMP processing unit of the CMP apparatus of FIG. 23;

FIG. 25 is an explanatory diagram of a CMP processing unit of the CMP apparatus of FIG. 23;

FIG. 26 is a plan view of a principal part during a manufacturing step of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 27 is a sectional view of a main part of FIG. 26;

FIG. 28 is an essential part plan view of the semiconductor integrated circuit device during a manufacturing step following FIG. 26;

FIG. 29 is a sectional view of a main part of FIG. 28;

30 is a fragmentary plan view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 28;

FIG. 31 is a sectional view of a main part of FIG. 30;

FIG. 32 is a flowchart showing a part of the manufacturing process of the semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 33 is a fragmentary cross-sectional view of a wiring structure of a semiconductor integrated circuit device studied by the present inventors;

FIG. 34 is a fragmentary cross-sectional view of a wiring structure of a semiconductor integrated circuit device studied by the present inventors.

FIG. 35 is a fragmentary cross-sectional view of a wiring structure of a semiconductor integrated circuit device studied by the present inventors;

FIG. 36 is an explanatory diagram of a cause of void generation in a wiring structure of a semiconductor integrated circuit device studied by the present inventors.

[Explanation of symbols]

1W wafer 1S semiconductor substrate 2 Separation unit 3 Gate insulating film 4 Gate electrode 5 Sidewall 6,7 Semiconductor area 8 Insulating film 9 Contact hole 10 plugs 11a insulating film 11b insulating film 11c insulating film 11d insulating film 12a insulating film 12b insulating film 12c insulating film 12d insulating film 13 Through hole 14 Plug 15a insulating film 15b insulating film (second insulating film) 15c insulating film 15d insulating film (second insulating film) 16a Wiring groove (wiring opening) 16b Wiring groove (wiring opening) 17a Conductive barrier film (first conductive film) 17b Conductive barrier film (first conductive film) 18a Main conductor film (second conductor film) 18b Main conductor film (second conductor film) 19 Through hole (wiring opening) 31 CMP equipment 31a Polishing unit 31b Post-cleaning unit 31c1 First surface plate 31c2 2nd surface plate 31d clean station 31g rotating arm 31e loader 31f unloader 31h loader 31i1 First cleaning unit 31i2 Second cleaning unit 31j spin dryer 31k unloader 31n drive mechanism 31p polishing pad 31q drive mechanism 31r wafer carrier 31s wafer chuck 31t retainer ring 31u slurry supply pipe 31v drive mechanism 31w dresser 31m shading wall 50, 51 embedded wiring 52 Through Hole 53 Embedded wiring 54 void 55 Triple Point L Comb wiring M2 Second wiring layer P1, P2 pad S measurement stage H heater Qp p-channel type MIS • FET Qn n-channel type MIS • FET PWL p-type well NWL n-type well Sr slurry

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Noriko Miura             3 shares at 6-16 Shinmachi, Ome-shi, Tokyo             Hitachi, Ltd. Device Development Center F term (reference) 5F033 HH04 HH08 HH09 HH11 HH18                       HH19 HH23 HH25 HH27 HH32                       HH33 HH34 JJ19 JJ33 KK03                       KK08 KK09 KK18 KK25 KK27                       KK33 MM01 MM02 MM07 PP15                       PP27 PP28 QQ09 QQ10 QQ25                       QQ31 QQ37 QQ48 QQ91 RR04                       RR06 RR08 RR09 RR11 RR15                       RR21 SS11 SS15 SS21 XX06                       XX24                 5F048 AA01 AB03 AC01 AC03 BA01                       BE03 BF01 BF12 BF16 BF17                       BG14

Claims (35)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) depositing a first insulating film on a wafer; and (b) wiring openings in the first insulating film. Forming a wiring including a first conductive film having a barrier property against copper diffusion and a second conductive film containing copper as a main component in the wiring opening; and (d). A step of performing a reducing plasma treatment on the surface of the first insulating film and the wiring; (e) a first step of suppressing or preventing the diffusion of copper on the surface of the wiring;
And (f) depositing a second insulating film on the first insulating film and the wiring by a chemical vapor deposition method using an organic silane compound gas as a film forming gas. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein in the step (e), the first wiring is exposed to a gas containing an inorganic silane compound gas, so that the first wiring is exposed on a surface of the first wiring. A method for manufacturing a semiconductor integrated circuit device, characterized by dissolving silicon as an atom. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the inorganic silane compound gas in the step (e) is a monosilane gas. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the inorganic silane compound gas in the step (e) is disilane gas or dichlorosilane gas. . 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the solid solution amount of the first atom is an amount that does not change the crystal system of the second conductor film of the wiring. A method for manufacturing a semiconductor integrated circuit device. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the film forming gas in the step (f) includes a trimethylsilane gas as an organic silane compound gas, and the second insulating film is formed of silicon carbide or charcoal. A method for manufacturing a semiconductor integrated circuit device comprising an insulating film containing silicon nitride as a main component. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the film forming gas in the step (f) includes trimethoxysilane gas as the organic silane compound gas, and the second insulating film is oxynitrided. A method for manufacturing a semiconductor integrated circuit device comprising an insulating film containing silicon as a main component. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said reducing plasma processing is an ammonia plasma processing. 9. A method for manufacturing a semiconductor integrated circuit device, comprising: (a) depositing a first insulating film on a wafer; and (b) wiring openings in the first insulating film. Forming a wiring including a first conductive film having a barrier property against copper diffusion and a second conductive film containing copper as a main component in the wiring opening; and (d). A step of performing a reducing plasma treatment on the surface of the first insulating film and the wiring; (e) a first step of suppressing or preventing the diffusion of copper on the surface of the wiring;
(F) depositing a second insulating film on the first insulating film and the wiring by a chemical vapor deposition method using a deposition gas not containing an inorganic silane compound gas. 10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein in the step (e), the first wiring is exposed to a gas containing an inorganic silane compound gas, so that the first wiring is exposed on a surface of the first wiring. A method for manufacturing a semiconductor integrated circuit device, characterized by dissolving silicon as an atom. 11. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein the inorganic silane compound gas in the step (e) is a monosilane gas. 12. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein the inorganic silane compound gas in the step (e) is a disilane gas or a dichlorosilane gas. . 13. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein the film forming gas in the step (f) includes trimethylsilane gas as an organic silane compound gas.
The method of manufacturing a semiconductor integrated circuit device, wherein the second insulating film comprises an insulating film containing silicon carbide or silicon carbonitride as a main component. 14. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein the film forming gas in the step (f) includes a trimethoxysilane gas as the organic silane compound gas, and the second insulating film is oxynitrided. A method for manufacturing a semiconductor integrated circuit device comprising an insulating film containing silicon as a main component. 15. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) depositing a first insulating film on a wafer; and (b) forming a wiring opening in the first insulating film. Forming a wiring including a first conductive film having a barrier property against copper diffusion and a second conductive film containing copper as a main component in the wiring opening; and (d). A step of performing a reducing plasma treatment on the surface of the first insulating film and the wiring; (e) a first step of suppressing or preventing the diffusion of copper on the surface of the wiring;
(F) forming a second solution by a chemical vapor deposition method using a deposition gas containing an organic silane compound gas and not containing an inorganic silane compound gas on the first insulating film and the wiring; Depositing a film. 16. The method for manufacturing a semiconductor integrated circuit device according to claim 15, wherein in the step (e), the first wiring is exposed to a gas containing an inorganic silane compound gas, so that the first wiring is exposed on a surface of the first wiring. A method for manufacturing a semiconductor integrated circuit device, characterized by dissolving silicon as an atom. 17. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) depositing a first insulating film on a wafer; and (b) wiring openings in the first insulating film. Forming a wiring including a first conductive film having a barrier property against copper diffusion and a second conductive film containing copper as a main component in the wiring opening; and (d). Performing an ammonia plasma treatment on the surfaces of the first insulating film and the wiring, (e).
By exposing the wiring to an inorganic silane compound gas,
Dissolving silicon on the surface of the wiring; and (f) depositing a second insulating film on the first insulating film and the wiring by a chemical vapor deposition method using an organic silane compound gas as a film forming gas. . 18. The method for manufacturing a semiconductor integrated circuit device according to claim 17, wherein the inorganic silane compound gas in the step (e) is a monosilane gas. 19. The method for manufacturing a semiconductor integrated circuit device according to claim 17, wherein the inorganic silane compound gas in the step (e) is disilane gas or dichlorosilane gas. . 20. The method of manufacturing a semiconductor integrated circuit device according to claim 17, wherein the film forming gas in the step (f) includes a trimethylsilane gas as an organic silane compound gas, and the second insulating film is formed of silicon carbide or carbon. A method for manufacturing a semiconductor integrated circuit device comprising an insulating film containing silicon nitride as a main component. 21. The method for manufacturing a semiconductor integrated circuit device according to claim 17, wherein the film forming gas in the step (f) includes a trimethoxysilane gas as the organic silane compound gas, and the second insulating film is oxynitrided. A method for manufacturing a semiconductor integrated circuit device comprising an insulating film containing silicon as a main component. 22. A method of manufacturing a semiconductor integrated circuit device, comprising the following steps: (a) depositing a first insulating film on a wafer; and (b) wiring openings in the first insulating film. Forming a wiring including a first conductive film having a barrier property against copper diffusion and a second conductive film containing copper as a main component in the wiring opening; and (d). Performing an ammonia plasma treatment on the surfaces of the first insulating film and the wiring, (e).
By exposing the wiring to an inorganic silane compound gas,
Dissolving silicon on the surface of the wiring; and (f) depositing a second insulating film on the first insulating film and the wiring by a chemical vapor deposition method using a deposition gas not containing an inorganic silane compound gas. Process. 23. The method for manufacturing a semiconductor integrated circuit device according to claim 22, wherein the inorganic silane compound gas in the step (e) is a monosilane gas. 24. A method for manufacturing a semiconductor integrated circuit device, comprising: (a) depositing a first insulating film on a wafer; and (b) wiring openings in the first insulating film. Forming a wiring including a first conductive film having a barrier property against copper diffusion and a second conductive film containing copper as a main component in the wiring opening; and (d). A step of subjecting the first insulating film and the surface of the wiring to a hydrogen plasma treatment; (e) exposing the wiring to an inorganic silane compound gas to cause a solid solution of silicon on the surface of the wiring; (f) The first
Depositing a second insulating film on the insulating film and the wiring by a chemical vapor deposition method using an organic silane compound gas as a deposition gas; 25. The method for manufacturing a semiconductor integrated circuit device according to claim 24, wherein the inorganic silane compound gas in the step (e) is a monosilane gas. 26. A method of manufacturing a semiconductor integrated circuit device, comprising: (a) depositing a first insulating film on a wafer; and (b) forming a wiring opening in the first insulating film. Forming a wiring including a first conductive film having a barrier property against copper diffusion and a second conductive film containing copper as a main component in the wiring opening; and (d). A step of subjecting the first insulating film and the surface of the wiring to a hydrogen plasma treatment; (e) exposing the wiring to an inorganic silane compound gas to cause a solid solution of silicon on the surface of the wiring; (f) The first
Depositing a second insulating film on the insulating film and the wiring by a chemical vapor deposition method using a deposition gas containing no inorganic silane compound gas; 27. The method for manufacturing a semiconductor integrated circuit device according to claim 26, wherein the inorganic silane compound gas in the step (e) is a monosilane gas. 28. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) depositing a first insulating film on a wafer; and (b) wiring openings in the first insulating film. Forming a wiring including a first conductive film having a barrier property against copper diffusion and a second conductive film containing copper as a main component in the wiring opening; and (d). Performing a hydrogen plasma treatment on the surfaces of the first insulating film and the wiring, (e) performing an ammonia plasma treatment on the surfaces of the first insulating film and the wiring, and (f) applying the inorganic silane to the wiring. Exposing the silicon to a solid solution on the surface of the wiring by exposing it to a compound gas; (g) forming a silicon on the first insulating film and the wiring;
A step of depositing a second insulating film by a chemical vapor deposition method using an organic silane compound gas as a film forming gas. 29. The method for manufacturing a semiconductor integrated circuit device according to claim 28, wherein the inorganic silane compound gas in the step (f) is a monosilane gas. 30. A method of manufacturing a semiconductor integrated circuit device, comprising: (a) depositing a first insulating film on a wafer; and (b) wiring openings in the first insulating film. Forming a wiring including a first conductive film having a barrier property against copper diffusion and a second conductive film containing copper as a main component in the wiring opening; and (d). Performing a hydrogen plasma treatment on the surfaces of the first insulating film and the wiring, (e) performing an ammonia plasma treatment on the surfaces of the first insulating film and the wiring, and (f) applying the inorganic silane to the wiring. Exposing the silicon to a solid solution on the surface of the wiring by exposing it to a compound gas; (g) forming a silicon on the first insulating film and the wiring;
A step of depositing a second insulating film by a chemical vapor deposition method using a deposition gas not containing an inorganic silane compound gas. 31. The method for manufacturing a semiconductor integrated circuit device according to claim 30, wherein the inorganic silane compound gas in the step (f) is a monosilane gas. 32. A method of manufacturing a semiconductor integrated circuit device, comprising: (a) depositing a first insulating film on a wafer;
(B) forming a wiring opening in the first insulating film;
(C) forming, in the wiring opening, a wiring including a first conductive film having a barrier property against copper diffusion and a second conductive film containing copper as a main component; and (d) the first insulating film. And a step of performing a reducing plasma treatment on the surface of the wiring,
(E) depositing a second insulating film on the first insulating film and the wiring by a chemical vapor deposition method using an organic silane compound gas as a film forming gas; When the wiring after the reducing plasma treatment is exposed to the organic silane compound gas prior to the insulating film deposition processing, silicon in the organic silane compound gas causes the surface of the wiring after the reducing plasma processing to be exposed. A method of manufacturing the semiconductor integrated circuit device, wherein conditions for the reducing plasma treatment are set so that the solid solution is easily formed. 33. A method of manufacturing a semiconductor integrated circuit device, comprising: (a) depositing a first insulating film on a wafer;
(B) forming a wiring opening in the first insulating film;
(C) forming, in the wiring opening, a wiring including a first conductive film having a barrier property against copper diffusion and a second conductive film containing copper as a main component; and (d) the first insulating film. And a step of performing a reducing plasma treatment on the surface of the wiring,
(E) exposing the wiring to an inorganic silane compound gas to form a solid solution of silicon on the surface of the wiring;
(F) depositing a second insulating film on the first insulating film and the wiring by a chemical vapor deposition method using an organic silane compound gas as a film-forming gas; A semiconductor integrated circuit device, wherein conditions of the reducing plasma processing are set so that silicon in the inorganic silane compound gas is easily dissolved in the surface of the wiring after the reducing plasma processing. Manufacturing method. 34. A method of manufacturing a semiconductor integrated circuit device, comprising: (a) depositing a first insulating film on a wafer;
(B) forming a wiring opening in the first insulating film;
(C) forming, in the wiring opening, a wiring including a first conductive film having a barrier property against copper diffusion and a second conductive film containing copper as a main component; and (d) the first insulating film. And a step of performing a reducing plasma treatment on the surface of the wiring,
(E) exposing the wiring to an inorganic silane compound gas to form a solid solution of silicon on the surface of the wiring;
(F) depositing a second insulating film on the first insulating film and the wiring by a chemical vapor deposition method using a deposition gas containing an organic silane compound gas and not containing an inorganic silane compound gas. In the step (e), the conditions of the reducing plasma treatment are set so that silicon in the inorganic silane compound gas is easily dissolved in the surface of the wiring after the reducing plasma treatment. A method of manufacturing a semiconductor integrated circuit device. 35. A method for manufacturing a semiconductor integrated circuit device, comprising: (a) depositing a first insulating film on a wafer;
(B) forming a wiring opening in the first insulating film;
(C) forming, in the wiring opening, a wiring including a first conductive film having a barrier property against copper diffusion and a second conductive film containing copper as a main component; and (d) the first insulating film. And performing a plasma treatment on the surface of the wiring in an atmosphere containing ammonia gas and nitrogen gas, and (e) exposing the wiring to an inorganic silane compound gas to dissolve silicon on the surface of the wiring. , (F) the first
A step of depositing a second insulating film containing silicon carbonitride as a main component on the insulating film and the wiring by a chemical vapor deposition method using a deposition gas containing a trimethylsilane gas; A method of manufacturing a semiconductor integrated circuit device, wherein conditions of the plasma processing are set such that silicon in the inorganic silane compound gas is easily dissolved in the surface of the wiring after the plasma processing.