JP2008141204A - Manufacturing method of semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing technology of a semiconductor circuit device which improves the Cu diffusion preventing performance of Cu wiring. <P>SOLUTION: The upper surface of a silicon oxide film 39, the surface of the silicon oxide film 39 on side walls of a wiring groove 42, the upper surface of a silicon oxide film 31b on the bottom of the wiring groove 42, and the surface of the silicon oxide film 31b on side walls of a through hole 34, are subjected to the ammonia plasma treatment. Thereby, a thin silicon nitride film of, for example, 10 nm in thickness is formed. As a result, the film property, the cleanliness and the electric stability of the upper surface of the silicon oxide film 39, the surface of the silicon oxide film 39 on the side walls of the wiring groove 42, the upper surface of the silicon oxide film 31b on the bottom of the wiring groove 42 and the surface of the silicon oxide film 31b on the side walls of the through hole 34, can be improved; and the diffusion preventing performance of Cu can be improved. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a manufacturing technology of a semiconductor integrated circuit device, and more particularly to a technology effective when applied to a semiconductor integrated circuit device having a buried wiring having copper as a main conductive layer.

  As a technique for forming a wiring constituting a semiconductor integrated circuit device, a semiconductor device, an electronic circuit device or an electronic device, a conductive film such as aluminum or tungsten is deposited on an insulating film, and this is then used for a normal photo process. A technique for forming a wiring by patterning using a lithography technique and a dry etching technique has been established.

  However, in the wiring formation technology, as the elements and wirings constituting the semiconductor integrated circuit device and the like are miniaturized, the wiring resistance increases remarkably, resulting in wiring delay. As a result, the performance of the semiconductor integrated circuit device and the like is further improved. There is a limit in improving it. Therefore, in recent years, for example, a wiring formation technique called damascene has been studied. This damascene method can be broadly divided into a single-damascene method and a dual-damascene method.

  In the single damascene method, for example, after forming a wiring groove in an insulating film, a main conductive layer for wiring formation is deposited on the insulating film and in the wiring groove, and the main conductive layer is further subjected to, for example, chemical mechanical polishing. In this method, the embedded wiring is formed in the wiring groove by polishing so as to remain only in the wiring groove by a CMP (Chemical Mechanical Polishing) method.

  In the dual damascene method, a connection hole for connecting a wiring groove and a lower layer wiring is formed in an insulating film, and then a main conductive layer for wiring formation is deposited on the insulating film in the wiring groove and the connecting hole. Further, the main conductive layer is polished so as to remain only in the wiring groove and the connection hole by CMP or the like, thereby forming a buried wiring in the wiring groove and the connection hole.

  In any of the methods, a material having a low resistance such as copper is used as the main conductive layer material of the wiring from the viewpoint of improving the performance of the semiconductor integrated circuit device. Copper has the advantages that it has a lower resistance than aluminum and an allowable current in reliability that is two orders of magnitude greater. Therefore, since the film can be thinned to obtain the same wiring resistance, the capacitance between adjacent wirings can also be reduced.

  However, copper is considered to be easily diffused into the insulating film as compared with other metals such as aluminum and tungsten. For this reason, when copper is used as a wiring material, it has a thin conductivity to prevent copper diffusion on the surface (bottom surface and side surface) of the main conductive layer made of copper, that is, the inner wall surface (side surface and bottom surface) of the wiring groove. There is a need to form a barrier film. Further, by depositing a cap film made of, for example, a silicon nitride film so as to cover the upper surface of the embedded wiring over the entire upper surface of the insulating film in which the wiring trench is formed, the copper in the embedded wiring is embedded. There is a technique for preventing diffusion from the upper surface of the wiring into the insulating film.

  Such embedded wiring technology is described in, for example, Japanese Patent Laid-Open No. 10-154709 (Patent Document 1), and the embedded wiring is made of high-purity copper having an oxygen concentration or a sulfur concentration of 3 ppm or less. Thus, a technique for improving the burying property of a contact hole with a fine aspect ratio by promoting the surface diffusibility and fluidity of copper is disclosed.

  Further, for example, in Japanese Patent Application Laid-Open No. 11-87349 (Patent Document 2), after forming a wiring groove and a connection hole in an insulating film, copper is formed by sputtering using a target having a purity of 99.999 wt% (5N) or more. A technique for forming a film is disclosed. This publication also discloses a technique for forming a titanium nitride / titanium film as a barrier layer on the surfaces of wiring grooves and connection holes in order to facilitate copper embedding.

  For example, Japanese Patent Application Laid-Open No. 11-87509 (Patent Document 3) or Japanese Patent Application Laid-Open No. 11-220023 (Patent Document 4) discloses a technique for removing the barrier layer on the bottom surface of the via and reducing the resistance of the via. Has been.

Further, for example, in Japanese Patent Application Laid-Open No. 11-16912 (Patent Document 5), an oxide layer formed on a wiring portion exposed from the bottom of a connection hole is subjected to heat, plasma, or ultraviolet irradiation treatment in a reducing atmosphere. The technique which makes it disappear by giving is disclosed.
JP 10-154709 A JP 11-87349 A JP-A-11-87509 Japanese Patent Laid-Open No. 11-220023 Japanese Patent Laid-Open No. 11-16912

  However, according to the examination results of the present inventors, it has been found that the semiconductor integrated circuit device technology having the embedded wiring with copper as the main conductive layer has the following problems.

  That is, first, as the dimensions (width, thickness, distance from the center of the adjacent wiring to the center and the interval between the adjacent wiring) of the embedded wiring having copper as the main conductive layer are miniaturized, the wiring As a result of the relatively large cross-sectional area of the high-resistance conductive barrier film occupying the cross-sectional area, there is a problem that the resistance of the embedded wiring increases. For this reason, despite the use of copper as a wiring material for performance improvement, there arises a problem that the performance improvement of the semiconductor integrated circuit device is hindered.

  Second, in order to solve the first problem, the wiring resistance can be reduced by simply thinning or eliminating the barrier film without performing any technical treatment, but the diffusion of copper. As a result, there is a problem that the dielectric breakdown resistance between the embedded wirings adjacent to each other is significantly reduced. Therefore, there arises a problem that a highly reliable semiconductor integrated circuit device cannot be provided. In addition, the yield of the semiconductor integrated circuit device is reduced, resulting in a problem that the cost of the semiconductor integrated circuit device is increased.

  Third, when a silicon nitride film is used as a cap film on a buried wiring having copper as a main conductive layer, a silicide is formed at the interface between the copper and the silicon nitride film, and the resistance of the buried wiring is increased. is there. In addition, it has been found for the first time by the present inventors that this silicide is one of the main causes of copper diffusion as described later. For this reason, there is a problem that the performance improvement of the semiconductor integrated circuit device is hindered. Further, there arises a problem that the yield and reliability of the semiconductor integrated circuit device are significantly lowered.

  Fourth, there is a problem that peeling occurs between the wiring layer of the embedded wiring and the insulating film (for example, the cap film) formed in the upper layer. For this reason, there arises a problem that the yield and reliability of the semiconductor integrated circuit device are significantly lowered.

  Therefore, an object of the present invention is to provide a technique capable of reducing the resistance of a buried wiring having copper as a main conductive layer.

  Another object of the present invention is to provide a technique capable of improving the dielectric breakdown resistance between embedded wirings using copper as a main conductive layer.

  Another object of the present invention is to provide a technique capable of improving the adhesion between a wiring layer of a buried wiring having copper as a main conductive layer and a cap film.

  Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor integrated circuit device having an embedded wiring having copper as a main conductive layer.

  Another object of the present invention is to provide a technique capable of improving the yield of a semiconductor integrated circuit device having a buried wiring whose main conductive layer is copper.

  Another object of the present invention is to provide a technique capable of improving the performance of a semiconductor integrated circuit device having an embedded wiring whose main conductive layer is copper.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  1. The present invention relates to a buried wiring layer mainly composed of copper embedded in a recess formed in an insulating film through a conductive barrier layer, and a cap formed so as to cover the upper surface of the insulating film and the buried wiring layer. The concentration of components other than copper in the embedded wiring layer having an insulating film is 0.8 At. % Or less.

  2. In the item 1, the thickness of the thickest part or the thinnest part of the conductive barrier film is less than 10 nm in the side wall portion in the recess.

  3. In the item 1, the thickness of the thickest or thinnest portion of the conductive barrier film is set to 2 nm or less in the sidewall portion of the recess.

  4). The present invention according to item 1, wherein the conductive barrier film itself does not exist in the recess.

  5. According to the present invention, in the above item 1, the embedded metal wiring layer is in direct contact with the recessed portion.

  6). The present invention includes a step of forming a recess in an insulating film formed on a semiconductor substrate, a step of depositing a conductive barrier film on the insulating film including the inside of the recess, and copper on the conductive barrier film including the inside of the recess. A step of depositing a metal film having a main component, and a step of forming a buried metal wiring layer through the conductive barrier film in the recess by removing the metal film and the conductive barrier film, The concentration of components other than copper in the buried metal wiring layer at the time of completion of the semiconductor chip formed from the substrate is 0.8 At. The purity of the copper of the metal film is 99.999% or more when a metal film mainly composed of copper is formed in order to form the buried metal wiring layer.

  7. According to the present invention, in the item 6, the metal film is formed by a sputtering method using a target having a copper purity of 99.999% or more.

  8). According to the present invention, in the item 6, the metal film is formed by sputtering using a target having a copper purity of 99.9999% or more.

  9. According to the present invention, in the above item 6, after the metal film is removed by a chemical mechanical polishing method to form a buried wiring layer, the upper surfaces of the insulating film and the buried wiring layer are subjected to plasma in a reducing gas atmosphere. And a step of forming a cap insulating film on the insulating film and the buried metal wiring layer after the plasma processing.

  10. According to the present invention, in the above item 9, the reducing gas atmosphere includes hydrogen as a main component.

  11. According to the present invention, in the item 9, the reducing gas atmosphere further has a nitriding action.

  12 According to the present invention, in the item 9, the reducing gas atmosphere includes ammonia as a main component.

  13. According to the present invention, in the above item 9, the step of forming the embedded metal wiring layer by removing the metal film is performed by abrasive-free chemical mechanical polishing.

  14 In the item 9, the concentration of the component other than copper is 0.02 At. % Or less.

  15. In the item 9, the thickness of the thickest part or the thinnest part of the conductive barrier film is less than 10 nm in the side wall part in the recess.

  16. In the item 9, the thickness of the thickest or thinnest portion of the conductive barrier film is 2 nm or less in the side wall portion in the recess.

  17. The present invention includes a step of plasma-treating the semiconductor substrate in a reducing gas atmosphere prior to the step of depositing the conductive barrier film after forming the recess.

  18. The present invention includes a step of forming a recess in an insulating film formed on a semiconductor substrate, a step of depositing a metal film containing copper as a main component on the insulating film including the inside of the recess without using a conductive barrier film, And removing the metal film to form a buried metal wiring layer in the recess without a conductive barrier film, and the buried metal wiring layer at the time of completion of the semiconductor chip formed from the semiconductor substrate. The concentration of components other than copper at 0.8 At. %, And in order to form the buried metal wiring layer, the copper purity of the metal film at the time of forming the metal film containing copper as a main component is 99.999% or more.

  19. The present invention includes a step of forming a recess in an insulating film on a semiconductor substrate, a step of depositing a conductive barrier film on the insulating film including the recess, and copper as a main component on the conductive barrier film including the recess. A step of depositing a metal film, a step of forming a buried metal wiring layer through the conductive barrier film in the recess by removing the metal film and the conductive barrier film, on the insulating film and the buried metal wiring layer A damascene wiring forming step including a step of forming a cap insulating film, and the concentration of components other than copper in the embedded metal wiring layer at the time of completion of the semiconductor chip formed from the semiconductor substrate is set to 0.8 At. In order to form the buried metal wiring layer, the purity of the copper of the metal film at the time of forming the metal film mainly composed of copper is set to 99.999% or more.

  20. The present invention includes a step of forming a buried wiring groove and a connection hole in an insulating film on a semiconductor substrate, a step of depositing a conductive barrier film on the insulating film including the buried wiring groove and the connection hole, the buried wiring groove and the connection. A step of depositing a metal film containing copper as a main component on the conductive barrier film including the hole, and removing the metal film and the conductive barrier film so that the embedded wiring groove and the connection hole are interposed with the conductive barrier film. A dual damascene wiring forming step including a step of forming a buried metal wiring layer and a step of forming a cap insulating film on the insulating film and the buried metal wiring layer, and completing a semiconductor chip formed from the semiconductor substrate. The concentration of components other than copper in the buried metal wiring layer at the time is 0.8 At. In order to form the buried metal wiring layer, the purity of the copper of the metal film at the time of forming the metal film mainly composed of copper is set to 99.999% or more.

  21. According to the present invention, in the above item 20, after the formation of the buried wiring trench and the connection hole, prior to the step of depositing the conductive barrier film, the semiconductor substrate is subjected to a reducing gas atmosphere. It has the process of plasma-processing.

  22. According to the present invention, in the above item 20, after the step of forming the buried wiring layer by removing the metal film by a chemical mechanical polishing method, before the step of forming the cap insulating film, the insulating film and the buried wiring layer are formed. It has a process of plasma-treating the upper surface in a reducing gas atmosphere.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1). According to the present invention, the concentration of components other than copper in the buried wiring layer is 0.8 At. By setting the ratio to not more than%, it becomes possible to reduce the resistance of the embedded wiring mainly composed of copper.

  (2). According to the present invention, the thickness of the thickest portion of the conductive barrier film on the side wall in the recess is less than 10 nm, thereby reducing the resistance of the embedded wiring mainly composed of copper. It becomes.

  (3). According to the present invention, since the conductive barrier film itself does not exist in the concave portion, it is possible to reduce the resistance of the embedded wiring mainly composed of copper.

  (4). According to the present invention, the concentration of components other than copper in the buried wiring layer is 0.8 At. By setting the ratio to not more than%, it becomes possible to improve the dielectric breakdown resistance between embedded wirings mainly composed of copper.

  (5). According to the present invention, after the metal film is removed by a chemical mechanical polishing method to form a buried wiring layer, the upper surface of the insulating film and the buried wiring layer is subjected to plasma treatment in a reducing gas atmosphere. By having the step of forming a cap insulating film on the insulating film and the buried metal wiring layer after the plasma treatment, it becomes possible to improve the dielectric breakdown resistance between the buried wirings mainly composed of copper.

  (6). According to the present invention, after the metal film is removed by a chemical mechanical polishing method to form a buried wiring layer, the upper surface of the insulating film and the buried wiring layer is subjected to plasma treatment in a reducing gas atmosphere. And improving the adhesion between the wiring layer of the embedded wiring mainly composed of copper and the cap film by forming a cap insulating film on the insulating film and the embedded metal wiring layer after the plasma treatment. Is possible.

  (7). By the above (1) to (6), it becomes possible to improve the performance of the semiconductor integrated circuit device having the embedded wiring mainly composed of copper.

  (8). According to the above (4) to (6), it is possible to improve the reliability of the semiconductor integrated circuit device having the embedded wiring mainly composed of copper.

  (9). According to the above (4) to (6), it is possible to improve the yield of the semiconductor integrated circuit device having the embedded wiring mainly composed of copper.

  In describing embodiments of the present invention, the basic meaning of terms in the present application will be described as follows.

1. TDDB (Time Dependence on Dielectric Breakdown) life is a plot of the time from voltage application to dielectric breakdown against the applied electric field when a relatively high voltage is applied between the electrodes under a given temperature (eg 140 ° C) measurement condition. The time (life) obtained by creating an extrapolated graph and extrapolating from this graph to the actual electric field strength used (for example, 0.2 MV / cm). FIG. 85 shows a sample used for the TDDB lifetime measurement of the present application, (a) is a plan view, (b) and (c) are a BB ′ line cross section and a CC ′ line cross section in (a), respectively. Show. This sample can actually be formed in a TEG (Test Equipment Group) region of a semiconductor wafer. As shown in the figure, a pair of comb-shaped wirings L is formed in the second wiring layer M2 and connected to the uppermost pads P1 and P2. An electric field is applied between the comb-shaped wires L, and a current is measured. Pads P1 and P2 are measurement terminals. The wiring width, the wiring interval, and the wiring thickness of the comb-shaped wiring L are all 0.5 μm. The wiring facing length was 1.58 × 10 ⁵ μm. FIG. 86 is a conceptual diagram showing an outline of measurement. The sample is held on the measurement stage S, and a current / voltage measuring device (I / V measuring device) is connected between the pads P1 and P2. The sample stage S is heated by the heater H, and the sample temperature is adjusted to 140 ° C. FIG. 87 shows an example of the current-voltage measurement result. A case where the sample temperature is 140 ° C. and the electric field strength is 5 MV / cm is illustrated. The TDDB lifetime measurement includes a constant voltage stress method and a low current stress method. In this application, the constant voltage stress method is used in which the average electric field applied to the insulating film is constant. After voltage application, the current density decreases with time, and then a rapid current increase (dielectric breakdown) is observed. Here, the time when the leakage current density reached 1 μA / cm ² was defined as the TDDB life (TDDB life at 5 MV / cm). In the present application, the TDDB life means a breakdown time (life) at 0.2 MV / cm unless otherwise specified, but in a broad sense, after referring to a predetermined electric field strength, the term “TDDB life” is used as the time until breakdown. May be used. Unless otherwise specified, the TDDB lifetime refers to the case where the sample temperature is 140 ° C. Although the TDDB life is measured with the above-mentioned comb-shaped wiring L, it goes without saying that it actually reflects the breakdown life between the wirings.

  2. Plasma treatment means that the surface of a substrate or the surface of a member such as an insulating film or metal film is exposed to an environment in a plasma state and exposed to the chemical and mechanical (bombardment) of the plasma. ) Refers to the treatment by applying an action to the surface. In general, plasma is generated by ionizing a gas by the action of a high-frequency electric field while replenishing the processing gas as needed in a reaction chamber substituted with a specific gas (processing gas). It cannot be replaced. Therefore, in this application, for example, ammonia plasma is not intended to be complete ammonia plasma, but does not exclude the presence of impurity gases (nitrogen, oxygen, carbon dioxide, water vapor, etc.) contained in the plasma. Absent. Similarly, it goes without saying that the inclusion of other dilution gas or additive gas in the plasma is not excluded.

  Plasma in a reducing atmosphere refers to a plasma environment in which reactive species such as radicals, ions, atoms, and molecules having a reducing action, that is, an action of extracting oxygen, exist predominantly. In the form of radicals or ions. In addition, the environment may contain not only a single reactive species but also a plurality of reactive species. For example, an environment in which hydrogen radicals and NH 2 radicals exist simultaneously may be used.

  3. In the present application, the gas concentration refers to the flow rate ratio in the mass flow rate. That is, in the mixed gas of gas A and gas B, when the concentration of gas A is 5%, the mass flow rate of gas A is Fa, the mass flow rate of gas B is Fb, and Fa / (Fa + Fb) = 0.05 That means.

  4). Chemical mechanical polishing (CMP) is generally performed by moving the surface to be polished in contact with a polishing pad made of a relatively soft cloth-like sheet material or the like while moving the surface relatively while supplying slurry. In this application, in addition, CML (Chemical Mechanical Lapping) for polishing by moving the surface to be polished relative to the hard grindstone surface, using other fixed abrasive grains, and using abrasive grains Including non-abrasive-free CMP.

  Abrasive-free chemical mechanical polishing generally refers to chemical mechanical polishing using a slurry having an abrasive weight concentration of 0.5% or less. Abrasive chemical mechanical polishing is an abrasive weight concentration of 0.5%. This refers to chemical mechanical polishing using a higher concentration of slurry. However, these are relative, and when the polishing in the first step is abrasive-free chemical mechanical polishing and the subsequent polishing in the second step is abrasive chemical mechanical polishing, the polishing concentration in the first step is If the polishing concentration in the second step is one digit or more, preferably two digits or less, the first step polishing may be referred to as abrasive-free chemical mechanical polishing. In this specification, the term “abrasive-free chemical mechanical polishing” refers to the case where the entire unit flattening process of the target metal film is performed by abrasive-free chemical mechanical polishing, and the main process is abrasive-free chemical mechanical polishing. This includes the case where the secondary process is carried out by abrasive chemical mechanical polishing.

  5. The polishing liquid (slurry) generally refers to a suspension in which abrasive grains are mixed with a chemical etching agent. In the present application, a slurry in which abrasive grains are not mixed is included in the nature of the invention.

  Abrasive grains (slurry particles) generally refer to powders such as alumina and silica contained in the slurry.

  6). The anticorrosive agent is an agent that prevents or suppresses the progress of polishing by CMP by forming a protective film having corrosion resistance and / or hydrophobic properties on the surface of the metal. Generally, benzotriazole (BTA) and the like are used. Used (refer to Japanese Patent Laid-Open No. 8-64594 for details).

  7. The conductive barrier film is a diffusion barrier conductive film that is formed relatively thin on the side surface or bottom surface of the embedded wiring in order to prevent copper from diffusing into the interlayer insulating film or the lower layer. A refractory metal such as titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a nitride thereof is used.

  8). A buried wiring or a buried metal wiring is generally a single damascene or dual damascene or the like, after a conductive film is embedded in a trench formed in an insulating film and then on the insulating film. A wiring patterned by a wiring forming technique for removing an unnecessary conductive film. In general, single damascene refers to an embedded wiring process in which plug metal and wiring metal are embedded in two stages. Similarly, dual damascene generally refers to an embedded wiring process in which plug metal and wiring metal are embedded at once. In general, copper embedded wiring is often used in a multilayer configuration.

  9. The terms selective removal, selective polishing, selective etching, and selective chemical mechanical polishing all refer to those having a selection ratio of 5 or more.

  10. As for the selection ratio, when the selection ratio “A to B” (or “A to B”) is X, the polishing rate for A is calculated based on the polishing rate for B when the polishing rate is taken as an example. It means to become X when you do.

  11. In the present application, the term “semiconductor integrated circuit device” refers not only to a device manufactured on a single crystal silicon substrate, but also to an SOI (Silicon On Insulator) substrate or TFT (Thin Film Transistor) unless otherwise specified. It shall include those made on other substrates such as substrates for liquid crystal manufacturing. A wafer refers to a single crystal silicon substrate (generally substantially disk-shaped), an SOS substrate, a glass substrate, other insulating, semi-insulating or semiconductor substrates used in the manufacture of a semiconductor integrated circuit device, or a composite substrate thereof.

  12 A semiconductor integrated circuit wafer (semiconductor integrated circuit substrate) or a semiconductor wafer (semiconductor substrate) is a silicon or other semiconductor single crystal substrate (generally a substantially planar circular shape), sapphire substrate, glass substrate, etc. An insulating, anti-insulating or semiconductor substrate or the like and a composite substrate thereof. Note that part or all of the substrate surface or all or part of the gate electrode may be formed of another semiconductor such as SiGe.

  A semiconductor integrated circuit chip (semiconductor integrated circuit substrate) or a semiconductor chip (semiconductor substrate) refers to a semiconductor wafer that has been subjected to a wafer process divided into unit circuit groups.

13. The term “silicon nitride, silicon nitride, or silicon nitride film” includes not only Si ₃ N ₄ but also an insulating film having a similar composition of silicon nitride.

  14 The cap film is an insulating film having a high insulating property and diffusion barrier property formed other than the electrical connection portion of the embedded wiring information, and is generally formed of a material different from the main part of the interlayer insulating film, for example, a silicon nitride film. The

  15. Wafer process, also called pre-process, starts from the state of a mirror-polished wafer (mirror wafer), goes through the element and wiring formation process, forms a surface protection film, and finally can perform an electrical test with a probe This is the process up to.

  16. The coverage in the wiring groove (recess) or the connection hole (recess) of the conductive barrier film has side coverage and bottom coverage. FIG. 88 schematically shows a state in which a barrier film 62 is deposited by a sputtering method in the upper surface of the insulating film 60 and in the wiring groove 61 formed in the insulating film 60. The term “deposit film thickness of the barrier film” generally refers to the film thickness D 1 of the barrier film 62 on the upper surface of the insulating film 60. The side coverage refers to the coverage of the barrier film 62 at the side wall portion (including the corner portion at the intersection of the side surface and the bottom surface) in the wiring groove 61, and the film thickness D2 at that portion is the thinnest. Further, the bottom coverage refers to the covering property of the barrier film 62 on the bottom surface in the wiring groove 61, and the film thickness D3 at that portion is the second largest after the deposition film thickness. For example, according to the experimental results of the present inventors, when the barrier film is deposited in a wiring groove having an aspect ratio of 1, for example, by a normal sputtering method that does not particularly consider directivity, the deposition thickness of the barrier film is At 100 nm, the side coverage was about 30 nm and the bottom coverage was about 50 nm. Further, when the barrier film was deposited by the long throw sputtering method, the deposit film thickness of the barrier film was 100 nm, the side coverage was about 20 nm, and the bottom coverage was about 90 nm.

  17. The Long Throw Sputtering method is a method for improving bottom coverage. Only the vertical component of the sputtered particles reaches the substrate, so the target and the substrate are separated from each other, and stable discharge is performed at low pressure. This refers to the sputtering method.

  18. The collimated sputtering method inserts a grid-like plate between the target and the substrate so that a sufficient film thickness can be obtained up to the bottom when forming a film in a recess such as a wiring groove or connection hole with a large aspect ratio. And a sputtering method having a mechanism for forcibly increasing the vertical component.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

  In this embodiment, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is simply abbreviated as MIS, a p-channel type MISFET is abbreviated as pMIS, and an n-channel type MISFET is abbreviated as nMIS.

(Embodiment 1)
In the first embodiment, for example, the case where the present invention is applied to a method of manufacturing a CMOS (Complementary MOS) -LSI (Large Scale Integrated circuit) will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 1, an element isolation trench 2 having a depth of about 350 nm is formed on a semiconductor substrate (hereinafter referred to as a substrate) 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm. After forming using dry etching, a silicon oxide film 3 is deposited on the substrate 1 including the inside of the trench by a CVD method. Subsequently, the surface of the silicon oxide film 3 above the trench is planarized by chemical mechanical polishing (CMP). Thus, a trench type element isolation portion 2A (trench isolation) is formed. Thereafter, p-type well 4 and n-type well 5 are formed by ion implantation of p-type impurity (boron) and n-type impurity (for example, phosphorus) into substrate 1, and then substrate 1 is steam oxidized to form p A gate insulating film 6 having a thickness of about 6 nm is formed on the surfaces of the mold well 4 and the n-type well 5. The film thickness of the gate insulating film 6 here is a silicon dioxide equivalent film thickness and may not match the actual film thickness.

The gate insulating film 6 may be composed of a silicon oxynitride film instead of the silicon oxide film. Since the silicon oxynitride film has a higher effect of suppressing the generation of interface states in the film and reducing the number of electron traps compared to the silicon oxide film, the hot carrier resistance of the gate insulating film 6 can be improved. Resistance can be improved. In order to form the silicon oxynitride film, for example, the substrate 1 may be heat-treated in a nitrogen-containing gas atmosphere such as NO, NO ₂ or NH ₃ . Further, after the gate insulating film 6 made of silicon oxide is formed on the surface of each of the p-type well 4 and the n-type well 5, the substrate 1 is heat-treated in the nitrogen-containing gas atmosphere described above. The same effect as described above can also be obtained by segregating nitrogen at the interface.

  The gate insulating film 6 may be formed of, for example, a silicon nitride film or a composite insulating film of a silicon oxide film and a silicon nitride film. If the gate insulating film 6 made of silicon oxide is thinned to a silicon dioxide equivalent film thickness of less than 5 nm, particularly less than 3 nm, a decrease in the withstand voltage due to direct tunneling current generation or stress-induced hot carriers becomes obvious. Since the silicon nitride film has a higher dielectric constant than the silicon oxide film, the silicon dioxide equivalent film thickness is thinner than the actual film thickness. That is, when a silicon nitride film is provided, a capacity equivalent to that of a relatively thin silicon dioxide film can be obtained even if it is physically thick. Therefore, when the gate insulating film 6 is composed of a single silicon nitride film or a composite film of it and silicon oxide, the effective film thickness can be made larger than that of the gate insulating film composed of the silicon oxide film. Therefore, it is possible to improve the generation of tunnel leakage current and the reduction of dielectric strength due to hot carriers. Further, since the silicon oxynitride film is less likely to penetrate impurities than the silicon oxide film, the gate insulating film 6 is made of a silicon oxynitride film, so that the impurities in the gate electrode material can be diffused to the semiconductor substrate side. It is possible to suppress fluctuations in the threshold voltage due to.

  Here, the silicon dioxide equivalent film thickness (hereinafter also simply referred to as the equivalent film thickness) dr of the single insulating film or the composite insulating film is the relative dielectric constant εi of the target insulating film, the film thickness di, When the relative dielectric constant of silicon is εs, the film thickness is defined by the following equation.

For example, the dielectric constants of silicon oxide (SiO ₂ ) and silicon nitride (Si ₃ N ₄ ) are _{4 to} 4.2 and 8, respectively. Accordingly, when the dielectric constant of silicon nitride is calculated as twice the dielectric constant of silicon oxide, for example, the silicon nitride equivalent film thickness of a silicon nitride film having a film thickness of 6 nm is 3 nm. That is, the gate insulating film made of a silicon nitride film with a thickness of 6 nm and the gate insulating film made of a silicon oxide film with a thickness of 3 nm have the same capacitance. The capacitance of the gate insulating film made of a composite film of a silicon oxide film with a thickness of 2 nm and a silicon nitride film with a thickness of 2 nm (equivalent film thickness = 1 nm) is a gate insulation made of a single silicon oxide film with a thickness of 3 nm. It is the same as the capacity of the membrane.

Next, as shown in FIG. 2, a gate electrode 7 made of a low resistance polycrystalline silicon film, a WN (tungsten nitride) film and a W (tungsten) film is formed on the gate insulating film 6. The polycrystalline silicon film can be formed by CVD, and the WN film and W film can be formed by sputtering. The gate electrode 7 is formed by patterning these deposited films. The gate electrode 7 may be formed using a laminated film in which a W silicide film or a cobalt (Co) silicide film is deposited on a low resistance polycrystalline silicon film. Further, as the material of the gate electrode 7, an alloy of polycrystalline or single crystal silicon (Si) and germanium (Ge) may be used. After such a gate electrode 7 is formed, ion implantation is performed to form a low impurity concentration n ⁻ type semiconductor region 11 in the p type well 4 and a low impurity concentration p ⁻ type semiconductor region 12 in the n type well 5. Form.

Next, as shown in FIG. 3, for example, a silicon nitride film is deposited by the CVD method, and this is anisotropically etched to form sidewall spacers 13 on the side walls of the gate electrode 7. Thereafter, ion implantation is performed to form a high impurity concentration n ⁺ type semiconductor region 14 (source, drain) in the p type well 4 and a high impurity concentration p ⁺ type semiconductor region 15 (source) in the n type well 5. , Drain). An example of the n-type impurity is phosphorus or arsenic, and an example of the p-type impurity is boron. Thereafter, a surface of the n ⁺ type semiconductor region 14 (source, drain) and the p ⁺ type semiconductor region are deposited using a so-called salicide method in which a metal film such as titanium or cobalt is deposited and an unreacted metal film is removed after the heat treatment. A silicide layer 9 is formed on the surface of 15 (source, drain). The n-channel type MISFET Qn and the p-channel type MISFET Qp are completed through the steps so far.

Next, as shown in FIG. 4, a silicon oxide film 18 is deposited on the substrate 1 by a CVD method, and then the silicon oxide film 18 is dry-etched using the photoresist film as a mask, thereby forming an n ⁺ type semiconductor region. A contact hole 20 is formed above 14 (source, drain), and a contact hole 21 is formed above p ⁺ -type semiconductor region 15 (source, drain). At this time, a contact hole 22 is also formed on the gate electrode 7.

  The silicon oxide film 18 is formed of a highly reflowable film that can embed a narrow space between the gate electrodes 7 and 7, for example, a BPSG (Boron-doped Phospho Silicate Glass) film. Moreover, you may comprise with the SOG (Spin On Glass) film | membrane formed by a spin coating method.

  Next, plugs 23 are formed inside the contact holes 20, 21, 22. In order to form the plug 23, for example, after depositing a TiN film and a W film on the silicon oxide film 18 including the insides of the contact holes 20, 21, and 22 by the CVD method, unnecessary TiN on the silicon oxide film 18 is formed. The film and the W film are removed by a chemical mechanical polishing (CMP) method or an etch back method, and these films are left only inside the contact holes 20, 21, and 22.

Next, as shown in FIG. 5, W wirings 24 to 30 serving as first-layer wirings are formed on the silicon oxide film 18. In order to form the W wirings 24 to 30, for example, a W film is deposited on the silicon oxide film 18 by sputtering, and then this W film is dry-etched using the photoresist film as a mask. The W wirings 24 to 30 of the first layer are connected to the source and drain (n ⁺ type semiconductor region) of the n channel type MISFET Qn and the source and drain (p ⁺ type semiconductor region) of the p channel type MISFET Qp through the contact holes 20, 21 and 22. ) Or the gate electrode 7 is electrically connected.

  Next, as shown in FIGS. 6A and 6B, a silicon oxide film 31 is deposited on top of the first-layer W wirings 24 to 30, followed by dry etching using the photoresist film as a mask. After through holes 32 to 36 are formed in the silicon oxide film 31, plugs 37 are formed inside the through holes 32 to 36. 6A is a plan view of a main part of the main surface of the semiconductor substrate, and FIG. 6B is a cross-sectional view taken along line AA in FIG.

  The silicon oxide film 31 is deposited by a plasma CVD method using, for example, ozone (or oxygen) and tetraethoxysilane (TEOS) as a source gas. The plug 37 is made of, for example, a W film, and is formed by the same method as the method of forming the plug 23 in the contact holes 20, 21, 22.

  Next, as shown in FIGS. 7A and 7B, a thin silicon nitride film 38 having a film thickness of 50 nm is deposited on the silicon oxide film 31 by plasma CVD, and then on the silicon nitride film 38. A silicon oxide film 39 having a thickness of about 450 nm is deposited by plasma CVD. Thereafter, the silicon oxide film 39 and the silicon nitride film 38 above the through holes 32 to 36 are removed by dry etching using the photoresist film as a mask, and wiring grooves 40 to 44 are formed. 7A is a plan view of the main part of the main surface of the semiconductor substrate, and FIG. 7B is a cross-sectional view taken along line AA in FIG.

  In order to form the wiring grooves 40 to 44, first, the silicon oxide film 39 is selectively etched using the silicon nitride film 38 as an etching stopper, and then the silicon nitride film 38 is etched. In this way, a thin silicon nitride film 38 is formed below the silicon oxide film 39 in which the wiring grooves 40 to 44 are formed. After the etching is temporarily stopped on the surface of the silicon nitride film 38, the silicon nitride film 38 is formed. The depth of the wiring grooves 40 to 44 can be accurately controlled without etching the wiring grooves 40 to 44.

  Next, a buried Cu wiring serving as a second-layer wiring is formed in the wiring grooves 40 to 44 by the following method.

  First, as shown in FIG. 8, a thin TiN (titanium nitride) film 45 is deposited on the upper portion of the silicon oxide film 39 including the inside of the wiring grooves 40 to 44 by sputtering, and then the wiring groove is formed on the TiN film 45. A Cu film 46 having a film thickness (for example, about 800 nm) sufficiently thicker than the depth of 40 to 44 is deposited by sputtering. The sputtering method for the TiN film 45 and the Cu film 46 may be a normal sputtering method or a sputtering method with high directivity such as a long throw sputtering method or a collimated sputtering method.

  Subsequently, the Cu film 46 is reflowed by heat-treating the substrate 1 in a non-oxidizing atmosphere (for example, hydrogen atmosphere) at about 475 ° C., for example, and the Cu film 46 is embedded in the wiring grooves 40 to 44 without any gap. Although the Cu film 46 by the sputtering method and the subsequent reflow embedding have been described here, a thin Cu film is formed by the sputtering method, and then a high-purity Cu film corresponding to the Cu film 46 is formed by the plating method. It may be formed.

  The TiN film 45 has a function of preventing the diffusion of Cu. The TiN film 45 has a function of improving the adhesion between the Cu film 46 and the silicon oxide film 39. Further, the TiN film 45 has a function of improving the wettability of the Cu film 46 when the Cu film 46 is reflowed.

  In the first embodiment, the case where the thickness of the thickest portion of the TiN film 45 is 50 nm is exemplified. However, according to the examination results of the present inventors, the TiN film 45 is further thinned or eliminated. It turns out that you can also. This will be described later in the sixth embodiment.

  As a film having such a function, it is preferable to use refractory metal nitrides such as WN and TaN (tantalum nitride) that hardly react with Cu instead of TiN. Further, instead of TiN, a material obtained by adding Si (silicon) to a refractory metal nitride, or a refractory metal such as Ta, Ti, W, or TiW alloy that hardly reacts with Cu can be used.

  Next, the Cu film 46 and the TiN film 45 are polished by the CMP method or the like. An example of the overall configuration of the CMP apparatus used in this polishing process is shown in FIG.

  The CMP apparatus 100 is a single-wafer type CMP apparatus used for polishing the Cu film 46. The loader 120 accommodates a plurality of substrates 1 having a Cu film 46 formed on the surface, and the Cu film 46 is polished and planarized. The surface of the polished substrate 130, the surface of the substrate 1 that has been polished, and the surface of the substrate 1 that has been subjected to the corrosion treatment, and the substrate 1 that has been subjected to the anticorrosion treatment are kept dry before being cleaned. An immersion processing unit 150, a post-cleaning processing unit 160 for post-cleaning the substrate 1 that has been subjected to the anticorrosion treatment, and an unloader 170 that accommodates a plurality of substrates 1 that have been post-cleaned are provided.

  As shown in FIG. 10, the polishing processing unit 130 of the CMP apparatus 100 includes a housing 101 having an upper opening, and a motor 103 is disposed at the upper end of the rotating shaft 102 attached to the housing 101. A polishing disk (platen) 104 that is driven by rotation is attached. A polishing pad 105 formed by evenly attaching a synthetic resin having a large number of pores is attached to the surface of the polishing board 104.

  In addition, the polishing processing unit 130 includes a wafer carrier 106 for holding the substrate 1. The drive shaft 107 to which the wafer carrier 106 is attached is rotated and driven integrally with the wafer carrier 106 by a motor (not shown), and is moved up and down above the polishing board 104.

  The substrate 1 is held on the wafer carrier 106 by a vacuum suction mechanism (not shown) provided on the wafer carrier 106 with its main surface, that is, the surface to be polished facing downward. A concave portion 106 a for accommodating the substrate 1 is formed at the lower end portion of the wafer carrier 106. When the substrate 1 is accommodated in the concave portion 106 a, the surface to be polished is almost the same as the lower end surface of the wafer carrier 106 or slightly. It will be in the state of protruding.

  Above the polishing board 104, a slurry supply pipe 108 for supplying a polishing slurry (S) is provided between the surface of the polishing pad 105 and the surface to be polished of the substrate 1, and supplied from the lower end thereof. The surface to be polished of the substrate 1 is chemically and mechanically polished by the polishing slurry (S). As the polishing slurry (S), for example, an abrasive such as alumina and an oxidizing agent such as aqueous hydrogen peroxide or aqueous ferric nitrate and the like dispersed or dissolved in water are used.

  Further, the polishing processing unit 130 includes a dresser 109 that is a tool for shaping (dressing) the surface of the polishing pad 105. The dresser 109 is attached to a lower end portion of a drive shaft 110 that moves up and down above the polishing board 104 and is driven to rotate by a motor (not shown).

  The substrate 1 that has been polished is subjected to a corrosion prevention treatment on the surface thereof in the corrosion prevention treatment unit 140. The anticorrosion processing unit 140 has a configuration similar to the configuration of the above-described polishing processing unit 130. Here, the main surface of the substrate 1 is first pressed against a polishing pad attached to the surface of a polishing board (platen) for polishing. After the slurry is mechanically removed, a surface of the Cu wiring formed on the main surface of the substrate 1 is supplied by supplying a chemical solution containing a corrosion inhibitor such as benzotriazole (BTA) to the main surface of the substrate 1. A hydrophobic protective film is formed on the portion.

  For example, as shown in FIG. 11, mechanical polishing (pre-cleaning) of the polishing slurry is a cylindrical shape made of a porous body of a synthetic resin such as PVA (polyvinyl alcohol) on both sides of the substrate 1 rotated in a horizontal plane. The both surfaces of the substrate 1 are simultaneously cleaned while being sandwiched between the brushes 121A and 121B and rotating the brushes 121A and 121B in a plane perpendicular to the surface of the substrate 1. In addition, in the anticorrosion treatment after the pre-cleaning, polishing is performed by performing pure water scrub cleaning, pure water ultrasonic cleaning, pure water running water cleaning or pure water spin cleaning, etc. in advance or in parallel with the anticorrosion treatment as necessary. The processing unit 130 sufficiently removes the oxidizing agent in the polishing slurry adhering to the main surface of the substrate 1, and forms a hydrophobic protective film under conditions where the oxidizing agent does not substantially act.

  The substrate 1 that has been subjected to the anticorrosion treatment is temporarily stored in the immersion treatment unit 150 in order to prevent the surface from drying. The immersion treatment unit 150 is for maintaining the surface of the substrate 1 after the anticorrosion treatment is finished so that the substrate 1 is not dried. For example, in the immersion tank (stocker) in which pure water is overflowed. A predetermined number of substrates 1 are immersed and stored. At this time, corrosion of the Cu wirings 28 to 30 is more reliably prevented by supplying pure water cooled to such a low temperature that the electrochemical corrosion reaction of the Cu wirings 28 to 30 does not substantially proceed. can do.

  Prevention of drying of the substrate 1 may be performed by a method other than storage in the immersion bath as long as at least the surface of the substrate 1 can be maintained in a wet state, such as supply of a pure water shower. .

  The substrate 1 transported to the post-cleaning processing unit 160 is immediately subjected to post-cleaning in a state where the surface of the substrate 1 is kept wet. Here, scrub cleaning (or brush cleaning) is performed on the surface of the substrate 1 while supplying a weak alkaline chemical solution such as a cleaning solution containing NH 4 OH to neutralize the oxidizing agent, and then an aqueous hydrofluoric acid solution is applied to the surface of the substrate 1. Supply and remove foreign particles by etching. Prior to or in parallel with the scrub cleaning described above, the surface of the substrate 1 is subjected to pure water scrub cleaning, pure water ultrasonic cleaning, pure water running water cleaning or pure water spin cleaning, and the back surface of the substrate 1 is subjected to pure water scrub cleaning. You may do it.

  The substrate 1 that has been subjected to the post-cleaning process is rinsed with pure water and spin-dried, then accommodated in the unloader 170 in a dry state, and conveyed to the next step in a batch of a plurality of sheets.

  In addition, as shown in FIG. 12, the immersion process part (wafer storage part) 150 for preventing the surface drying of the board | substrate 1 which the corrosion-proof process was complete | finished is made into a light-shielding structure, and illumination light etc. are irradiated to the surface of the board | substrate 1 in storage Can be prevented. Thereby, generation | occurrence | production of the short circuit current by a photovoltaic effect can be prevented. In order to make the immersion treatment unit 150 have a light shielding structure, specifically, the illuminance inside the immersion tank (stocker) is at least 500 lux, preferably by covering the periphery of the immersion tank (stocker) with a light shielding sheet or the like. 300 lux or less, more preferably 100 lux or less.

  Further, as shown in FIG. 13, immediately after the polishing process, that is, immediately before the electrochemical corrosion reaction by the oxidant in the polishing slurry remaining on the surface is started, it is immediately transferred to the drying processing unit, where the polishing slurry contains Moisture may be removed by forced drying. A CMP apparatus 200 shown in FIG. 13 includes a loader 220 that accommodates a plurality of substrates 1 having a Cu film formed on the surface, a polishing processing unit 230 that polishes and flattens the Cu film to form wiring, and the substrate 1 that has been polished. A drying processing unit 240 for drying the surface of the substrate, a post-cleaning processing unit 250 for post-cleaning the substrate 1, and an unloader 260 for storing a plurality of substrates 1 after the post-cleaning. In the Cu wiring formation process using the CMP apparatus 200, the substrate 1 subjected to the polishing process in the polishing processing unit 230 is subjected to electrochemical corrosion immediately after the polishing process, that is, with an oxidizing agent in the polishing slurry remaining on the surface. Immediately before the reaction is started, it is transported to the drying processing unit 240, and moisture in the polishing slurry is removed by forced drying. Thereafter, the substrate 1 is transported to the post-cleaning processing unit 250 while being kept in a dry state, subjected to post-cleaning processing, and then accommodated in the unloader 260 through pure water rinsing and spin drying. In this case, since the surface of the substrate 1 is kept in a dry state immediately after the polishing process and after the post-cleaning is started, the start of the electrochemical corrosion reaction is suppressed, whereby the corrosion of the Cu wiring is suppressed. Can be effectively prevented.

  Through such a polishing process by the CMP method, the Cu film 46 and the TiN film 45 on the silicon oxide film 39 are removed, and Cu wirings 46a to 46e are formed in the wiring grooves 40 to 44 as shown in FIG. .

  Next, plasma processing is performed on the surfaces of the Cu wirings 46 a to 46 e and the silicon oxide film 39. FIG. 15 is a cross-sectional view (a) and a plan view (b) showing an example of a processing apparatus used for plasma processing. This plasma treatment is described in Japanese Patent Application No. 11-226876 by the present inventors.

  In this processing apparatus, two processing chambers 302 a and 302 b and a cassette interface 303 are attached to a load lock chamber 301. The load lock chamber 301 has a robot 304 for transporting the substrate 1. A gate valve 305 is provided between the load lock chamber 301 and the processing chambers 302a and 302b so that a high vacuum state in the load lock chamber 301 can be maintained even during processing.

  In the processing chambers 302 a and 302 b, a susceptor 306 that holds the substrate 1, a baffle plate 307 that adjusts the gas flow, a support member 308 that supports the susceptor 306, a mesh electrode 309 disposed opposite the susceptor 306, and a baffle plate 307 has an insulating plate 310 disposed substantially opposite to 307. The insulating plate 310 has an effect of suppressing parasitic discharge in an unnecessary region other than between the susceptor 306 and the electrode 309. A lamp 312 installed in the reflection unit 311 is disposed on the back side of the susceptor 306, and an infrared ray 313 emitted from the lamp 312 passes through the quartz window 314 and is irradiated to the susceptor 306 and the substrate 1. Thereby, the substrate 1 is heated. The substrate 1 is placed face up on the susceptor 306.

  The inside of the processing chambers 302 a and 302 b can be evacuated to a high vacuum, and processing gas and high-frequency power are supplied from the gas port 315. The processing gas passes through the mesh electrode 309 and is supplied to the vicinity of the substrate 1. The processing gas is discharged from the vacuum manifold 316, and the pressure is controlled by controlling the supply flow rate and the exhaust speed of the processing gas. High frequency power is applied to the electrode 309 and generates plasma between the susceptor 306 and the electrode 309. The high frequency power uses a frequency of 13.56 MHz, for example.

  In the processing chamber 302a, for example, ammonia plasma processing described below is performed. In the processing chamber 302b, a cap film (silicon nitride film) described later is deposited. Since the processing chamber 302a and the processing chamber 302b are connected via the load lock chamber 301, the substrate 1 can be transferred to the processing chamber 302b without breaking the vacuum after the ammonia plasma processing. The film can be formed continuously.

  Next, ammonia plasma treatment is performed on the substrate 1 using the plasma treatment apparatus described above. The substrate 1 is carried into the load lock chamber 301 by the robot 304 from the cassette interface 303. The load lock chamber 301 is evacuated to a sufficiently reduced pressure, and the substrate 1 is transferred to the processing chamber 302a using the robot 304. After closing the gate valve 305 of the processing chamber 302a and evacuating the processing chamber 302a to a sufficient degree of vacuum, ammonia gas is introduced into the processing chamber 302a, and the pressure is adjusted to maintain a predetermined pressure. Thereafter, an electric field is applied to the electrode 309 from a high-frequency power source, and the surface of the substrate 1 is subjected to plasma treatment as shown in FIG. After the elapse of a predetermined time, the high frequency electric field is stopped and the plasma is stopped. Thereafter, the inside of the processing chamber 302 a is evacuated, the gate valve 305 is opened, and the substrate 304 is carried out to the load lock chamber 301 by the robot 304. Since the load lock chamber 301 is maintained in a high vacuum state, the surface of the substrate 1 is not exposed to the air atmosphere.

As for the plasma processing conditions, for example, when the size of the substrate 1 is 8 inches (= about 20 cm), the processing pressure is 5.0 Torr (= 6.6661 × 10 ² Pa), the RF power is 600 W, and the substrate temperature is 400 ° C. The ammonia flow rate can be 200 sccm and the treatment time can be 10 seconds. The distance between the electrodes was 600 mils. Of course, the plasma processing conditions are not limited to these exemplified conditions. According to the study by the present inventors, the plasma damage can be reduced as the pressure is increased, and the variation in the TDDB lifetime in the substrate is reduced and the lifetime is increased as the substrate temperature is increased. Further, it has been found that hillocks are more likely to occur on the surface of Cu as the substrate temperature is higher, the RF power is higher, and the treatment time is longer. Considering these findings and the variation in conditions depending on the apparatus configuration, the processing pressure is 0.5 to 6 Torr (= 0.66661 × 10 ^{2 to} 7.99932 × 10 ² Pa), the RF power is 300 to 600 W, and the substrate temperature is 350 to 450 ° C., the ammonia flow rate is 20 to 500 sccm, the treatment time is 5 to 180 seconds, and the distance between the electrodes can be set in the range of 300 to 600 mils.

  In this way, by performing plasma treatment on the surfaces of the Cu wirings 46 a to 46 e and the silicon oxide film 39, nitride films of the respective base materials are formed in very thin regions on the surfaces of the Cu wirings 46 a to 46 e and the silicon oxide film 39. can do. As a result, the adhesion between the cap film (silicon nitride film) described below, the Cu wirings 46a to 46e, and the silicon oxide film 39 is improved, and the TDDB life can be remarkably improved. This point will be described in detail later together with the analysis of the experimental results of the inventors.

  Next, the substrate 1 is transferred to the processing chamber 302b using the robot 304. After closing the gate valve 305 of the processing chamber 302b and exhausting the processing chamber 302b to a sufficient degree of vacuum, a mixed gas of silane (SiH4), ammonia, and nitrogen is introduced into the processing chamber 302b to adjust the pressure. Maintain a predetermined pressure. Thereafter, an electric field is applied from the high frequency power source to the electrode 309 to generate plasma, and a silicon nitride film 47 (cap film) is deposited on the surfaces of the Cu wirings 46a to 46e and the silicon oxide film 39 as shown in FIG. After the elapse of a predetermined time, the high frequency electric field is stopped and the plasma is stopped. Thereafter, the inside of the processing chamber 302 b is evacuated, the gate valve 305 is opened, and the substrate 1 is carried out to the load lock chamber 301 by the robot 304. Further, the substrate 1 is discharged to the cassette interface 303 using the robot 304.

  The film thickness of the silicon nitride film 47 is 50 nm, for example. Thereafter, a silicon oxide film for forming a plug for connecting the third-layer wiring and the second-layer wiring (Cu wirings 46a to 46e) is formed, and the third method is performed in the same manner as described above. Embedded Cu wirings after the first layer are formed. FIG. 18 is an overall flow diagram of the formation process of the Cu wirings 46a to 46e described above.

  FIG. 19 shows an example of a CMOS-LSI in which the wiring up to the seventh layer is formed. The first layer wiring (M1) is made of a tungsten film as described above. The film thickness and the wiring pitch of the first layer wiring (distance from the center of the adjacent wiring to the center) are, for example, about 0.4 μm or about 0.25 μm.

  The second layer wiring (M2) to the fifth layer wiring (M5) are manufactured by the above-described Cu wiring forming method. The thickness of the TiN film of the second layer wiring (M2) and the third layer wiring (M3) is, for example, about 0.05 μm, the thickness of the Cu film is, for example, about 0.35 μm, and the wiring width and wiring pitch are, for example, It is about 0.5 μm or about 0.25 μm. The thickness of the TiN film of the fourth layer wiring (M4) and the fifth layer wiring (M5) is, for example, about 0.05 μm, the thickness of the Cu film is, for example, about 0.95 μm, and the wiring width and wiring pitch are, for example, It is about 1.0 μm or about 0.25 μm.

  The sixth layer wiring (M6) has a three-layer structure of, for example, a tungsten film, an aluminum film, and a tungsten film. The seventh layer wiring (M7) is made of, for example, an aluminum film. A bump electrode or a bonding wire is connected to the pad of the seventh layer wiring (M7), but the illustration is omitted. As one of the reasons why the seventh layer wiring (M7) is composed of a laminated film of aluminum and tungsten, the laminated film is used as the uppermost layer of a normal semiconductor integrated circuit device that does not employ a damascene wiring structure. This is because it has been empirically proved that reliability in connection with bump electrodes and bonding wires can be secured.

  The diameter of the through hole connecting the first layer wiring M1 and the second layer wiring M2 is, for example, about 0.45 μm or about 0.25 μm. The diameter of the through hole connecting the second layer wiring M2 and the third layer wiring M3 is, for example, about 0.5 μm or about 0.25 μm. The diameter of the through hole connecting the third layer wiring M3 and the fourth layer wiring M4 is, for example, about 0.5 μm or about 0.25 μm. The diameter of the through hole connecting the fourth layer wiring M4 and the fifth layer wiring M5 is, for example, about 1.0 μm or about 0.25 μm. The diameter of the through hole connecting the fifth layer wiring M5 and the sixth layer wiring M6 is, for example, about 0.5 μm or about 0.25 μm.

  According to the present embodiment, the TDDB life is significantly improved. FIG. 20 is a graph showing the TDDB life of the TEG sample formed in the same layer as the second layer wiring M2 (Cu wirings 46a to 46e) of the present embodiment. Shown in For comparison, TDDB life data (line Ref) when ammonia plasma treatment is not performed are also shown. As is apparent from the figure, in this embodiment, the life is improved by about 6 digits compared to the comparison data.

  FIG. 21 shows data (line B) when the silicon oxide film 39 applied in this embodiment is replaced with a denser and stronger silicon nitride film. Even when the insulating film is replaced with silicon nitride, there is no difference from the case where the insulating film is a silicon oxide film unless the ammonia plasma treatment is performed (line Ref). On the other hand, when a silicon nitride film is applied to the insulating film and ammonia plasma treatment is performed, the TDDB life is improved as compared with the present embodiment. However, the rate of improvement is not large, and it can be seen that the factor due to the ammonia plasma treatment is more dominant. This indicates that the factor governing the TDDB lifetime is dominated by the interface rather than the bulk of the insulating film.

  Therefore, the present inventors conducted surface analysis of copper and silicon oxide films in order to analyze the mechanism by which the TDDB life is improved by the ammonia plasma treatment. The results of the analysis will be described below.

  22 to 24 are graphs showing the results of XPS (X-ray Photo-electron Spectroscopy) analysis of the Cu wiring surface. In each figure, (a) and (c) show the spectral results of Cu2p, and (b) and (d) show the spectral results of N1s.

  FIGS. 22A and 22B show the results of analysis of the as-deposited Cu film surface. Since the Cu2p peak is observed and the N1s peak is a noise level, it can be seen that nitrogen is not present in the as-deposited Cu film. 22C and 22D show the results of analysis of the Cu wiring surface immediately after the CMP of the Cu film only. The N1s peak is observed together with the Cu2p peak. As described above, since BTA is contained in the slurry, it can be assumed that nitrogen in BTA remaining on the Cu surface is observed. FIGS. 23A and 23B show the results of analysis of the Cu wiring surface in a state where the post-cleaning is performed after the CMP. Although no change is observed in the Cu2p peak, the N1s peak is lowered. It is thought that BTA was removed by washing. 23 (c) and 23 (d) show the results of analysis of the Cu wiring surface in a state where it is left in the air atmosphere after post-cleaning for 24 hours. A CuO peak is observed together with a Cu2p peak. The N1s peak is not changed by standing. It can be seen that the Cu surface was oxidized by being left and CuO was produced.

  FIGS. 24A and 24B show results obtained by analyzing the surface of the Cu wiring in a state where the ammonia wiring is applied to the oxidized Cu wiring. The CuO peak has almost disappeared. On the other hand, the N1s peak is strongly generated. It is considered that the Cu surface is reduced and oxygen is extracted and the surface is nitrided. For comparison, the surface of the Cu wiring in a state where the oxidized Cu wiring was subjected to hydrogen heat treatment at 350 ° C. was analyzed. The results are shown in FIGS. 24 (c) and 24 (d). When the Cu2p peak is compared with FIG. 24C and FIG. 24A, it is closer to the as-deposited state (FIG. 22A), and therefore it is considered that the hydrogen heat treatment is more reducible. On the other hand, since almost no N1s peak is observed, the hydrogen heat treatment only reduces the Cu surface.

  From the above results, it can be seen that the surfaces of the Cu wirings 46a to 46e are reduced and a nitride layer is formed by the ammonia plasma treatment. This nitride layer is considered to have a function of preventing the reaction between silane and copper contained in the source gas when depositing the silicon nitride film after the ammonia plasma treatment and suppressing the formation of copper silicide. Prevention of silicide formation has the effect of suppressing an increase in wiring resistance.

  FIG. 25 is a graph showing the results of XPS analysis of the silicon oxide film surface, and FIGS. 26 and 27 are graphs showing the results of mass analysis (TDS-APIMS) of the silicon oxide film. In the analysis of the silicon oxide film, the state after cleaning after CMP (profile C), the state after hydrogen cleaning after CMP (profile D), and the state after ammonia cleaning after cleaning after CMP (profile E) ), A state (profile F) in which nitrogen plasma treatment was performed after post-CMP cleaning was analyzed. Note that the shift of profile C in the high energy direction of about 1 eV is due to the effect of charge-up.

  FIGS. 25A and 25B are data obtained by observing the Si2p spectrum. FIG. 25A shows the depth of about 10 nm, and FIG. 25B shows the depth of about 2 nm. 25 (c), (d), and (e) are data obtained by observing N1s, O1s, and C1s spectra, respectively.

  FIG. 25B shows a broad peak on the low energy side (near 102 eV) of the hydrogen plasma treatment (profile D). This is considered that Si-H bonds exist, and it is assumed that Si-H is formed on the surface of the silicon oxide film by the hydrogen plasma treatment.

  From FIG. 25 (a), the 105 eV peak of the ammonia plasma treatment (profile E) and the nitrogen plasma treatment (profile F) is an asymmetric peak spreading toward the low energy side. The asymmetric peak (103.5 eV) is considered to be a Si—O—N bond. It is presumed that the surface of the silicon oxide film is nitrided by ammonia plasma treatment and nitrogen plasma treatment. Further, from the comparison between FIGS. 25A and 25B, it is considered that nitriding is strengthened on the surface. Nitridation by ammonia plasma treatment and nitrogen plasma treatment can also be confirmed in FIG.

  From FIG. 25 (e), almost no carbon is detected in the hydrogen plasma treatment (profile D). It can be seen that organic substances on the surface are removed by the hydrogen plasma treatment. Further, the peak at 289 eV after CMP (profile C) is considered to be a C—O bond. It is considered that slurry remains after CMP.

  FIG. 25 (f) shows a value obtained by obtaining the abundance ratio from the Si peak and the N peak and estimating the N amount. It is considered that almost the same nitriding is performed in the ammonia plasma treatment and the nitrogen plasma treatment.

  26 (a), (b), (c), and (d) are mass numbers 41 (Ar-H), mass numbers 27 (C2 H3), mass numbers 57 (C4 H9), and mass numbers 59 (C3 H7). It is the graph which measured O). FIGS. 27 (a), (b), (c), and (d) are mass numbers 28 (Si, C2 H4), mass numbers 44 (SiO, C3 H6), and mass numbers 29 (SiH, C2 H5), respectively. FIG. 3 is a graph obtained by measuring a mass number 31 (SiH 3).

  From FIG. 26 (a), there is almost no difference in the amount of hydrogen desorbed by the plasma treatment, but the desorption temperature of the hydrogen plasma treatment (profile D) is as low as 520 ° C compared to the other cases (560 ° C). I understand.

  26 (a), (b), and (c), organic substances are detached from each process. On the other hand, from FIGS. 27A to 27D, the presence of peaks other than the separation of organic substances can be seen. That is, the peaks at 300 to 400 ° C. are considered to be Si, SiO, SiH, and SiH 3, respectively. Comparing the figures, SiO separation is observed in the hydrogen, ammonia, and nitrogen plasma treatments, but SiH and SiH3 are hardly observed in the ammonia plasma treatment. That is, in the ammonia plasma treatment, Si—O—N is formed and is easily detached with relatively low energy. Further, the energy required for separation is highest in the case of nitrogen plasma treatment, and it can be said that the hydrogen plasma treatment and the ammonia plasma treatment are almost the same.

  From these results, it is considered that Si—OH and Si—O— that cause dangling bonds on the surface of the silicon oxide film are terminated by weakly bonded Si—O—N by ammonia plasma treatment. In the film formation of the silicon nitride film after the ammonia plasma treatment, Si—O—N on the very surface is detached, and the bulk Si—O bond and the Si—N of the silicon nitride film are firmly bonded, and are continuously formed. Form an interface. This is considered to be a mechanism for improving the adhesion at the interface. On the other hand, when ammonia plasma treatment is not performed, the surface of the silicon oxide film having many Si—OH bonds and ammonia, which is a raw material gas for the silicon nitride film, undergo a condensation reaction, and Si—O, which is the cause of dangling bonds. -Many bonds are considered to have occurred. If there are a large number of dangling bonds at the interface between the silicon oxide film and the silicon nitride film, it forms a leak path, which is considered to cause a leakage current between wirings and, consequently, a dielectric breakdown.

  From the above analysis results, the surface of the oxidized Cu wiring is reduced and converted into a Cu single element by the ammonia plasma treatment, and becomes electrically stable than the ionized Cu, and the silicon oxide film / Since the silicon nitride film interface becomes a continuous and strong film, it is considered that the leakage current is reduced and the TDDB life is greatly improved.

  The present inventors photographed TEM photographs of the interface between the wiring layer and the silicon nitride film (cap film) when the ammonia plasma treatment was performed and when it was not performed. As a result, in the case of the present embodiment where the ammonia plasma treatment was performed, it was confirmed that a thin film was present at the interface. The thin film is considered to be the aforementioned nitride layer. On the other hand, when the ammonia plasma treatment is not performed, such a film cannot be confirmed.

  Moreover, in this Embodiment, resistance of Cu wiring can be reduced. FIG. 28 shows the measurement results of the wiring resistance when various processes are performed. In the case of no treatment (no plasma treatment) and the case of ammonia plasma treatment, the values are significantly lower than in other cases (hydrogen plasma treatment, hydrogen annealing, nitrogen plasma treatment). FIG. 29 and FIG. 30 are trace drawings of TEM photographs in which the interface between the Cu wiring and the cap film (silicon nitride film) when these processes are performed is observed.

  In the case of no treatment and ammonia plasma treatment (FIG. 29), there is no peculiarity at the interface, but in the case of hydrogen annealing and nitrogen plasma treatment (FIG. 30), a copper silicide (CuSi) layer is formed at the interface. . This silicide layer seems to be the cause of the increase in resistance. Such a silicide layer is formed by reaction with silane gas during the formation of a silicon nitride film. However, when ammonia plasma treatment is performed, a very thin nitride film is formed on the Cu surface. It is considered that the film functions as a silicidation blocking layer. On the other hand, if the copper surface is simply reduced, such as hydrogen annealing, the active Cu surface is exposed and the reaction with silicon is promoted, so that a silicide layer is likely to be formed. In the case of hydrogen plasma treatment (FIG. 30C), some product is seen at the interface. However, in many cases, such a product may not be formed, and it is considered that the degree of silicidation is small in the case of hydrogen plasma treatment.

  From the analysis results described above, the inventors have found for the first time that the following model can be considered as a deterioration mechanism of the TDDB lifetime. FIG. 31 (a) shows a schematic diagram of the mechanism of TDDB degradation, and FIG. 31 (b) shows its energy band. That is, when the ammonia plasma treatment of the present embodiment is not performed, copper oxide (CuO) is formed on the surface of the Cu wiring due to the subsequent surface process, and the cap film (silicon nitride film 47). ) Forms copper silicide (Cu compound). Such copper oxide or copper silicide is easily ionized as compared with pure copper, and such ionized copper is drifted by an electric field between wirings and diffused into an insulating film between the wirings.

  Further, the interface between the insulating film (silicon oxide film 39) and the cap film (silicon nitride film 47) formed by embedding the copper wiring is subject to CMP damage or organic matter when the ammonia plasma treatment of this embodiment is not performed. Alternatively, many dangling bonds are formed, are discontinuous, and have poor adhesion. The presence of such dangling bonds has a function of promoting the diffusion of copper ions, and the copper ions are drifted and diffused along the interface. That is, a leak path is formed at the interface between the wirings. The leakage current flowing through the leakage path is also subjected to a long-time leakage action and thermal stress due to the current, and then the current value increases at an accelerated rate, leading to dielectric breakdown (decrease in TDDB life).

  In contrast, FIGS. 32 (a) and 32 (b) show a schematic diagram of a mechanism for improving TDDB and its energy band when the ammonia plasma treatment is performed. In the present embodiment, since the surface of Cu wirings 46a to 46e is subjected to ammonia plasma treatment, the oxide layer on the surface of Cu wirings 46a to 46e is reduced and disappears, and a thin nitride layer is formed on the surfaces of Cu wirings 46a to 46e. Therefore, copper silicide is not formed when the silicon nitride film 47 is formed. For this reason, it is possible to eliminate a causative substance that dominantly supplies copper ions that cause leakage and dielectric breakdown. In the present embodiment, since the surface of the silicon oxide film 39 is subjected to ammonia plasma treatment, the connection with the silicon nitride film 47 is made continuous, the density of dangling bonds can be reduced, and the formation of leak paths can be suppressed. In addition, the surface of the silicon oxide film 39 can be cleaned. Therefore, in the present embodiment, it is possible to form a bonding interface between the silicon oxide film 39 and the silicon nitride film 47 that can suppress the generation of copper ions that cause a decrease in the TDDB life and can suppress the diffusion of copper. . Thereby, the TDDB life can be improved.

  From the above analysis, it is considered that the TDDB life can be improved even by hydrogen plasma treatment. That is, the surface of Cu is reduced by hydrogen plasma treatment, and dangling bonds such as Si—O— and Si—OH causing the termination are terminated with Si—H. Then, when the silicon nitride film is formed, Si—H on the surface having a weak bond is detached and replaced with Si—N. As a result, a continuous interface between the silicon oxide film and the silicon nitride film is formed. However, the wiring resistance increases as described above.

  FIG. 33 is a graph showing TDDB life data when hydrogen plasma treatment is performed. For reference, line Ref (no treatment) and line A (ammonia plasma treatment) are shown. It can be seen that the hydrogen plasma treatment (line C) significantly improves the TDDB life. In the case of hydrogen plasma treatment, plasma damage is expected to be reduced. Therefore, when a material that does not generate a reaction product with Cu, which is another material replacing the silicon nitride film as the cap film, can be applied. Very effective. In the nitrogen plasma treatment (line D), the TDDB life is reduced. As can be seen from FIGS. 26 and 27, this is probably due to the increased adhesion of organic matter due to the nitrogen plasma treatment.

  In the present embodiment, since the adhesion between the Cu wirings 46a to 46e and the silicon oxide film 39 and the cap film 47 is improved, there is an effect that the peeling strength at the interface is increased and the margin is increased.

  The treatment is not limited to a single gas of ammonia and hydrogen, but may be performed by a mixed gas plasma with an inert gas such as nitrogen, argon, or helium. That is, a mixed gas of ammonia and hydrogen, nitrogen, argon, or helium, or a mixed gas of hydrogen and ammonia, nitrogen, argon, or helium may be used. Further, a mixed gas of a ternary system, a quaternary system or the like selected from these gases may be used. At this time, hydrogen, ammonia, or the sum of hydrogen and ammonia needs to be mixed by 5% or more with respect to the total flow rate (mass flow rate).

(Embodiment 2)
A method of manufacturing a CMOS-LSI according to another embodiment of the present invention will be described in the order of steps with reference to FIGS.

  The manufacturing method of the present embodiment is the same for the steps from FIG. 1 to FIG. 8 in the first embodiment. That is, the process is the same up to the Cu film deposition step. Therefore, the steps after the CMP step will be described below.

  FIG. 34 is a schematic diagram showing an example of the overall configuration of a CMP apparatus used for forming embedded Cu wiring.

  As shown in the figure, the CMP apparatus 400 includes a polishing processing unit 401 and a post-cleaning unit 402 provided in the subsequent stage. In the polishing processing unit 401, two surface plates (first surface plate 403A and second surface plate 403B) for polishing the wafer (substrate) 1 and the substrate 1 after the polishing processing are preliminarily cleaned, A clean station 404 for performing anticorrosion treatment, a rotating arm 405 for moving the substrate 1 between the loader 406, the first surface plate 403A, the second surface plate 403B, the clean station 404, and the unloader 407 are installed.

  A post-cleaning unit 402 that scrubs and cleans the surface of the substrate 1 that has been subjected to preliminary cleaning is provided at the subsequent stage of the polishing processing unit 401. In the post-cleaning unit 402, a loader 408, a first cleaning unit 409A, a second cleaning unit 409B, a spin dryer 410, an unloader 411, and the like are installed. Further, the post-cleaning unit 402 is entirely surrounded by a light-shielding wall 430 in order to prevent the surface of the substrate 1 being cleaned from being irradiated with light, and the inside is in a dark room state of 180 lux, preferably 100 lux or less. Yes. This is because when the substrate 1 with the polishing liquid adhered to the surface is irradiated with light in a wet state, a short-circuit current flows to the pn junction by the photovoltaic of the silicon, and is connected to the p side (+ side) of the pn junction. This is because Cu ions are dissociated from the surface of the Cu wiring to cause wiring corrosion.

  As shown in FIG. 35, the first surface plate 403A is rotationally driven in a horizontal plane by a drive mechanism 412 provided in the lower part thereof. Further, a polishing pad 413 formed by uniformly attaching a synthetic resin such as polyurethane having a large number of pores is attached to the upper surface of the first surface plate 403A. Above the first surface plate 403A, a wafer carrier 415 that is moved up and down by a drive mechanism 414 and driven to rotate in a horizontal plane is installed. The substrate 1 is held with its main surface (surface to be polished) facing downward by a wafer chuck 416 and a retainer ring 417 provided at the lower end of the wafer carrier 415, and is pressed against the polishing pad 413 with a predetermined load. A slurry (polishing liquid) S is supplied between the surface of the polishing pad 413 and the surface to be polished of the substrate 1 through a slurry supply pipe 418, and the surface to be polished of the substrate 1 is chemically and mechanically polished. In addition, a dresser 420 is installed above the first surface plate 403A so as to move up and down by a drive mechanism 419 and to rotate in a horizontal plane. A base material electrodeposited with diamond particles is attached to the lower end of the dresser 420, and the surface of the polishing pad 413 is periodically cut by this base material in order to prevent clogging by the abrasive grains. The second surface plate 403B has substantially the same configuration as the first surface plate 403A except that two slurry supply pipes 418a and 418b are provided.

  In order to form Cu wiring using the CMP apparatus 400, the substrate 1 accommodated in the loader 406 is carried into the polishing processing unit 401 using the rotating arm 405, and first, as shown in FIG. On 403A, chemical mechanical polishing (abrasive-free chemical mechanical polishing) (first step CMP) is performed using a slurry that does not contain abrasive grains, and the Cu film 46 outside the wiring grooves 40 to 44 is removed. (FIG. 37).

  Here, the abrasive-free chemical mechanical polishing means chemical mechanical polishing using a polishing liquid (slurry) containing 0.5% by weight or less of abrasive grains made of powder such as alumina and silica. In particular, the content of abrasive grains is preferably 0.1% by weight or less, more preferably 0.05% by weight or less or 0.01% by weight or less.

  Further, as the polishing liquid, a liquid whose pH is adjusted so as to belong to the corrosion area of Cu is used, and the polishing selectivity of the Cu film 46 to the TiN film 45 (barrier layer) is at least 5 or more. What the composition was adjusted is used. As such a polishing liquid, a slurry containing an oxidizing agent and an organic acid can be exemplified. Examples of the oxidizing agent include hydrogen peroxide, ammonium hydroxide, ammonium nitrate, and ammonium chloride. Examples of the organic acid include citric acid, malonic acid, fumaric acid, malic acid, adipic acid, benzoic acid, and phthalic acid. And tartaric acid, lactic acid, succinic acid and the like. Of these, hydrogen peroxide does not contain a metal component and is not a strong acid, and therefore is a suitable oxidizing agent for use in the polishing liquid. Citric acid is also generally used as a food additive, has low toxicity, low waste damage, no odor, and high solubility in water, so it is a suitable organic acid for use in polishing liquids. . In this embodiment, for example, a polishing liquid in which 5% by volume of hydrogen peroxide and 0.03% by weight of citric acid are added to pure water so that the content of abrasive grains is less than 0.01% by weight is used.

  When chemical mechanical polishing is performed with the above polishing liquid, the Cu surface is first oxidized by an oxidizing agent, and a thin oxide layer is formed on the surface. Next, when a substance for water-solubilizing the oxide is supplied, the oxide layer is eluted as an aqueous solution, and the thickness of the oxide layer is reduced. The thinned portion of the oxide layer is again exposed to the oxidizing substance to increase the thickness of the oxide layer, and this reaction is repeated to advance chemical mechanical polishing. The chemical mechanical polishing using such an abrasive-free polishing solution is described in detail in Japanese Patent Application Nos. 9-299937 and 10-317233 by the present inventors.

The polishing conditions are, for example, load = 250 g / cm ² , wafer carrier rotation speed = 30 rpm, surface plate rotation speed = 25 rpm, slurry flow rate = 150 cc / min, and the polishing pad is a hard pad (Rodel, USA) IC1400). The polishing end point is when the Cu film 46 is removed and the underlying TiN film 45 is exposed, and the end point is detected when the polishing target changes from the Cu film 46 to the TiN film 45. This is performed by detecting the rotational torque signal intensity of the. Alternatively, a hole may be formed in a part of the polishing pad, and the end point may be detected based on a change in the light reflection spectrum from the wafer surface, or the end point may be detected based on the change in the optical spectrum of the slurry.

  As shown in FIG. 37, by performing the above-mentioned abrasive-free chemical mechanical polishing, the Cu film 46 outside the wiring grooves 40 to 44 is almost removed and the lower TiN film 45 is exposed, but FIG. ) And (b), the Cu film 46 that could not be removed by this polishing remains in the depressions (indicated by arrows) of the TiN film 45 caused by the underlying step.

  Next, in order to remove the TiN film 45 outside the wiring grooves 40 to 44 and the Cu film 46 left locally on the upper surface thereof, the substrate 1 is replaced with the first surface plate shown in FIGS. From 403A to the second surface plate 403B, chemical mechanical polishing (abrasive chemical mechanical polishing) using a polishing liquid (slurry) containing abrasive grains (CMP in the second step) is performed. Here, the abrasive-mechanical chemical mechanical polishing means chemical mechanical polishing using a polishing liquid in which the content of abrasive grains made of powder such as alumina and silica is more than 0.5% by weight. In the present embodiment, a mixture of 5% by volume of hydrogen peroxide, 0.03% by weight of citric acid, and 0.5% by weight of abrasive grains is used as a polishing liquid in a pure water. However, the present invention is not limited to this. It is not something. This polishing liquid is supplied to the polishing pad 413 of the second surface plate 403B through the slurry supply pipe 418a.

  In this abrasive-mechanical chemical polishing, the TiN film 45 outside the wiring grooves 40 to 44 is removed following the removal of the Cu film 46 left locally on the upper surface of the TiN film 45. Therefore, polishing is performed under the condition that the polishing selection ratio of the Cu film 46 to the TiN film 45 (barrier layer) is lower than that of the abrasive-free chemical mechanical polishing, for example, the selection ratio is 3 or less. The surface of the internal Cu film 46 is prevented from being polished.

The polishing conditions are, for example, a load = 120 g / cm ² , a wafer carrier rotation speed = 30 rpm, a platen rotation speed = 25 rpm, and a slurry flow rate = 150 cc / min, and a polishing pad IC1400 is used. The amount of polishing is equivalent to the thickness of the TiN film 45, and the end point of polishing is controlled by the time calculated from the thickness of the TiN film 45 and the polishing rate.

  As shown in FIG. 39, by carrying out the abrasive chemical mechanical polishing described above, the TiN film 45 outside the wiring grooves 40 to 44 is almost removed and the underlying silicon oxide film 39 is exposed. As shown in enlarged views (a) and (b), the TiN film 45 that could not be removed by the above polishing is formed in the depressions (indicated by arrows) of the silicon oxide film 39 caused by the underlying step. Remains.

  Next, the TiN film 45 (barrier layer) remaining locally on the silicon oxide film 39 outside the wiring grooves 40 to 44 while suppressing the polishing of the Cu film 46 inside the wiring grooves 40 to 44 as much as possible. A selective chemical mechanical polishing (CMP of the third step) is carried out to remove the material. This selective chemical mechanical polishing is performed under the condition that the polishing selection ratio of the TiN film 45 to the Cu film 46 is at least 5 or more. The chemical mechanical polishing is performed under the condition that the ratio of the polishing rate of the silicon oxide film 39 to the polishing rate of the Cu film 46 is larger than 1.

  In order to perform the selective chemical mechanical polishing, generally, a polishing solution containing more than 0.5 wt% of abrasive grains used in the abrasive chemical mechanical polishing is added with an anticorrosive agent. . The anticorrosive agent refers to an agent that prevents or suppresses the progress of polishing by forming a corrosion-resistant protective film on the surface of the Cu film 46, and includes BTA derivatives such as benzotriazole (BTA) and BTA carboxylic acid, dodecyl mercaptan, and triazole. Tolyltriazole and the like are used, and a stable protective film can be formed particularly when BTA is used.

  When BTA is used as an anticorrosive, the concentration depends on the type of slurry, but is usually 0.001 to 1% by weight, more preferably 0.01 to 1% by weight, still more preferably 0.1 to 1% by weight. A sufficient effect can be obtained by adding% (3 steps). In the present embodiment, the polishing liquid used in the second step abrasive grain chemical mechanical polishing is mixed with 0.1% by weight of BTA as an anticorrosive agent. However, the present invention is limited to this. It is not a thing. Further, in order to avoid a decrease in polishing rate due to the addition of an anticorrosive agent, polyacrylic acid, polymethacrylic acid, ammonium salts thereof, ethylenediaminetetraacetic acid (EDTA), or the like may be added as necessary. Note that chemical mechanical polishing using a slurry containing such an anticorrosive is described in detail in Japanese Patent Application Nos. 10-209857, 9-299937 and 10-317233 by the present inventors. Has been.

In this selective chemical mechanical polishing (CMP of the third step), after the abrasive chemical mechanical polishing (CMP of the second step) is completed, the second chemical mechanical polishing of the CMP apparatus shown in FIGS. It is performed on the surface plate 403B. The polishing liquid to which the anticorrosive is added is supplied to the surface of the polishing pad 413 through the slurry supply pipe 418b. The polishing conditions are, for example, a load = 120 g / cm ² , a wafer carrier rotation speed = 30 rpm, a platen rotation speed = 25 rpm, and a slurry flow rate = 190 cc / min.

  As shown in FIGS. 41 and 42 (a) and 42 (b), by performing the selective chemical mechanical polishing described above, the TiN film 45 outside the wiring grooves 40 to 44 is all removed, and the wiring grooves 40 to 44 are removed. Embedded Cu wirings 46a to 46e are formed in the inside.

  A slurry residue containing particles such as abrasive grains and metal particles such as Cu oxide is attached to the surface of the substrate 1 where the formation of the embedded Cu wirings 46a to 46e is completed. In order to remove this slurry residue, first, the substrate 1 is washed with pure water containing BTA in the clean station 404 shown in FIG. At this time, megasonic cleaning in which slurry residue is released from the surface of the substrate 1 by applying high-frequency vibration of 800 kHz or more to the cleaning liquid may be used in combination. Next, in order to prevent the surface from being dried, the substrate 1 is transported from the polishing processing unit 401 to the post-cleaning unit 402 in a wet state, and a cleaning liquid containing 0.1 wt% NH 4 OH is added to the first cleaning unit 409A. The scrub cleaning used is performed, followed by scrub cleaning using pure water in the second cleaning unit 409B. As described above, the post-cleaning unit 402 is entirely covered with the light-shielding wall 430 in order to prevent the Cu wirings 46a to 46e from being corroded due to light irradiating the surface of the substrate 1 being cleaned. It has been broken.

  After the scrub cleaning (post-cleaning) is completed, the substrate 1 is dried by the spin dryer 410 and then transferred to the next process. The subsequent steps are the same as those in the first embodiment. FIG. 43 is an overall flow diagram of the formation process of the Cu wirings 46a to 46e described above.

  According to the present embodiment, the TDDB life can be further improved as compared with the case of the first embodiment. FIG. 44 is a graph showing the TDDB life in the case of the present embodiment. Data in the case of the present embodiment is indicated by a line E. For reference, data (line A) in the case of no treatment (line Ref) and chemical mechanical polishing of abrasive grains (first embodiment) are shown simultaneously. It should be noted that the TDDB characteristics are improved as shown by line F even if only the abrasive-free chemical mechanical polishing is performed without performing the ammonia plasma treatment. The reason why the TDDB life is improved when the abrasive grains are free is considered to be because damage to the silicon oxide film can be reduced. In the case of abrasive grains, the slurry contains abrasive grains (such as alumina) having a particle diameter (secondary particle diameter) of 2 to 3 μm. The abrasive grains cause micro scratches and damage the surface of the silicon oxide film 39. However, when abrasive grains are free, the slurry does not contain abrasive grains, or even if they are contained, there are very few, so damage can be greatly reduced. For this reason, it is considered that the TDDB characteristics are improved.

  In addition, when the acid treatment (HF treatment) described in the next embodiment is combined, the TDDB characteristics are further improved (line G). In the acid treatment, after the post-CMP cleaning, the substrate 1 is further treated with an acidic aqueous solution (for example, HF aqueous solution), and then ammonia plasma treatment is performed. It is considered that the surface damage layer was removed by the acid treatment, the adhesion at the interface was improved, and the TDDB life was improved.

(Embodiment 3)
FIG. 45 is an overall flow diagram of the formation process of the Cu wirings 46a to 46e of the third embodiment. As shown in the figure, the process is the same as that of the first embodiment except that a cleaning step using HF or citric acid is inserted.

  As the HF cleaning, for example, brush scrub cleaning is used, and the conditions of HF concentration of 0.5% and cleaning time of 20 seconds can be selected.

  Alternatively, citric acid cleaning may be used instead of HF cleaning. For the citric acid cleaning, for example, brush scrub cleaning is used, and a condition where the citric acid concentration is 5% and the cleaning time is 45 seconds can be selected.

  Thus, by using HF or citric acid cleaning, the damaged layer on the surface generated by CMP or the like can be removed. Thereby, the TDDB life can be improved. FIG. 46 is a graph showing the TDDB life in the case of the present embodiment. In the present embodiment, data applying citric acid is indicated by line H, and data applying HF cleaning is indicated by line I. For reference, no processing (line Ref) and data of the first embodiment (line A) are shown at the same time. It should be noted that the TDDB characteristics are improved as shown by line J even if only the HF cleaning is performed without performing the ammonia plasma treatment. This is presumably because the interface characteristics could be improved by removing the damaged layer.

(Embodiment 4)
47 to 49 are plan views and cross-sectional views showing a method for manufacturing a semiconductor integrated circuit device according to the fourth embodiment of the present invention. 47 to 49, only the wiring portion is shown.

  As shown in FIG. 47, an insulating film 502 for forming a wiring is formed on the insulating film 501 and buried in the insulating film 502 to form a copper wiring 503. The formation method of copper wiring 503 is the same as in the first to third embodiments.

  Further, a silicon oxide film (TEOS oxide film) 506 formed by a plasma CVD method using a silicon nitride film 504, a low dielectric constant silicon oxide film 505, and TEOS as a source gas is formed.

  The low dielectric constant silicon oxide film 505 is made of, for example, an inorganic SOG film using hydrogen silsesquioxane as a raw material, tetraalkoxysilane + alkylalkoxysilane. It is formed of a silicon oxide insulating film having a relative dielectric constant (ε) of 3.0 or less, such as a coating type insulating film such as an organic SOG film or a fluorocarbon polymer film formed by a plasma CVD method. By using such a low dielectric constant silicon oxide film, the parasitic capacitance between wirings can be reduced and the problem of wiring delay can be avoided.

  Next, in the pattern as shown in FIG. 48A, as shown in FIG. 48B, the connection hole 507 is opened. Photolithography and etching are used for opening the connection hole 507. By the way, the silicon oxide film 505 having a low dielectric constant has a rough film structure and has many Si—OH bonds. For this reason, it has been empirically found that the film quality and interface state of the film formed thereon are not good. It has also been empirically found that the TDDB characteristics are not good if the barrier film (titanium nitride) described in the next step is formed as it is. Therefore, next, the ammonia plasma treatment described in Embodiment 1 is performed on the exposed portion of the silicon oxide film 505 in the connection hole 507. Thereby, the Si—OH bond on the surface is modified and converted to the Si—O—N bond as described in the first embodiment.

  Next, as shown in FIG. 49, a plug 508 made of titanium nitride and tungsten is formed in the connection hole 507. When this titanium nitride is deposited, the Si—O—N bond is released as in the first embodiment, and the interface between the titanium nitride and the silicon oxide film 505 having a low dielectric constant is improved and the adhesion is improved.

  Of course, such plasma treatment in the connection hole can also be applied to the wiring trench.

  Further, instead of the ammonia plasma treatment, a plasma treatment in which hydrogen plasma treatment, nitrogen, argon, helium, or the like is mixed may be used.

  Note that the surface of the wiring 503 at the bottom of the connection hole 507 may be oxidized in an ashing process for removing the photoresist film after the connection hole 507 is opened. As a technique for removing such an oxide layer, there is a technique described in JP-A-11-16912.

  The silicon oxide film 505 having a low dielectric constant can be defined as a silicon oxide film having a dielectric constant lower than that of a silicon oxide film (for example, a TEOS oxide film) included in a protective film formed as a passivation film.

(Embodiment 5)
The method for forming the embedded Cu wirings 46a to 46e described above can also be applied to the formation of the embedded Cu wiring using the dual damascene method. In this case, after forming the first-layer W wirings 24-30, first, as shown in FIG. 50, a film thickness of about 1200 nm is formed on the first-layer W wirings 24-30 by plasma CVD. A silicon oxide film 31, a thin silicon nitride film 38 having a thickness of about 50 nm, and a silicon oxide film 39 having a thickness of about 350 nm are sequentially deposited.

  Next, as shown in FIG. 51, the silicon oxide film 39, the silicon nitride film 38 and the oxide film on the first W wirings 24, 26, 27, 29, and 30 are formed by dry etching using a photoresist film as a mask. After sequentially removing the silicon film 31, as shown in FIGS. 52A and 52B, the silicon oxide film 39 is formed by dry etching using another photoresist film as a mask and the silicon nitride film 38 as an etching stopper. By removing, the wiring grooves 50 to 54 that also serve as through holes are formed.

  Next, as shown in FIG. 53, a thin TiN film 45 having a thickness of about 50 nm is deposited on the silicon oxide film 39 including the inside of the wiring grooves 50 to 54, and then the wiring grooves 50 to 50 are formed on the TiN film 45. A Cu film 46 having a thickness sufficiently thicker than the depth of 54 is deposited. Since the wiring grooves 50 to 54 that also serve as through holes have a larger aspect ratio than the wiring grooves 40 to 44, the TiN film 45 is deposited by the CVD method. The Cu film 46 is deposited by repeating sputtering twice or more. Further, it may be formed by a CVD method, an electrolytic plating method, or an electroless plating method. When the Cu film 46 is formed by plating, a step of forming a Cu seed layer by sputtering or the like under the wiring grooves 50 to 54 is required.

  Next, as shown in FIG. 54, the Cu film 46 and the TiN film 45 outside the wiring grooves 50 to 54 are removed by the above-described abrasive-free chemical mechanical polishing, abrasive-containing chemical mechanical polishing, and selective chemical mechanical polishing. Then, embedded Cu wirings 46 a to 46 e are formed inside the wiring grooves 50 to 54. Subsequent steps are the same as the method of forming the embedded Cu wirings 46a to 46e using the single damascene method.

(Embodiment 6)
As described above, it is generally known that when Cu is used as a wiring material, the TDDB life is significantly shorter than other metal materials (for example, aluminum and tungsten). Here, FIG. 55 is a graph showing data obtained by measuring TDDB characteristics of Cu wiring, aluminum wiring, and tungsten wiring. The vertical axis indicates the TDDB life, and the horizontal axis indicates the electric field strength.

Extrapolating the characteristics of the aluminum wiring (data A) and the tungsten wiring (data B), the TDDB life at an electric field strength of 0.2 MV / cm (normal use state) is the development target of the present inventors 3 × 10 ⁸ sec (10 years) is well exceeded. On the other hand, extrapolating the characteristics of the Cu wiring (data C) shows that there is almost no margin with respect to the 10-year development target.

  In this test, the aluminum wiring is formed by depositing a film and patterning using photolithography, but the tungsten wiring is formed using the damascene method in the same manner as the Cu wiring. That is, the difference between the Cu wiring and the tungsten wiring is only the material, and there is no structural difference. Nevertheless, it is suggested that there is a significant difference in TDDB characteristics due to the difference in wiring materials. Here, the TDDB characteristics indicate data performed at a temperature of 140 ° C.

  It is generally considered that the cause of the deterioration of the TDDB life is that Cu applied to the wiring material diffuses to the periphery, and this reduces the withstand voltage between the wirings. Therefore, it is considered that a barrier film for preventing the diffusion of Cu is indispensable for putting Cu wiring into practical use. However, with the miniaturization of wiring, the wiring resistance increases as the cross-sectional area of the high-resistance barrier film occupies the wiring cross-sectional area. As a result, there is a problem that the merit of using copper as the wiring material is reduced. To do.

  Therefore, the present inventors conducted a new experiment and examined the copper diffusion phenomenon. As a result, the present inventors found for the first time an essential mechanism for the copper diffusion phenomenon as described above. That is, the copper in the wiring is more dominant than the atomic copper because the ionized copper supplied from copper oxide or copper silicide drifts and diffuses at the potential between the wirings. Also, the copper diffusion path is dominated by the interface between the insulating film on which the copper wiring is formed and the cap film. That is, copper oxide or copper silicide is formed on the surface of the copper wiring, copper ions are formed from these copper compounds, and the ionized copper is caused by the electric field between the wirings along the interface between the wiring forming insulating film and the cap film. It drifts and diffuses, and the diffused copper atoms increase the leakage current. Then, the increase in the leakage current increases the thermal stress, and finally dielectric breakdown occurs in the leakage path, leading to the TDDB life.

  FIG. 56 is a graph showing the content of Si in the Cu wiring without the various surface treatments (ammonia plasma treatment, hydrogen plasma treatment, hydrogen annealing treatment, nitrogen plasma treatment) and without treatment. This inspection result is obtained after the Cu wiring (including TiN film (barrier film)) forming process, the cleaning process, the various surface treatment processes, the cap film forming process, and the interlayer insulating film forming process. It was created by the inspection conducted. In addition, it is considered that the same result as that of Si can be obtained with other impurities such as oxygen and sulfur.

  As described above, Cu silicide in various surface treatments is mainly due to a set flow at the time of film formation of a cap film (silicon nitride or the like). In the hydrogen annealing process and the nitrogen plasma process at the time of this inspection, compared to the ammonia plasma process and the hydrogen plasma process, near the surface of the Cu wiring (d = about 10 to 60 nm) and inside (d = about 90 to 300 nm). High Si content. In particular, it can be seen that the number is extremely near the surface. In these processes, as shown in FIG. 33, the TDDB characteristics were bad.

  On the other hand, in the ammonia plasma treatment and the hydrogen plasma treatment at the time of the inspection, the Si content in the vicinity of the surface of the Cu wiring and in the inside thereof is smaller than that in the hydrogen annealing treatment and the nitrogen plasma treatment. In particular, the Si content near the surface is extremely low. That is, in these treatments, the content of impurities in the Cu wiring is small, the cleanness of the surface of the insulating film in which the wiring groove is formed, and the dangling bond on the surface of the insulating film in which the wiring groove is formed. Etc. are few. Therefore, as shown in FIG. 33, the TDDB characteristics were good. Thus, when there is a TiN film (conductive barrier film), the TDDB characteristic is determined only by the influence of the interface.

  From such a new point of view, the present inventors have formed a film of neutral Cu that is not ionized on the side wall and bottom of the wiring trench (increasing the purity of copper), the ammonia plasma treatment or the hydrogen plasma treatment. Even if the thickness of the barrier film is reduced to less than 10 nm by combining these with the CMP process or the cleaning process, or even without the barrier film itself, the Cu wiring is formed. It has been found for the first time that the TDDB life of a semiconductor integrated circuit device can be improved.

  FIG. 57 shows the dependence of the wiring resistance (TiN · x (film thickness) nm / TiN · 50 nm ratio) on the thickness of the TiN film (barrier film). The figure shows the measured value and theoretical value (calculated value) of the wiring resistance for a groove shape having a wiring width of, for example, about 0.4 μm and 1.0 μm and a wiring groove depth of, for example, about 0.4 μm. It shows. The film thickness of the TiN film is the film thickness at the bottom of the wiring trench.

  From FIG. 57, it can be seen that as the thickness of the TiN film (barrier film) becomes thinner, the wiring resistance also decreases, and the calculated value and the measured value almost coincide. Therefore, compared with the wiring resistance when the film thickness of TiN is 50 nm, when there is no TiN film, 19% when the wiring width is about 0.4 μm and 15% when the wiring width is about 1.0 μm. The wiring resistance can be greatly reduced. It can also be seen that even when the thickness of the TiN film is about 10 nm, the wiring resistance can be reduced by 16% when the wiring width is about 0.4 μm and by about 12% when the wiring width is about 1.0 μm.

FIG. 58 shows the dependency of TDDB characteristics on the TiN film when Cu wiring is formed by the long throw sputtering method. From the figure, it can be seen that the TDDB characteristics when the thickness of the TiN film is about 10 to 50 nm are equivalent to those described above. On the other hand, the TDDB characteristic of the sample in the absence of the TiN film is less inclined than the TDDB characteristic of the TiN film of about 10 to 50 nm, but the new system target (for example, 0.2 MV / cm, 110 ° C., 10 years = 3 × 10 ⁸ seconds).

  FIG. 59 shows TDDB characteristics depending on the presence or absence of heat treatment in each Cu wiring when there is no TiN film and when the thickness of the TiN film is about 10 nm. From the figure, it can be seen that the TDDB characteristics are not deteriorated even when the sample does not have a TiN film, for example, by heat treatment at 400 ° C. for 3 hours.

  From the evaluation results of FIGS. 58 and 59, even when there is no TiN film, that is, when the wiring is composed only of Cu, the reliability can be sufficiently achieved and a practical Cu wiring can be formed. It became clear for the first time by experiment of the present inventors.

  Next, FIG. 60 shows a specific example of the wiring structure of the semiconductor integrated circuit device according to the sixth embodiment. FIG. 60 is a cross-sectional view showing a part of the semiconductor integrated circuit device (first-layer wiring and second-layer wiring), where (a) is a portion formed by a single damascene method, and (b) is The locations formed by the dual damascene method are shown respectively. Note that a silicon oxide film 48 is deposited on the silicon nitride film 47. In FIG. 2B, a silicon oxide film 31 b is deposited on the silicon oxide film 31 a and the W wiring 27 via a silicon nitride film 49. In the silicon oxide film 31b and the silicon nitride film 49, a case where a through hole 34 is formed so that a part of the upper surface of the W wiring 27 is exposed is illustrated. Further, in the following description, for ease of explanation, only the first layer wiring and the second layer wiring are extracted and described, but the present invention is limited to being applied only to that part. However, the present invention can be applied to other wiring layer portions.

  The width of the wiring (width of the wiring groove 42) and the interval between adjacent wirings (distance from the side surfaces of the adjacent wirings facing each other) are, for example, 0.4 μm or less. The semiconductor integrated circuit device has a wiring structure in which the wiring width and the adjacent wiring interval considered by the present inventors are, for example, 0.25 μm or less, or 0.2 μm or less. The aspect ratio of the wiring trench 42 is, for example, 1.

  The thickness of the conductive barrier film exemplified by the TiN film 45 is, for example, less than 10 nm, preferably about 6 to 7 nm. In the sixth embodiment, the TDDB characteristics can be improved even when the thickness of the TiN film 45 is, for example, 5 nm or less, 3 nm or less, or 2 nm, which is thinner. The thickness of the TiN film 45 here refers to the surface portion to be deposited the thinnest. That is, here, as described above, since the side wall is thinned in the thickness of the TiN film 45 in the wiring groove (wiring groove 42, etc.) or the connection hole (through hole 34, etc.), the side wall This refers to the thickness of the TiN film 45. Further, in that case, for example, there are the following two structures. One is that the thickness of the thinnest portion of the TiN film 45 in the side wall portion (including the bottom corner of the groove or hole) in the wiring groove or connection hole is the above thickness (for example, less than 10 nm, preferably 6 to 7 nm). About 5 nm or less, 3 nm or less, or 2 nm). The other one is that the thickness of the thickest portion of the TiN film 45 in the side wall portion in the wiring groove or connection hole is the above thickness (for example, less than 10 nm, preferably about 6 to 7 nm, 5 nm or less, 3 nm or less, Or about 2 nm).

Since the TiN film 45 having a thickness of less than 10 nm is formed as described above, the TiN film 45 has better adhesion to the silicon oxide film 39 than the Cu film, so that the Cu film 46 peels off during the CMP process. Can be prevented. In addition, although the wiring resistance is increased as compared with the case where the TiN film 45 is not provided (described in the eighth embodiment later), a highly reliable Cu wiring structure can be realized. Further, the TDDB characteristics can be improved as compared with the case where the TiN film 45 is not provided. This is presumably because, when there is no TiN film 45, Cu collides with the side wall portion of the wiring groove 42 and reacts with SiO ₂ when the Cu film 46 is formed, resulting in slight generation of Cu ions. Even after the heat treatment, the TDDB characteristics do not deteriorate, and it is considered that the Cu ion layer at the slight Cu / SiO ₂ interface has an influence. Therefore, according to the present embodiment, it is considered that even the TiN film 45 having a thickness of less than 10 nm serves as a barrier against ionized Cu and can improve the TDDB characteristics.

  Further, the concentration of components other than Cu in the Cu wiring exemplified by the Cu wiring 46c is 0.8 atomic% (atomic% or At.%) Or lower or 0.2 atomic% or lower. Further, in the actual measurement result of the present inventors, the concentration of the component other than Cu is, for example, 0.08 atomic% or less, 0.05 atomic% or less lower than that, or 0.02 atomic% or less lower than that. It was possible to The concentration value of the component other than Cu is a value when the semiconductor chip is completed, that is, when the semiconductor chip is cut out from the semiconductor wafer through the wafer process, and the component other than Cu is the Cu wiring. It is a value calculated on the assumption that it has diffused into the Cu wiring due to heat at the time of film formation of the insulating film and metal film after formation (for example, heat of about 450 ° C. is applied at the time of film formation for tungsten or the like). In the actual Cu wiring, the components other than Cu are considered to be distributed in such a state that the concentration of the upper layer portion (the portion in contact with the cap film) of the Cu wiring is high and becomes gradually thinner toward the center of the Cu wiring. It is done. Examples of the components other than Cu include silicon, oxygen, sulfur (sulphur is considered when a Cu wiring is formed by a plating method), or any combination thereof.

  Further, instead of the silicon oxide films 31a, 31b, 31, 39, 48, etc., the material of the interlayer insulating film may be, for example, a SiOF, organic SOG (Spin On Glass) or PSG (Phospho Silicate Glass) film. When an insulating material having a low dielectric constant such as SiOF or an organic SOG film is used, the wiring capacity can be reduced, so that the performance of the semiconductor integrated circuit device can be further improved. In addition, when a PSG film is used, the TDDB life can be further improved because it has a function of preventing the diffusion of Cu. Therefore, the reliability of the semiconductor integrated circuit device can be further improved.

  Next, an example of a method for forming a Cu wiring structure by such a single damascene method will be described with reference to FIGS. Each of FIGS. 61 to 65 is a plan view of a main part during the manufacturing process of the semiconductor integrated circuit device, and (b) is a cross-sectional view taken along the line AA of each figure (a). ing. Further, although FIGS. 61A to 64A are plan views, the metal film is hatched for easy understanding of the drawings.

  First, after the steps of FIGS. 1 to 6 described in the first embodiment and the like, a wiring groove 42 is formed as shown in FIG. 61 in the same manner as described with reference to FIG. From the bottom surface of the wiring groove 42, the upper surface of the plug 37 is exposed. Subsequently, as shown in FIG. 62, for example, a Ta film 45a (conductive barrier film) is deposited by a sputtering method or the like similar to that of the first embodiment, for example, with a deposition film thickness of about 30 nm. At this time, a Ta film 45a of, for example, less than 10 nm or less and about 6 to 7 nm is deposited on the sidewall portion of the wiring groove 42 at the thickest portion or the thinnest portion. Here, the conductive barrier film is made of Ta, but TiN and other exemplified films may be used as described above.

  Thereafter, a Cu film 46 is deposited on the Ta film 45a by a sputtering method similar to that of the first embodiment, for example, with a deposition thickness of about 300 nm. The conditions at this time are as follows, for example. The pressure is, for example, 0.02 Pa, the direct current (DC) power is, for example, 10 kW, the distance between the target and the substrate 1 is, for example, 300 to 400 mm, and the temperature is, for example, room temperature.

  As described above, in this embodiment, the Cu film 46 is deposited by the sputtering method, so that the generation of the compound can be greatly reduced as compared with the CVD method and the plating method. As a target at that time, oxygen-free Cu having a high purity of, for example, 99.999% (5N) or more, preferably 99.9999% (6N) or more was used. Thereby, for example, the Cu concentration of the Cu film 46 during film formation can be 99.999% or more, preferably 99.9999% or more. Therefore, Cu with higher purity can be deposited.

  When depositing the Ta film 45a and the Cu film 46, a normal sputtering method may be used, but a sputtering method with high directivity such as a long throw sputtering method or a collimated sputtering method may be used. In that case, the coverage of the metal film to the wiring trench 42 can be improved.

Next, a hydrogen annealing process is performed. As a result, the Cu film 46 is satisfactorily embedded in the wiring groove 42. The conditions at that time are, for example, about 475 ° C., 3 minutes, 26.6644 × 10 ² Pa, and about 500 sccm.

  Subsequently, as shown in FIG. 63, the Cu film 46 and the Ta film 45a are polished by the CMP method similar to that described in the first and second embodiments, and the excess portion is removed, thereby removing the Cu wiring. 46c is formed. Subsequently, the same anticorrosion process as described in the first and second embodiments and the same cleaning process as described in the first to third embodiments are performed. Thereafter, as shown by hatching in FIG. 64, the ammonia plasma treatment or hydrogen plasma treatment described in the first embodiment is applied to the surfaces of the insulating film 39 and the Cu wiring 46c.

  When the ammonia plasma treatment is performed, SiH bonds and SiN bonds are formed on the surface portion of the silicon oxide film 39. As a result, the film quality, cleanliness, and electrical stability of the surface portion of the silicon oxide film 39 are improved. It is possible to improve the Cu diffusion preventing performance. Further, as described in the first embodiment, it is possible to improve the adhesiveness with the cap film. In addition, CuN is formed on the surface portion of the Cu wiring 46c, and the CuN acts to block the bonding of silicon and oxygen in a later process. As a result, the formation of copper silicide and copper oxide can be prevented. The purity of the can be improved. Accordingly, Cu diffusion can be prevented, and the TDDB life can be improved. Further, since the purity of Cu is high, the resistance of the Cu wiring can be lowered as intended in a state completed as a semiconductor chip. For this reason, it becomes possible to improve the performance of the semiconductor integrated circuit device.

  On the other hand, when the hydrogen plasma treatment was performed, SiH bonds were formed on the surface portion of the silicon oxide film 39, and as a result, almost the same effect as in the ammonia plasma treatment was obtained. Further, according to the experimental results of the present inventors, in the hydrogen plasma treatment, Cu reacts with silicon of about several percent in the subsequent cap film forming step, but in the case of hydrogen annealing, nitrogen plasma treatment or no treatment. Compared to the above, the leakage current can be greatly reduced, and the TDDB life can be improved. In addition, although the resistance of the Cu wiring was inferior to that of ammonia plasma treatment, it could be reduced as compared with hydrogen annealing or nitrogen plasma treatment.

  Thereafter, as shown in FIG. 65, a silicon nitride film (cap film) 47 is deposited as in the first embodiment. Thereafter, as shown in FIG. 60A, a silicon oxide film 48 is deposited on the silicon nitride film 47 by, for example, a plasma CVD method using TEOS (Tetraethoxysilane) gas.

  Next, an example of a method for forming a Cu wiring structure by the dual damascene method will be described with reference to FIGS. 66 (a) to 77 (a) are plan views of the main part during the manufacturing process of the semiconductor integrated circuit device, and FIG. 66 (b) is a cross-sectional view taken along the line AA of FIG. ing. Further, (a) in FIGS. 73 to 76 is a plan view, but the metal film is hatched for easy understanding of the drawings.

  First, after the steps of FIGS. 1 to 5 described in the first embodiment and the like, and after the step of FIG. 50 of the fifth embodiment, as shown in FIG. A prevention film 65 is applied, and a photoresist pattern 66 is formed thereon. The photoresist pattern 66 is a mask pattern for forming a planar circular hole, for example, and is formed by a normal photolithography technique. Subsequently, as shown in FIG. 67, using the photoresist pattern 66 as a mask, the antireflection film 65 exposed from the photoresist pattern 66 is removed by dry etching, and then, the silicon oxide film 39, the silicon nitride film 38, and the silicon oxide are further removed. The through hole 34 is formed by removing the film 31b by dry etching. In the etching process of the silicon oxide film 39, the silicon nitride film 38, and the silicon oxide film 31b, first, non-selection is performed, and the etching selection ratio between the silicon oxide film and the silicon nitride film is increased halfway to Etching is performed under conditions where etching is easier to remove than the silicon nitride film. Thereby, the through hole 34 is drilled using the silicon nitride film 49 as an etching stopper. Therefore, at this stage, the silicon nitride film 49 is exposed from the bottom surface of the through hole 34.

  Next, after removing the photoresist pattern 66 and the antireflection film 65 by an ashing method or the like as shown in FIG. 68, the antireflection film 67 is again oxidized so as to be embedded in the through hole 34 as shown in FIG. The entire surface of the silicon film 39 is applied. Subsequently, as shown in FIG. 70, a photoresist pattern 68 is formed on the antireflection film 67. The photoresist pattern 68 is a mask pattern for forming, for example, a planar belt-like wiring groove, and is formed by a normal photolithography technique. Thereafter, as shown in FIG. 71, using the photoresist pattern 68 as a mask, the antireflection film 67 exposed therefrom is etched away by dry etching, and then the silicon oxide film 39 is further etched away by dry etching. Thus, the wiring trench 42 is formed. In this etching process of the silicon oxide film 39, the etching selectivity between the silicon oxide film and the silicon nitride film is increased, and the silicon oxide film is etched under the condition that it is easier to etch away than the silicon nitride film. Thereby, the wiring trench 42 is formed using the silicon nitride film 38 as an etching stopper. Therefore, at this stage, the silicon nitride film 38 is exposed from the bottom surface of the wiring trench 42.

  Next, after removing the photoresist pattern 68 and the antireflection film 67 by an ashing method or the like as shown in FIG. 72, the silicon nitride films 38 and 49 exposed at the bottoms of the wiring trench 42 and the through hole 34 are selectively removed. To do. In this etching process, the etching selectivity between the silicon oxide film and the silicon nitride film is increased, and the silicon nitride film is etched under conditions that are easier to etch away than the silicon oxide film. Thereby, as shown in FIG. 73, the silicon oxide film 39 and a part of the W wiring 27 are exposed from the bottom surfaces of the wiring trench 42 and the through hole 34. This is for establishing electrical connection between the W wiring 27 and the upper-layer buried wiring. Another purpose is to reduce the wiring capacitance by reducing the silicon nitride films 38 and 49 having a dielectric constant higher than that of the silicon oxide film as much as possible. In this way, the wiring groove 42 and the through hole 34 are formed.

  Next, as shown in FIG. 74, for example, a Ta film 45a (conductive barrier film) is deposited by sputtering under the same conditions as in the single damascene method described in the sixth embodiment. At this time, the barrier film 45a of, for example, less than 10 nm or less and about 6 to 7 nm is deposited on the side walls of the wiring trench 42 and the through hole 34 at the thickest portion or the thinnest portion. Here, Ta is used as the conductive barrier film, but TiN and other exemplified films may be used as described above.

  Subsequently, a Cu film 46 is deposited on the Ta film 45a by sputtering, for example, with a deposition thickness of about 150 nm under the same conditions as in the single damascene method described in the sixth embodiment. As a target at that time, oxygen-free Cu having a high purity of, for example, 99.999% (5N) or more, preferably 99.9999% (6N) or more was used. Thereby, for example, the Cu concentration of the Cu film 46 during film formation can be 99.999% or more, preferably 99.9999% or more. Therefore, high-purity Cu can be deposited on the bottom and side portions of the Cu wiring.

Thereafter, a Cu film 46 is formed by electrolytic plating or the like. The conditions for embedding the Cu film 46 in the through hole 34 by electrolytic plating are, for example, a current density of 0.5 to 1.0 A / dm ² and about 40 seconds. The conditions for embedding the Cu film 46 in the wiring trench 42 are, for example, a current density of 1.0 to 2.0 A / dm ² and about 140 seconds.

  Next, hydrogen annealing is performed in the same manner as in the single damascene method described in the sixth embodiment. This process may not be necessary depending on circumstances.

  Subsequently, as shown in FIG. 75, the Cu film 46 and the Ta film 45a are polished by the CMP method similar to that described in the first and second embodiments, and an excess portion is removed to remove the Cu wiring 46c. Then, the same anticorrosion process as described in the first and second embodiments and the same cleaning process as described in the first to third embodiments are performed. Thereafter, as shown by hatching in FIG. 76, the ammonia plasma treatment or the hydrogen plasma treatment described in the first embodiment is performed on the surfaces of the insulating film 39 and the Cu wiring 46c. As a result, the same effect as described in the single damascene method of the sixth embodiment can be obtained.

  Thereafter, as shown in FIG. 77, a silicon nitride film (cap film) 47 is deposited in the same manner as in the first embodiment, and then, for example, on the silicon nitride film 47 as shown in FIG. A silicon oxide film 48 is deposited by a plasma CVD method using TEOS gas or the like.

  In the sixth embodiment, in addition to the effects obtained by the configuration of the sixth embodiment, the same components as those of the first to fifth embodiments have been described in the first to fifth embodiments. The same effect can be obtained.

(Embodiment 7)
In the seventh embodiment, the ammonia plasma treatment or the hydrogen plasma treatment is performed after a wiring groove or a connection hole is formed. Since both the single damascene method and the dual damascene method are the same, the seventh embodiment will be described with reference to FIGS. 78 and 79 by taking the dual damascene method as an example. 78A, 78A, 79A, 79A, 79A, and 79A are plan views of main parts during the manufacturing process of the semiconductor integrated circuit device, and FIG. 78B is a cross-sectional view taken along the line AA of FIGS. Yes. 78 and 79 (a) are plan views, the metal film is hatched for easy understanding of the drawings.

  In the seventh embodiment, after the manufacturing process described with reference to FIGS. 66 to 73 of the sixth embodiment, the ammonia plasma treatment or the hydrogen plasma treatment is performed as shown by hatching in FIG. Apply.

  When the ammonia plasma treatment is performed, the upper surface of the silicon oxide film 39, the surface of the silicon oxide film 39 on the side wall of the wiring groove 42, the upper surface of the silicon oxide film 31b on the bottom of the wiring groove 42, and the side wall of the through hole 34 are formed. SiH bonds and SiN bonds are formed on the surface of the silicon oxide film 31b (for example, a thin silicon nitride film having a thickness of less than 10 nm is formed). As a result, the upper surface of the silicon oxide film 39 and the side wall portion of the wiring trench 42 are The film quality, cleanliness, and electrical stability of the surface of the silicon oxide film 39, the upper surface of the silicon oxide film 31b at the bottom of the wiring groove 42, and the surface portion of the silicon oxide film 31b at the side wall of the through hole 34 can be improved. It is possible to improve the anti-diffusion performance. In addition, as described in the first embodiment, the adhesion between the silicon oxide film 39 and the cap film can be improved. Note that the nitride film (in this case, the WN film) formed on the upper portion of the W wiring 27 may be removed by performing a light dry etching process after the ammonia plasma process.

  On the other hand, when the hydrogen plasma treatment is performed, the upper surface of the silicon oxide film 39, the surface of the silicon oxide film 39 on the side wall of the wiring groove 42, the upper surface of the silicon oxide film 31 b at the bottom of the wiring groove 42, and the through hole 34. As a result of the formation of SiH bonds on the surface of the silicon oxide film 31b on the side wall, almost the same effect as in the case of ammonia plasma treatment is obtained.

  Subsequently, as shown in FIG. 79, a Ta film 45a and a Cu film 46 are sequentially deposited from the lower layer as in the sixth embodiment. Since the subsequent steps are the same as those described in the sixth embodiment, description thereof will be omitted.

  In the present seventh embodiment, in addition to the effects obtained in the sixth embodiment, by performing ammonia plasma treatment or hydrogen plasma treatment on the side wall portions of the wiring groove 42 and the through hole 34, Since the TDDB life can be further improved, the reliability and yield of the semiconductor integrated circuit device can be further improved.

(Embodiment 8)
A specific example of the wiring structure of the semiconductor integrated circuit device according to the eighth embodiment is shown in FIG. FIG. 80 is a cross-sectional view showing a part of the semiconductor integrated circuit device, in which (a) shows a portion formed by the single damascene method, and (b) shows a portion formed by the dual damascene method. Yes.

  In the eighth embodiment, the conductive barrier film is not formed. That is, only Cu is embedded in the wiring groove 42 or the through hole 34. Therefore, the side wall and the bottom of the Cu wiring 46 c are in direct contact with the silicon oxide film 39 almost directly. However, when the formation method described in the seventh embodiment is adopted, the side wall and the bottom of the Cu wiring 46 c are formed on the side wall and the bottom of the silicon oxide film 39 in the wiring groove 42 and the through hole 34. The thin silicon nitride film is in direct contact.

  The concentration and distribution of components other than Cu in the Cu wiring exemplified by the Cu wiring 46c are the same as those described in the sixth embodiment. The same applies to the material of the interlayer insulating film used in place of the silicon oxide films 31a, 31b, 31, 39, 48 and the like. Further, the dimensions such as the width of the wiring (width of the wiring groove 42) and the interval between adjacent wirings (distance from side to side of the adjacent wiring) are the same as those described in FIG. 60 of the sixth embodiment. It is.

  Also in this eighth embodiment, as described in the sixth embodiment, the TDDB life could be improved. Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved. In the eighth embodiment, the conductive barrier film is not provided, and only the Cu film 46 is embedded in the wiring groove 42 and the through hole 34, so that the wiring resistance is greatly improved. Is possible. Further, the different wiring layers are directly connected without passing through the conductive barrier film (Ta film 45a, TiN film 45, etc.) (here, a structure in which the Cu wiring 46c and the W wiring 27 are directly connected is illustrated). However, since Cu wirings with different wiring layers may be directly connected), the contact resistance between the different layer wirings can be greatly reduced, and the resistance at minute through holes can be reduced. It has become. Therefore, even if the wiring trench 42 and the through hole 34 are miniaturized, the performance of the semiconductor integrated circuit device can be improved.

  The method for forming such a Cu wiring structure is the same as described in the sixth and seventh embodiments. As an example, a method of forming the Cu wiring structure of the eighth embodiment by the dual damascene method will be described with reference to FIGS. Each of FIGS. 81 to 84 is a plan view of the main part of the semiconductor integrated circuit device during the manufacturing process, and FIG. 81B is a cross-sectional view taken along line AA of FIG. ing. Further, although FIGS. 81 to 83A are plan views, the metal film is hatched for easy understanding of the drawings.

  In the eighth embodiment, after the manufacturing process described with reference to FIGS. 66 to 73 of the sixth embodiment, the ammonia plasma treatment or the hydrogen plasma treatment is performed as shown by the hatched area in FIG. Apply.

  By performing ammonia plasma treatment or hydrogen plasma treatment, as described in the seventh embodiment, the upper surface of the silicon oxide film 39, the surface of the silicon oxide film 39 on the side wall of the wiring groove 42, and the bottom of the wiring groove 42 are formed. The film quality, cleanliness and electrical stability of the upper surface of the silicon oxide film 31b and the surface portion of the silicon oxide film 31b on the side wall of the through hole 34 can be improved, and the Cu diffusion preventing performance can be improved. In addition, as described in the first embodiment, the adhesion between the silicon oxide film 39 and the cap film can be improved. As described in the seventh embodiment, the nitride film (in this case, the WN film) formed on the upper portion of the W wiring 27 is removed by performing a light dry etching process after the ammonia plasma process. You may do it.

  Subsequently, as shown in FIG. 82, a high-purity Cu film 46 is deposited in the same manner as the Cu film forming process of the sixth embodiment. That is, in the eighth embodiment, a high-purity Cu film 46 is directly deposited on the silicon oxide film 39 (wiring trench 42) without depositing a conductive barrier film (Ta film 45a, TiN film 45, etc.). And the inside of the through hole 34). It is considered that the Cu film 46 embedded in the wiring groove 42 and the through hole 34 is in direct contact with the thin silicon nitride film at the side wall and the bottom. Therefore, Cu is hard to be ionized at the side wall and bottom of the Cu film 46.

  Thereafter, the Cu film 46 is polished and removed by a CMP method or the like, as described in the sixth embodiment, and then a cleaning process is performed. Thereby, as shown in FIG. 83, Cu wiring 46c is formed. The Cu wiring 46c is basically formed of Cu.

  Next, as shown by hatching in FIG. 83, the ammonia plasma treatment or the hydrogen plasma treatment is performed on the upper surface of the silicon oxide film 39 and the upper surface (exposed surface) of the Cu wiring 46c. Accordingly, as described in the sixth embodiment, Cu diffusion can be prevented and the TDDB life can be improved. In addition, since the purity of Cu can be kept high, the resistance of the Cu wiring can be lowered in a state completed as a semiconductor chip.

  Subsequently, as shown in FIG. 84, a silicon nitride film (cap film) 47 is deposited in the same manner as in the first embodiment and the like, as described in the sixth embodiment. As shown in FIG. 80B, the silicon oxide film 48 is deposited by, for example, a plasma CVD method using TEOS gas.

  In the eighth embodiment, in addition to the effects obtained by the configurations of the first to seventh embodiments, the following effects can be obtained. That is, by not providing the conductive barrier film, it is possible to greatly reduce the resistance of the Cu wiring 46c. Therefore, the performance of the semiconductor integrated circuit device can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, it is needless to say that Embodiments 1 to 8 can be applied in combination with each other as well as being independently applicable. For example, the technology of the second embodiment is applied to perform chemical mechanical polishing without abrasive grains, and then the third embodiment is applied to perform acid treatment, and the first embodiment is further applied to ammonia or hydrogen. Plasma treatment may be performed.

  In the first to eighth embodiments, the formation of the silicon nitride film 47 after the ammonia plasma processing is continuously performed without breaking the vacuum. However, after the ammonia plasma processing, the vacuum breaking is performed once, and then the nitriding is performed. A silicon film 47 may be formed. Although the effect of the present invention can be more effectively achieved without vacuum breakage, a thin nitride layer is formed by the ammonia plasma treatment, so that the formation of an oxide layer is suppressed even when vacuum break is performed and exposed to the atmosphere. it can. Therefore, even when the vacuum breaks, the effect of the present embodiment can be achieved to some extent.

  In the first to eighth embodiments, the case where the Cu film is formed by the sputtering method has been described. However, if the Cu can be secured with a high purity, a plating method or a CVD method can be used instead of the sputtering method. Also good.

  In the above description, the case where the invention made mainly by the present inventor is applied to the CMOS-LSI technology which is the field of use as the background has been described. However, the present invention is not limited to this. For example, DRAM (Dynamic Random Access Memory) ), SRAM (Static Random Access Memory), flash memory (EEPROM: Electric Erasable Programmable Read Only Memory), FRAM (Ferroelectric Random Access Memory), etc. The present invention can also be applied to a semiconductor integrated circuit device having a circuit or a mixed semiconductor integrated circuit device in which the memory circuit and the logic circuit are provided on the same semiconductor substrate. The present invention is applicable to a semiconductor integrated circuit device, a semiconductor device, an electronic circuit device, an electronic device, or the like having at least a fine copper wiring structure.

It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment (Embodiment 1) of this invention. FIG. 3 is a main-portion cross-sectional view of the semiconductor substrate showing the manufacturing method in Embodiment 1; FIG. 3 is a main-portion cross-sectional view of the semiconductor substrate showing the manufacturing method in Embodiment 1; FIG. 3 is a main-portion cross-sectional view of the semiconductor substrate showing the manufacturing method in Embodiment 1; FIG. 3 is a main-portion cross-sectional view of the semiconductor substrate showing the manufacturing method in Embodiment 1; (A) is a top view which shows the manufacturing method of Embodiment 1, (b) is principal part sectional drawing which shows the manufacturing method of Embodiment 1. FIG. (A) is a top view which shows the manufacturing method of Embodiment 1, (b) is principal part sectional drawing which shows the manufacturing method of Embodiment 1. FIG. FIG. 3 is a main-portion cross-sectional view of the semiconductor substrate showing the manufacturing method in Embodiment 1; It is the schematic which shows an example of the whole structure of the CMP apparatus used for formation of embedded Cu wiring. It is the schematic which shows a part of CMP apparatus used for formation of embedded Cu wiring. It is a perspective view which shows the scrub cleaning method of a wafer. It is the schematic which shows the other example of the whole structure of the CMP apparatus used for formation of embedded Cu wiring. It is the schematic which shows the further another example of the whole structure of the CMP apparatus used for formation of embedded Cu wiring. FIG. 3 is a main-portion cross-sectional view of the semiconductor substrate showing the manufacturing method in Embodiment 1; (A) is sectional drawing which showed the outline | summary of the plasma processing apparatus used for ammonia plasma processing and deposition of a silicon nitride film, (b) is also a top view. FIG. 3 is a main-portion cross-sectional view of the semiconductor substrate showing the manufacturing method in Embodiment 1; FIG. 3 is a main-portion cross-sectional view of the semiconductor substrate showing the manufacturing method in Embodiment 1; 5 is a flowchart showing a method for manufacturing the semiconductor integrated circuit device of the first embodiment. FIG. 1 is a cross-sectional view showing an outline of a semiconductor integrated circuit device according to a first embodiment. It is a graph which shows TDDB lifetime. It is a graph which shows TDDB lifetime. (A)-(d) is a graph which shows XPS data. (A)-(d) is a graph which shows XPS data. (A)-(d) is a graph which shows XPS data. (A)-(e) is a graph which shows XPS data. (F) is a table | surface figure which shows a composition ratio. (A)-(d) is a graph which shows a mass spectrometry result. (A)-(d) is a graph which shows a mass spectrometry result. It is a graph which shows wiring resistance. (A) is sectional drawing which traced the TEM photograph which shows the wiring part in the case of no process, (b) is sectional drawing which traced the TEM photograph which shows the wiring part of Embodiment 1. (A)-(c) is sectional drawing which traced the TEM photograph shown as a comparison. (A) And (b) is explanatory drawing which shows the mechanism of TDDB degradation. (A) And (b) is explanatory drawing which shows the mechanism of TDDB improvement. It is a graph which shows TDDB lifetime. It is the schematic which shows an example of the whole structure of the CMP apparatus used for the manufacturing method of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is the schematic which shows a part of CMP apparatus used for formation of embedded Cu wiring. It is the schematic of the CMP apparatus which shows the grinding | polishing state of Cu film | membrane. FIG. 10 is a main-portion cross-sectional view of the semiconductor substrate showing the method of manufacturing the semiconductor integrated circuit device of the second embodiment. (A) is a principal part top view of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device of Embodiment 2, (b) is also principal part sectional drawing. FIG. 10 is a main-portion cross-sectional view of the semiconductor substrate showing the method of manufacturing the semiconductor integrated circuit device of the second embodiment. (A) is a principal part top view of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device of Embodiment 2, (b) is also principal part sectional drawing. FIG. 10 is a main-portion cross-sectional view of the semiconductor substrate showing the method of manufacturing the semiconductor integrated circuit device of the second embodiment. (A) is a principal part top view of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device of Embodiment 2, (b) is also principal part sectional drawing. FIG. 10 is a flowchart showing a method for manufacturing the semiconductor integrated circuit device of the second embodiment. It is a graph which shows TDDB lifetime. FIG. 10 is a flowchart showing a method for manufacturing the semiconductor integrated circuit device of the third embodiment. It is a graph which shows TDDB lifetime. FIG. 10 is a main-portion cross-sectional view of the semiconductor substrate showing the method of manufacturing the semiconductor integrated circuit device of Embodiment 4; (A) is a principal part top view of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device of Embodiment 4, (b) is also principal part sectional drawing. FIG. 10 is a main-portion cross-sectional view of the semiconductor substrate showing the method of manufacturing the semiconductor integrated circuit device of Embodiment 4; It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device of other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device of other embodiment of this invention. (A) is a principal part top view of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device of other embodiment, (b) is also principal part sectional drawing. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device of other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device of other embodiment of this invention. It is a graph which shows the data which measured the TDDB characteristic of copper wiring, aluminum wiring, and tungsten wiring. It is a graph which shows the quantity of the silicon contained in the copper wiring at the time of performing each process. It is a graph which shows the conductive barrier film thickness dependence in the resistance of a buried copper wiring. It is a graph which shows the conductive barrier film thickness dependence of TDDB characteristic. It is a graph which shows the TDDB characteristic after annealing treatment in the case where there is no conductive barrier film and the thickness is less than 10 nm. (A) And (b) is principal part sectional drawing of the copper embedding wiring layer of the semiconductor integrated circuit device which is other Embodiment of this invention. (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device which is embodiment of this invention, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 61, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 62, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 63, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 64, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device which is embodiment of this invention, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 66, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 67, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 68, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 69, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 70, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 71, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 72, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 73, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 74, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 75, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 76, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device which is embodiment of this invention, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 78, (b) is sectional drawing of the AA of (a). (A) And (b) is principal part sectional drawing of the copper embedding wiring layer of the semiconductor integrated circuit device which is further another embodiment of this invention. (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device which is embodiment of this invention, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 81, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 82, (b) is sectional drawing of the AA of (a). (A) is a principal part top view in the manufacturing process of the semiconductor integrated circuit device following FIG. 83, (b) is sectional drawing of the AA of (a). The sample used for the TDDB lifetime measurement of this application is shown, (a) is a top view, (b) and (c) are explanatory drawings which each show the BB 'line cross section and CC' line cross section in (a). is there. It is the conceptual diagram which showed the outline | summary of the measurement. It is an example of a current-voltage measurement result. It is explanatory drawing of the coverage in the wiring groove | channel or connection hole of an electroconductive barrier film.

Explanation of symbols

1 substrate 2 element isolation trench 3 silicon oxide film 4 p-type well 5 n-type well 6 gate insulating film 7 gate electrode 9 silicide layer 11 n ⁻ type semiconductor region 12 p ⁻ type semiconductor region 13 sidewall spacer 14 n ⁺ type semiconductor region 15 p ⁺ type semiconductor region 18 silicon oxide film 20-22 contact hole 23 plug 24-30 W wiring 28-30 Cu wiring 31 silicon oxide film 31a silicon oxide film 31b silicon oxide film 32-36 through hole 37 plug 38 silicon nitride film 39 Silicon oxide film 40 to 44 Wiring groove 45 TiN film 46 Cu film 46a to 46e Cu wiring 47 Silicon nitride film (cap film)
48 Silicon oxide film 49 Silicon nitride films 50 to 54 Wiring groove 60 Insulating film 61 Wiring groove 62 Barrier film 65 Antireflection film 66 Photoresist pattern 67 Antireflection film 68 Photoresist pattern 100 CMP apparatus 101 Housing 102 Rotating shaft 103 Motor 104 Polishing board 105 Polishing pad 106 Wafer carrier 106a Recess 107 Drive shaft 108 Slurry supply tube 109 Dresser 110 Drive shaft 120 Loader 121A Brush 130 Polishing processing unit 140 Corrosion processing unit 150 Immersion processing unit 160 Post-cleaning processing unit 170 Unloader 200 CMP apparatus 220 Loader 230 Polishing processing unit 240 Drying processing unit 250 Post-cleaning processing unit 260 Unloader 301 Load lock chamber 302a Processing chamber 302b Processing chamber 303 Cassette interface 304 Robot 305 Gate valve 306 Susceptor 307 Baffle plate 308 Support member 309 Electrode 310 Insulating plate 311 Reflecting unit 312 Lamp 313 Infrared ray 314 Quartz window 315 Gas port 316 Vacuum manifold 400 CMP apparatus 401 Polishing processing unit 402 Post cleaning unit 403A First surface plate 403B Second surface plate 404 Clean station 405 Rotating arm 406 Loader 407 Unloader 408 Loader 409A First cleaning unit 409B Second cleaning unit 410 Spin dryer 411 Unloader 412 Drive mechanism 413 Polishing pad 414 Drive mechanism 415 Wafer carrier 416 Wafer chuck 417 Retainer ring 418 Slurry supply pipe 418a Slurry supply pipe 418b Slurry supply pipe 419 Drive mechanism 420 Dresser 430 Light shielding wall 501 Insulating film 502 Insulating film 503 Wiring 504 Nitride Silicon film 505 a silicon oxide film 507 connecting holes 508 plug Qn n-channel type MISFET
Qp p-channel MISFET

Claims (6)

(A) forming a first insulating film on the semiconductor substrate;
(B) after the step (a), forming a groove and a hole connected to the bottom surface of the groove in the first insulating film;
(C) after the step (b), subjecting the surface of the first insulating film including the inside of the groove and the hole to an ammonia plasma treatment;
(D) After the step (c), a step of forming a conductive film containing Cu as a main component so as to be in direct contact with the first insulating film;
(E) After the step (d), the step of embedding the conductive film in the groove and in the hole by removing the conductive film outside the groove and outside the hole;
(F) A step of performing an ammonia plasma treatment on the surface of the first insulating film and the surface of the conductive film after the step (e);
Have
In the method of manufacturing a semiconductor integrated circuit device, the first insulating film including the inside of the groove and the inside of the hole is nitrided in a region less than 10 nm from the surface by the step (c). In the manufacturing method of the semiconductor integrated circuit device according to claim 1,
The method of manufacturing a semiconductor integrated circuit device, wherein the step (e) is performed by a CMP method. (A) forming a first insulating film on the semiconductor substrate;
(B) after the step (a), forming a groove and a hole connected to the bottom surface of the groove in the first insulating film;
(C) after the step (b), subjecting the surface of the first insulating film including the inside of the groove and the hole to an ammonia plasma treatment;
(D) After the step (c), by using a Cu target having a purity of 99.999% or more, a step of forming a seed layer so as to be in direct contact with the first insulating film;
(E) After the step (d), forming a conductive film containing Cu as a main component on the seed layer;
(F) After the step (e), the seed layer and the conductive film outside the groove and outside the hole are removed, and the seed layer and the conductive film are embedded in the groove and in the hole. A step of forming the first wiring;
(G) A step of performing an ammonia plasma treatment on the surface of the first insulating film and the surface of the first wiring after the step (f);
Have
In the method of manufacturing a semiconductor integrated circuit device, the first insulating film including the inside of the groove and the inside of the hole is nitrided in a region less than 10 nm from the surface by the step (c). (A) forming a first insulating film on the semiconductor substrate;
(B) after the step (a), forming a groove and a hole connected to the bottom surface of the groove in the first insulating film;
(C) after the step (b), subjecting the surface of the first insulating film including the inside of the groove and the hole to an ammonia plasma treatment;
(D) After the step (c), by using a Cu target having a purity of 99.999% or more, a step of forming a seed layer so as to be in direct contact with the first insulating film;
(E) After the step (d), forming a conductive film containing Cu as a main component on the seed layer;
(F) After the step (e), the seed layer and the conductive film outside the groove and outside the hole are removed, and the seed layer and the conductive film are embedded in the groove and in the hole. A step of forming the first wiring;
(G) A step of performing an ammonia plasma treatment on the surface of the first insulating film and the surface of the first wiring after the step (f);
(H) After the step (g), a step of forming a barrier insulating film on the first insulating film and the first wiring by a plasma CVD method;
Have
The concentration of components other than Cu in the first wiring at the time of completing the step (h) is 0.8 At. % Or less,
In the method of manufacturing a semiconductor integrated circuit device, the first insulating film including the inside of the groove and the inside of the hole is nitrided in a region less than 10 nm from the surface by the step (c). The method of manufacturing a semiconductor integrated circuit device according to claim 3 or 4,
The method of manufacturing a semiconductor integrated circuit device, wherein the step (f) is performed by a CMP method. In the manufacturing method of the semiconductor integrated circuit device according to any one of claims 1 to 5,
A method of manufacturing a semiconductor integrated circuit device, wherein the groove has a width of 0.4 μm or less.

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