JP5204789B2 - めっきピラーパッケージの形成 - Google Patents
めっきピラーパッケージの形成 Download PDFInfo
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- JP5204789B2 JP5204789B2 JP2009549725A JP2009549725A JP5204789B2 JP 5204789 B2 JP5204789 B2 JP 5204789B2 JP 2009549725 A JP2009549725 A JP 2009549725A JP 2009549725 A JP2009549725 A JP 2009549725A JP 5204789 B2 JP5204789 B2 JP 5204789B2
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- Prior art keywords
- substrate
- package
- seed layer
- forming
- sacrificial layer
- Prior art date
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- Expired - Fee Related
Links
- 230000015572 biosynthetic process Effects 0.000 title description 4
- 238000000034 method Methods 0.000 claims description 56
- 239000000758 substrate Substances 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 28
- 238000007747 plating Methods 0.000 claims description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000000945 filler Substances 0.000 claims description 9
- 238000009713 electroplating Methods 0.000 claims description 5
- 238000007772 electroless plating Methods 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims 1
- 238000012986 modification Methods 0.000 description 13
- 230000004048 modification Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 9
- 238000013459 approach Methods 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 8
- 238000001465 metallisation Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000005022 packaging material Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- BGTFCAQCKWKTRL-YDEUACAXSA-N chembl1095986 Chemical compound C1[C@@H](N)[C@@H](O)[C@H](C)O[C@H]1O[C@@H]([C@H]1C(N[C@H](C2=CC(O)=CC(O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O)=C2C=2C(O)=CC=C(C=2)[C@@H](NC(=O)[C@@H]2NC(=O)[C@@H]3C=4C=C(C(=C(O)C=4)C)OC=4C(O)=CC=C(C=4)[C@@H](N)C(=O)N[C@@H](C(=O)N3)[C@H](O)C=3C=CC(O4)=CC=3)C(=O)N1)C(O)=O)=O)C(C=C1)=CC=C1OC1=C(O[C@@H]3[C@H]([C@H](O)[C@@H](O)[C@H](CO[C@@H]5[C@H]([C@@H](O)[C@H](O)[C@@H](C)O5)O)O3)O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O[C@@H]3[C@H]([C@H](O)[C@@H](CO)O3)O)C4=CC2=C1 BGTFCAQCKWKTRL-YDEUACAXSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electroplating Methods And Accessories (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
Claims (15)
- 基板上に第1の犠牲層を設ける工程であって、前記基板はその上に設けられた第1のシード層を含む、工程と、
前記第1の犠牲層に開口を形成して、前記第1のシード層の一部分を露出させる工程と、
前記第1のシード層の前記露出された部分に導電性金属でめっきを施してピラーを形成する工程と、
前記第1の犠牲層を除去する工程と、
前記ピラーに隣接して前記基板上に第1の充填材料を設ける工程であって、前記第1の充填材料の外表面が、前記ピラーの外表面と共に実質的に平面状の表面を形成する、工程と、
前記基板を除去する工程と、
を備えるパッケージの形成方法。 - 前記第1の犠牲層が形成される前に前記基板上に前記第1のシード層を形成する工程をさらに備える、請求項1記載の方法。
- 前記第1のシード層を形成する工程は、接点およびトレースを形成する工程を備える、請求項2記載の方法。
- 前記接点およびトレースを形成する工程は、前記接点および前記トレースをメタライジングする工程を備える、請求項3記載の方法。
- 前記第1の犠牲層は、フォトレジストである、請求項1記載の方法。
- 前記第1の充填材料は、絶縁体である、請求項1記載の方法。
- 前記めっきを施す工程は、電気めっきを施す工程または無電解めっきを施す工程を備える、請求項1記載の方法。
- 前記開口のうちの少なくとも幾つかが、50μm以下の幅を有する、請求項1記載の方法。
- 前記開口のうちの少なくとも幾つかが、50μm以下のピッチを有する、請求項8記載の方法。
- 前記開口のうちの少なくとも幾つかが、20μm以下の幅を有する、請求項1記載の方法。
- 前記開口のうちの少なくとも幾つかが、20μm以下のピッチを有する、請求項10記載の方法。
- 前記開口のうちの第1のセットが第1の幅を有し、前記開口のうちの第2のセットが前記第1の幅とは異なる第2の幅を有する、請求項1記載の方法。
- 前記ピラーおよび前記第1の充填材料上に第2のシード層を設ける工程と、
前記第2のシード層、前記ピラー、および前記第1の充填材料上に第2の犠牲層を設ける工程と、
前記第2の犠牲層に開口を形成する工程と、
前記第2の犠牲層の前記開口内にピラーを形成する工程と、
前記第2の犠牲層を除去する工程と、
前記第2のシード層および前記第1の充填材料上に第2の充填材料を設ける工程と、
をさらに備える請求項1記載の方法。 - 前記第1の充填材料は、硬化性または自硬性の材料を備える、請求項1記載の方法。
- 請求項1乃至14のいずれか1項に記載する方法を用いて形成されるデバイスであって、
複数の配線ピラーと、
前記複数の配線ピラーを取り巻く前記第1の充填材料であって、前記複数の配線ピラーは前記第1の充填材料の第1の面から前記第1の充填材料の反対の面まで延びる、第1の充填材料と、
前記複数の配線ピラーのうちの少なくとも2つにそれぞれ接続される複数のトレースと、
前記複数のトレースのうちの少なくとも1つに結合される第1のチップと、
を備えるデバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/675,731 | 2007-02-16 | ||
US11/675,731 US7670874B2 (en) | 2007-02-16 | 2007-02-16 | Plated pillar package formation |
PCT/US2008/053994 WO2008101102A1 (en) | 2007-02-16 | 2008-02-14 | Plated pillar package formation |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010519410A JP2010519410A (ja) | 2010-06-03 |
JP2010519410A5 JP2010519410A5 (ja) | 2010-10-28 |
JP5204789B2 true JP5204789B2 (ja) | 2013-06-05 |
Family
ID=39363948
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009549725A Expired - Fee Related JP5204789B2 (ja) | 2007-02-16 | 2008-02-14 | めっきピラーパッケージの形成 |
Country Status (6)
Country | Link |
---|---|
US (2) | US7670874B2 (ja) |
EP (1) | EP2118924A1 (ja) |
JP (1) | JP5204789B2 (ja) |
KR (2) | KR101225921B1 (ja) |
CN (2) | CN103050437A (ja) |
WO (1) | WO2008101102A1 (ja) |
Families Citing this family (5)
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KR101023296B1 (ko) * | 2009-11-09 | 2011-03-18 | 삼성전기주식회사 | 포스트 범프 형성방법 |
US8492171B2 (en) | 2011-07-21 | 2013-07-23 | International Business Machines Corporation | Techniques and structures for testing integrated circuits in flip-chip assemblies |
US9087777B2 (en) * | 2013-03-14 | 2015-07-21 | United Test And Assembly Center Ltd. | Semiconductor packages and methods of packaging semiconductor devices |
CN205016513U (zh) * | 2014-10-24 | 2016-02-03 | 胡迪群 | 具有封装胶体支撑的电路重新分布层结构 |
WO2018125066A1 (en) * | 2016-12-28 | 2018-07-05 | Intel Corporation | Package substrate having copper alloy sputter seed layer and high density interconnects |
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-
2007
- 2007-02-16 US US11/675,731 patent/US7670874B2/en not_active Expired - Fee Related
-
2008
- 2008-02-14 JP JP2009549725A patent/JP5204789B2/ja not_active Expired - Fee Related
- 2008-02-14 CN CN2012105183353A patent/CN103050437A/zh active Pending
- 2008-02-14 KR KR1020127003235A patent/KR101225921B1/ko not_active IP Right Cessation
- 2008-02-14 EP EP08729889A patent/EP2118924A1/en not_active Withdrawn
- 2008-02-14 CN CN200880005012A patent/CN101715606A/zh active Pending
- 2008-02-14 KR KR1020097018959A patent/KR20090119901A/ko active Search and Examination
- 2008-02-14 WO PCT/US2008/053994 patent/WO2008101102A1/en active Application Filing
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Publication number | Publication date |
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CN101715606A (zh) | 2010-05-26 |
CN103050437A (zh) | 2013-04-17 |
KR101225921B1 (ko) | 2013-01-25 |
US7670874B2 (en) | 2010-03-02 |
US20090174079A1 (en) | 2009-07-09 |
KR20120045008A (ko) | 2012-05-08 |
WO2008101102A1 (en) | 2008-08-21 |
US20080197508A1 (en) | 2008-08-21 |
JP2010519410A (ja) | 2010-06-03 |
EP2118924A1 (en) | 2009-11-18 |
KR20090119901A (ko) | 2009-11-20 |
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