JP2010519410A5 - - Google Patents

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JP2010519410A5
JP2010519410A5 JP2009549725A JP2009549725A JP2010519410A5 JP 2010519410 A5 JP2010519410 A5 JP 2010519410A5 JP 2009549725 A JP2009549725 A JP 2009549725A JP 2009549725 A JP2009549725 A JP 2009549725A JP 2010519410 A5 JP2010519410 A5 JP 2010519410A5
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Prior art keywords
forming
sacrificial layer
filler material
seed layer
openings
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JP2009549725A
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JP5204789B2 (ja
JP2010519410A (ja
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Priority claimed from US11/675,731 external-priority patent/US7670874B2/en
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Claims (15)

  1. 基板上に第1の犠牲層を設ける工程であって、前記基板はその上に設けられた第1のシード層を含む、工程と、
    前記第1の犠牲層に開口を形成して、前記第1のシード層の一部分を露出させる工程と、
    前記第1のシード層の前記露出された部分に導電性金属でめっきを施してピラーを形成する工程と、
    前記第1の犠牲層を除去する工程と、
    前記ピラーに隣接して前記基板上に第1の充填材料を設ける工程であって、前記第1の充填材料の外表面が、前記ピラーの外表面と共に実質的に平面状の表面を形成する、工程と、
    前記基板を除去する工程と、
    を備えるパッケージの形成方法。
  2. 前記第1の犠牲層が形成される前に前記基板上に前記第1のシード層を形成する工程をさらに備える、請求項1記載の方法。
  3. 前記第1のシード層を形成する工程は、接点およびトレースを形成する工程を備える、請求項2記載の方法。
  4. 前記接点およびトレースを形成する工程は、前記接点および前記トレースをメタライジングする工程を備える、請求項3記載の方法。
  5. 前記第1の犠牲層は、フォトレジストである、請求項1記載の方法。
  6. 前記第1の充填材料は、絶縁体である、請求項1記載の方法。
  7. 前記めっきを施す工程は、電気めっきを施す工程または無電解めっきを施す工程を備える、請求項1記載の方法。
  8. 前記開口のうちの少なくとも幾つかが、50μm以下の幅を有する、請求項1記載の方法。
  9. 前記開口のうちの少なくとも幾つかが、50μm以下のピッチを有する、請求項8記載の方法。
  10. 前記開口のうちの少なくとも幾つかが、20μm以下の幅を有する、請求項1記載の方法。
  11. 前記開口のうちの少なくとも幾つかが、20μm以下のピッチを有する、請求項10記載の方法。
  12. 前記開口のうちの第1のセットが第1の幅を有し、前記開口のうちの第2のセットが前記第1の幅とは異なる第2の幅を有する、請求項1記載の方法。
  13. 前記ピラーおよび前記第1の充填材料上に第2のシード層を設ける工程と、
    前記第2のシード層、前記ピラー、および前記第1の充填材料上に第2の犠牲層を設ける工程と、
    前記第2の犠牲層に開口を形成する工程と、
    前記第2の犠牲層の前記開口内にピラーを形成する工程と、
    前記第2の犠牲層を除去する工程と、
    前記第2のシード層および前記第1の充填材料上に第2の充填材料を設ける工程と、
    をさらに備える請求項1記載の方法。
  14. 前記第1の充填材料は、硬化性または自硬性の材料を備える、請求項1記載の方法。
  15. 請求項1乃至14のいずれか1項に記載する方法を用いて形成されるデバイスであって、
    複数の配線ピラーと、
    前記複数の配線ピラーを取り巻く前記第1の充填材料であって、前記複数の配線ピラーは前記第1の充填材料の第1の面から前記第1の充填材料の反対の面まで延びる、第1の充填材料と、
    前記複数の配線ピラーのうちの少なくとも2つにそれぞれ接続される複数のトレースと、
    前記複数のトレースのうちの少なくとも1つに結合される第1のチップと、
    を備えるデバイス。
JP2009549725A 2007-02-16 2008-02-14 めっきピラーパッケージの形成 Expired - Fee Related JP5204789B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/675,731 US7670874B2 (en) 2007-02-16 2007-02-16 Plated pillar package formation
US11/675,731 2007-02-16
PCT/US2008/053994 WO2008101102A1 (en) 2007-02-16 2008-02-14 Plated pillar package formation

Publications (3)

Publication Number Publication Date
JP2010519410A JP2010519410A (ja) 2010-06-03
JP2010519410A5 true JP2010519410A5 (ja) 2010-10-28
JP5204789B2 JP5204789B2 (ja) 2013-06-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009549725A Expired - Fee Related JP5204789B2 (ja) 2007-02-16 2008-02-14 めっきピラーパッケージの形成

Country Status (6)

Country Link
US (2) US7670874B2 (ja)
EP (1) EP2118924A1 (ja)
JP (1) JP5204789B2 (ja)
KR (2) KR20090119901A (ja)
CN (2) CN103050437A (ja)
WO (1) WO2008101102A1 (ja)

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US11037802B2 (en) 2016-12-28 2021-06-15 Intel Corporation Package substrate having copper alloy sputter seed layer and high density interconnects

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