US20090174079A1 - Plated pillar package formation - Google Patents

Plated pillar package formation Download PDF

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US20090174079A1
US20090174079A1 US12404872 US40487209A US2009174079A1 US 20090174079 A1 US20090174079 A1 US 20090174079A1 US 12404872 US12404872 US 12404872 US 40487209 A US40487209 A US 40487209A US 2009174079 A1 US2009174079 A1 US 2009174079A1
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plurality
pillars
interconnect
device
fill material
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US12404872
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John Trezza
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Cufer Asset Ltd LLC
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Cufer Asset Ltd LLC
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A device includes a first plurality of interconnects, a first fill material surrounding the first plurality of interconnects, a first plurality of traces, and a first chip. The first plurality of interconnects extend from a first side of the fill material to an opposite side of the fill material. Each of the traces is connected to at least two of the first plurality of interconnects. The first chip is coupled to at least one of the first plurality of traces.

Description

    CROSS-REFERENCE TO RELATED PATENT APPLICATIONS
  • This application is a Divisional of U.S. patent application Ser. No. 11/675,731, filed Feb. 16, 2007, the entire disclosure of which is incorporated herein by reference.
  • BACKGROUND
  • The present invention relates to electrical connections and, more particularly, to a process of forming a package for such electrical connections.
  • U.S. patent application Ser. Nos. 11/329,481, 11/329,506, 11/329,539, 11/329,540, 11/329,556, 11/329,557, 11/329,558, 11/329,574, 11/329,575, 11/329,576, 11/329,873, 11/329,874, 11/329,875, 11/329,883, 11/329,885, 11/329,886, 11/329,887, 11/329,952, 11/329,953, 11/329,955, 11/330,011 and 11/422,551, incorporated herein by reference, describe various techniques for forming small, deep vias in, and electrical contacts for, semiconductor wafers. Our techniques allow for via densities and placement that was previously unachievable and can be performed on a chip, die or wafer scale. However, if these techniques are used to form high density interconnects, there is presently no “off the shelf” or low cost commercially available packaging that can be used with them.
  • There is therefore a present need for low cost packaging that can be used with such high density interconnects.
  • SUMMARY
  • According to an exemplary embodiment, a device includes a first plurality of interconnects, a first fill material surrounding the first plurality of interconnects, a first plurality of traces, and a first chip. The first plurality of interconnects extend from a first side of the fill material to an opposite side of the fill material. Each of the traces is connected to at least two of the first plurality of interconnects. The first chip is coupled to at least one of the first plurality of traces.
  • According to another exemplary embodiment, a device includes a first plurality of interconnect pillars, a first fill material surrounding the first plurality of interconnect pillars, a second plurality of interconnect pillars, and a second fill material surrounding the second plurality of interconnect pillars. The first plurality of interconnect pillars extend from a first side of the first fill material to an opposite side of the first fill material. The second plurality of interconnect pillars extend from a first side of the second fill material to an opposite side of the second fill material. At least one of the first plurality of interconnect pillars is coupled to at least one of the second plurality of interconnect pillars.
  • According to another exemplary embodiment, a device includes a first plurality of interconnect pillars, a first fill material surrounding the first plurality of interconnect pillars, a first chip, a second plurality of interconnect pillars, and a second fill material surrounding the second plurality of interconnect pillars. The first plurality of interconnect pillars extend from a first side of the first fill material to an opposite side of the first fill material. The second plurality of interconnect pillars extend from a first side of the second fill material to an opposite side of the second fill material. The first chip is coupled to at least one of the first plurality of electrically conductive pillars and to at least one of the second plurality of electrically conductive pillars.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates, in simplified form, a portion of a substrate 100 that will serve as the base for the process described herein;
  • FIG. 2 illustrates, in simplified form, the portion of the substrate 100 after a seed layer has been deposited by metalizing;
  • FIG. 3 illustrates, in simplified form, the portion of the substrate of FIG. 2 in which a photoresist has been applied and patterned to create openings down to the seed layer;
  • FIG. 4 illustrates, in simplified form, the portion of the substrate after plating is complete;
  • FIG. 5 illustrates, in simplified form, the portion of the substrate after removal of the photoresist;
  • FIG. 6 illustrates, in simplified form, the portion of the substrate after the package material is fully hardened;
  • FIG. 7 illustrates, in simplified form, the package after removal of the substrate and seed layer;
  • FIG. 8 illustrates, in simplified form, the underside of a portion of the package containing the cross section of FIG. 7;
  • FIG. 9 through FIG. 16 collectively illustrate, in simplified form, a more sophisticated variant of the instant approach to formation of a plated pillar package;
  • FIG. 17 illustrates, in simplified form, a package variant created by using the variant of FIG. 10 through FIG. 15 as a substrate for the basic approach of FIG. 2 through FIG. 7; and
  • FIG. 18 illustrates, in simplified form, a package variant created by using the variant of FIG. 10 through FIG. 15, to create a first package and then using that package as the substrate in the same variant approach.
  • DETAILED DESCRIPTION
  • We have devised a way to create a low cost package that can be used with a chip or a die containing densely packed small vias, such as described in the above-incorporated applications. Our approach allows for low cost, accurate formation of the package connections on extremely small pitches, on the order of 25 μm or less and, in many cases 10 μm or less. Moreover, the same approach can be applied with different materials to allow the package to be tailored to the particular application in terms of, for example, thermal expansion, strength, flexure/rigidity, or to be tailored to a particular required or desired thickness.
  • One aspect of our approach involves plating pillars of electrically conductive material up from a seed layer located on a substrate, surrounding the pillars with a fill material so that the pillars and fill material collectively define a first package, and removing the substrate from the first package.
  • Another aspect of our approach involves a process for forming a package. The process involves applying a photoresist onto a seed layer-bearing substrate, defining openings in the photoresist at locations where interconnects are to be located, the openings extending down to and exposing the seed layer at the locations, plating the exposed seed layer until a desired height of plating metal has been built up, removing the photoresist while leaving the built up plating metal in place, applying a fill material into a volume created by the removal of the photoresist, and removing the substrate.
  • The advantages and features described herein are a few of the many advantages and features available from representative embodiments and are presented only to assist in understanding the invention. It should be understood that they are not to be considered limitations on the invention as defined by the claims, or limitations on equivalents to the claims. For instance, some of these advantages are mutually contradictory, in that they cannot be simultaneously present in a single embodiment. Similarly, some advantages are applicable to one aspect of the invention, and inapplicable to others. Thus, this summary of features and advantages should not be considered dispositive in determining equivalence. Additional features and advantages of the invention will become apparent in the following description, from the drawings, and from the claims.
  • In general overview, our approach builds up a series of interconnects on a wafer or other suitable substrate using photolithographic and plating techniques. Thus, we can form small interconnects, on extremely tight pitches, because the ability to do so is only limited by the ability to photolithographically define the interconnects and the ability to plate them to their desired height. Moreover, packages formed using an approach herein can have a broad range of thicknesses extending from as thin as about 10 μm to even 1000 μm or more (note that, the measurements referred to throughout this description are not intended to be exact but rather, should be considered to be plus or minus the tolerances in measurement or manufacture acceptable for the particular application).
  • FIG. 1 through FIG. 8 collectively illustrate, in simplified form, a basic version of the instant approach to formation of a plated pillar package.
  • FIG. 1 illustrates, in simplified form, a portion of a substrate 100 that will serve as the base for the process described herein. Depending upon the particular implementation, the substrate 100 can be a semiconductor wafer, a wafer of ceramic, or some other material of having the characteristics that it can withstand the operations involved in the process and, ultimately, can be removed without damaging the formed package.
  • Ideally, because of the potential narrow pitches involved between the interconnects, the substrate 100 will be very flat (e.g. if a standard 8″ wafer, it should have an overall bow or dish of no more than, and preferably much less than, 10 μm).
  • The process begins by metalizing the substrate 100 to apply a thin layer of metal onto the substrate 100 and thereby form a seed layer for a subsequent plating operation (electroless or electroplating). The metalization can be done through, for example, a vapor deposition process (chemical or physical) or any other suitable process. In some variants, the substrate itself could be a metal or metal alloy. In such cases, if the substrate itself can serve as the seed layer, the metalizing step would be optional or unnecessary.
  • Depending upon the particular implementation, and advantageously as described below, the metalizing operation can be performed across the entire substrate, limited to particular areas (for example, an area suitably sized relative to the area of a chip to which the package will ultimately be attached), or even more limited to the vicinity of defined connection points.
  • FIG. 2 illustrates, in simplified form, the portion of the substrate 100 after a seed layer 200 has been deposited by metalizing.
  • FIG. 3 illustrates, in simplified form, the portion of the substrate 100 of FIG. 2 in which a photoresist 300 has been applied and patterned to create openings 302, 304, 306, 308 extending down to, and exposing, parts of the seed layer 200.
  • Depending upon the particular implementation, the photoresist 300 can be flowable or solid. Conventional flowable photoresists used in semiconductor processing are suitable for use with the process. Suitable solid photoresist include those from the Riston.RTM. dry film photoresist line, specifically, the Riston.RTM. PlateMaster, EtchMaster and TentMaster lines of photoresist, all commercially available from E. I. du Pont de Nemours & Co.
  • As shown in FIG. 3, for purposes of example, the openings all fall within about a 140 μm long cross section of the substrate 100, with the three leftmost openings being about 10 μm wide and on a 20 μm pitch. Of course, with particular implementations, the openings can be any desired size, but the approach will be most advantageous for high density interconnects where the openings are 50 μm wide or less, in some cases, less than 10 μm wide and the openings are on a pitch of 50 μm or less, in some cases again, less than 10 μm.
  • Next, the substrate is inserted into a plating bath so that a plating metal 400 will build up on the parts of the seed layer 200 that were exposed through the patterned photoresist 300. This can occur via, for example, a conventional electro- or electroless plating process. Depending upon the particular application, the plating metal 400 can be allowed to build up to any height within the openings as desired.
  • FIG. 4 illustrates, in simplified form, the portion of the substrate 100 after plating is complete.
  • Once plating is complete, the photoresist 300 is removed as required for the particular photoresist 300 used.
  • FIG. 5 illustrates, in simplified form, the portion of the substrate 100 after removal of the photoresist 300. As shown, the plating metal 400 left behind after removal of the photoresist 300 results in a series of upstanding “pillars” of the plating metal 400 that have essentially coplanar upper surfaces 402 and are anchored at their bottoms to the seed layer 200. These pillars will form the interconnects of the ultimate package.
  • At this point, a package material 600 is applied to the substrate 100 to fill in the volume previously occupied by the photoresist 300 up to about the level of the upper surfaces 402. Ideally, the package material 600, when solidified, should be electrically non-conducting and relatively stable and/or inert. The package material 600 is then allowed to solidify by hardening or curing as appropriate.
  • Depending upon the particular implementation, this package material 600 can be a self hardening, curable or other material. Suitable examples of the package material 600 include moldable and flowable resins and plastics, such as for example, epoxies or liquid crystal polymers.
  • FIG. 6 illustrates, in simplified form, the portion of the substrate 100 after the package material 600 is fully hardened.
  • Finally, in the basic process, the substrate 100 and seed layer 200 are removed using a mechanical, chemical or chemical-mechanical process appropriate for the particular materials involved, leaving behind the fully formed package 700.
  • FIG. 7 illustrates, in simplified form, the package 700 after removal of the substrate 100 and seed layer 200 from the underside 702 of the package 700.
  • FIG. 8 illustrates, in simplified form, the underside 702 of a portion of the package 700 containing the cross section of FIG. 7, the cross section having been taken through the location indicated by the dashed line. As can now be seen, this approach allows for formation of densely packed interconnects. For example, in the left side of FIG. 8, there are eight interconnects 400 located within a square area that is about 50 μm on a side.
  • FIG. 9 through FIG. 16 collectively illustrate, in simplified form, a more sophisticated variant of the instant approach to formation of a plated pillar package. The approach is similar to that of FIG. 1 through FIG. 8, except for the metalization details. Thus, this variant will be described in abbreviated form with the understanding that, except as specifically noted, the details are the same as described in connection with FIG. 1 through FIG. 8.
  • Thus, as shown in FIG. 9, the process begins with a substrate 100.
  • Next, the process of metalizing the substrate 100 to form a seed layer 1000 for the subsequent plating operation occurs. However, unlike the approach of FIG. 1 through FIG. 8, the seed layer 1000 is applied after an intermediate patterning and lift-off has been performed to ensure that the seed layer 1000 is only located in areas where traces or contact points in the final package will be located. In addition, the seed layer 1000 is applied to be of sufficient thickness to allow the connection to ultimately carry the necessary current. FIG. 10 illustrates, in simplified form, the substrate 100 after the localized seed layer 1000 has been applied. Other metal or conductive material can connect the seed layers to allow current to flow to them if electroplating is subsequently used, however, the thickness of these connection regions need not be thick enough to carry the operating current of the final chips that are attached to the package.
  • Thereafter, as shown in FIG. 11 through FIG. 14, the approach is the same as described above. Specifically, a photoresist 300 is applied and patterned to expose the relevant portion of the seed layer 1000 (FIG. 1). Then, the plating occurs to build up the plating metal 400 (FIG. 12). Next, the photoresist 300 is removed, leaving behind the pillars of plating metal 400. (FIG. 13).
  • At this point it is worth noting that, in an alternative variant of this approach, immediately following the deposition of the seed layer 1000, but before removal of the photoresist used to localize the locations for seed layer placement, the substrate can undergo a preliminary plating operation. In other words, immediately prior to what is shown in FIG. 10. The purpose of this plating operation is to build up the seed to a thickness appropriate for handling the current that could be carried by the contact or trace in the ultimate package. In such a variant, the approach would otherwise be the same, except that the seed layer of FIG. 10 would already have a layer of plating metal over its extent and thus be thicker.
  • Next, the package material 600 is applied and solidified (FIG. 14), followed by removal of the substrate 100 (FIG. 15) from the underside 1402, and any connections between the seed portions (if a metal or other conductor were used as described above) leaving behind the fully formed package 1500.
  • FIG. 16 illustrates, in simplified form, the underside 1402 of a portion of the package 1500 containing the cross section of FIG. 15, the cross section having been taken through the location indicated by the dashed line. As can now be seen, in addition to allowing for formation of densely packed interconnects, this approach further allows for the package to contain connections 1602, 1604 between the interconnects or routing traces 1606, that can be connected to from external to the package 1500, for example, from another chip or another package.
  • Having described two basic variants, it will be appreciated that once such packages 700, 1500 are created, they can be treated as chips and thus, in addition to acting as a package for one or more chips, they can be stacked on and joined to each other or sandwiched between chips to allow for the formation of complex interconnects rivaling those created when back-end processing of a wafer to interconnect devices occurs.
  • Still further, with some variants, more complex interconnect arrangements can be created by simply using the final basic package in place of the substrate 100 and using the localized seed placement variant to apply a localized seed layer to a surface of the completed package. Then, the process described herein can be performed as described up to the point where the package material 600 is applied and solidified, at which point, the more complex package will be complete (i.e. there is no substrate to remove.)
  • FIG. 17 illustrates, in simplified form, a package 1700 variant created by using the variant of FIG. 10 through FIG. 15, and then using it as a substrate for the basic approach of FIG. 2 through FIG. 7.
  • FIG. 18 illustrates, in simplified form, a package 1800 variant created by using the variant of FIG. 10 through FIG. 15, to create a first package and then using that package as the substrate in the same variant approach.
  • Finally, it should now be understood that plated packages created as described herein can, in some cases, be ideally suited for use with the different intelligent chip packages, or as the back end wafers, described in the above-incorporated applications.
  • It should thus be understood that this description (including the figures) is only representative of some illustrative embodiments. For the convenience of the reader, the above description has focused on a representative sample of all possible embodiments, a sample that teaches the principles of the invention. The description has not attempted to exhaustively enumerate all possible variations. That alternate embodiments may not have been presented for a specific portion of the invention, or that further undescribed alternate embodiments may be available for a portion, is not to be considered a disclaimer of those alternate embodiments. One of ordinary skill will appreciate that many of those undescribed embodiments incorporate the same principles of the invention and others are equivalent.

Claims (25)

  1. 1. A device comprising:
    a first plurality of interconnect pillars;
    a first fill material surrounding the first plurality of interconnect pillars, wherein the first plurality of interconnect pillars extend from a first side of the first fill material to an opposite side of the first fill material;
    a first plurality of traces, each of the traces connected to at least two of the first plurality of interconnect pillars; and
    a first chip coupled to at least one of the first plurality of traces.
  2. 2. The device of claim 1, further comprising a second chip coupled to at least one of the first plurality of interconnect pillars.
  3. 3. The device of claim 1, further comprising:
    a second plurality of interconnect pillars; and
    a second fill material surrounding the second plurality of interconnect pillars, wherein the second plurality of interconnect pillars extend from a first side of the second fill material to an opposite side of the second fill material, and wherein at least one of the first plurality of interconnect pillars is coupled to at least one of the second plurality of interconnect pillars.
  4. 4. The device of claim 3, further comprising a second plurality of traces, wherein at least one of the first plurality of interconnect pillars and at least one of the second plurality of interconnect pillars are not aligned and are coupled to at least one of the second plurality of traces.
  5. 5. The device of claim 1, wherein at least one of the first plurality of interconnect pillars has a width of 50 μm or less.
  6. 6. The device of claim 5, wherein at least one of the first plurality of interconnect pillars has a pitch of 50 μm or less.
  7. 7. The device of claim 1, wherein at least one of the first plurality of interconnect pillars has a width of 20 μm or less.
  8. 8. The device of claim 7, wherein at least one of the first plurality of interconnect pillars has a pitch of 20 μm or less.
  9. 9. The device of claim 1, wherein a first set of the first plurality of interconnect pillars have different widths than a second set of the first plurality of interconnect pillars.
  10. 10. A device, comprising:
    a first plurality of interconnect pillars;
    a first fill material surrounding the first plurality of interconnect pillars, wherein the first plurality of interconnect pillars extend from a first side of the first fill material to an opposite side of the first fill material;
    a second plurality of interconnect pillars; and
    a second fill material surrounding the second plurality of interconnect pillars, wherein the second plurality of interconnect pillars extend from a first side of the second fill material to an opposite side of the second fill material, and wherein at least one of the first plurality of interconnect pillars is coupled to at least one of the second plurality of interconnect pillars.
  11. 11. The device of claim 10, further comprising a first plurality of traces, wherein at least one of the first plurality of interconnect pillars and at least one of the second plurality of interconnect pillars are not aligned and are coupled to at least one of the first plurality of traces.
  12. 12. The device of claim 11, further comprising a chip coupled to at least one of the first plurality of interconnect pillars.
  13. 13. The device of claim 11, further comprising a second plurality of traces, each of the traces electrically connected to at least one of the first plurality of interconnect pillars.
  14. 14. The device of claim 13, further comprising a chip coupled to at least one of the second plurality of traces.
  15. 15. The device of claim 14, further comprising a third plurality of traces electrically connected to at least one of the second plurality of interconnect pillars, wherein the third plurality of traces and the first plurality of traces are on opposite sides of the second fill material.
  16. 16. The device of claim 10, wherein at least one of the first or second pluralities of interconnect pillars have a width of 50 μm or less.
  17. 17. The device of claim 16, wherein at least one of the first or second pluralities of interconnect pillars have a pitch of 50 μm or less.
  18. 18. The device of claim 10, wherein, among the first plurality of interconnect pillars, a first set of interconnect pillars and a second set of interconnect pillars have different widths, and wherein, among the second plurality of interconnect pillars, a third set of interconnect pillars and a fourth set of interconnect pillars have different widths.
  19. 19. The device of claim 10, wherein the first and second plurality of interconnect pillars comprise a conductive material, and wherein the first and second fill materials comprise a dielectric.
  20. 20. A device, comprising:
    a first plurality of electrically conductive pillars;
    a first fill material surrounding the first plurality of electrically conductive pillars, wherein the first plurality of electrically conductive pillars extend from a first side of the first fill material to an opposite side of the first fill material;
    a first chip coupled to at least one of the first plurality of electrically conductive pillars;
    a second plurality of electrically conductive pillars; and
    a second fill material surrounding the second plurality of electrically conductive pillars, wherein the second plurality of electrically conductive pillars extend from a first side of the second fill material to an opposite side of the second fill material, and wherein the first chip is coupled to at least one of the second plurality of electrically conductive pillars.
  21. 21. The device of claim 20, further comprising a first plurality of traces, each of the traces connected to at least one of the first plurality of electrically conductive pillars and the first chip.
  22. 22. The device of claim 21, further comprising a second chip coupled to at least one of the first plurality of electrically conductive pillars and to at least one of the second plurality of electrically conductive pillars.
  23. 23. The device of claim 22, further comprising a second plurality of traces, each of the traces connected to at least one of the second plurality of electrically conductive pillars and the second chip.
  24. 24. The device of claim 20, wherein at least one of the first or second pluralities of electrically conductive pillars have a width of 50 μm or less.
  25. 25. The device of claim 24, wherein at least one of the first or second pluralities of electrically conductive pillars have a pitch of 50 μm or less.
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CN205016513U (en) * 2014-10-24 2016-02-03 胡迪群 Circuit is distribution layer structure again with encapsulation colloid supports
WO2018125066A1 (en) * 2016-12-28 2018-07-05 Intel Corporation Package substrate having copper alloy sputter seed layer and high density interconnects

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