JP2012119648A5 - - Google Patents
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- JP2012119648A5 JP2012119648A5 JP2011010288A JP2011010288A JP2012119648A5 JP 2012119648 A5 JP2012119648 A5 JP 2012119648A5 JP 2011010288 A JP2011010288 A JP 2011010288A JP 2011010288 A JP2011010288 A JP 2011010288A JP 2012119648 A5 JP2012119648 A5 JP 2012119648A5
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor die
- substrate
- pad
- power
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Claims (15)
- 半導体素子を作製する方法であって、
半導体ダイを提供することであって、該半導体ダイは、該半導体ダイの周辺領域中の2つ以下の周辺列に位置する信号パッドと、主に該信号パッドから該半導体ダイの内部領域中に位置する電力パッドおよび接地パッドとを有するダイパッドレイアウトを有する、ことと、
該半導体ダイの該信号パッド、電力パッド、および接地パッド上に複数のバンプを形成することと、
基板を提供することと、
該基板上に相互接続部位を有する複数の伝導性トレースを形成することであって、該半導体ダイの該信号パッド、電力パッド、および接地パッド上の該バンプは、該伝導性トレースの該相互接続部位よりも幅広い、ことと、
該半導体ダイを該基板に載置することであって、該半導体ダイの該信号パッド、電力パッド、および接地パッド上の該バンプは、該バンプが該相互接続部位の頂面および側面を覆うように、該基板上の該相互接続部位に接着される、ことと、
該半導体ダイと基板との間で該バンプの周囲に封入材を堆積させることと
を含む、方法。 - 前記バンプは、可融性部分と、非可融性部分とを含む、請求項1に記載の方法。
- 前記半導体ダイの縁とほぼ平行で前記信号パッドを配設することをさらに含む、請求項1に記載の方法。
- 前記電力パッドおよび接地パッドの10%未満は、前記周辺領域内に位置し、前記信号パッドの10%未満は、前記内部領域内に位置する、請求項1に記載の方法。
- 前記相互接続部位から離れた前記基板の領域上にマスキング層を形成することをさらに含む、請求項1に記載の方法。
- 半導体素子を作製する方法であって、
半導体ダイを提供することと、
基板を提供することと、
主に該基板の周辺領域中に位置する信号パッドと、主に該信号パッドから該基板の内部領域中に位置する電力部位および接地部位とを有するレイアウトで配設される、相互接続部位を有する複数の伝導性トレースを形成することであって、該相互接合部位が、該伝導性トレース上にあり、該基板上に配置されている、ことと、
該伝導性トレース上の該相互接続部位よりも幅広いバンプで該半導体ダイを該相互接続部位に接着することと、
該半導体ダイと基板との間に封入材を堆積させることと
を含む、半導体素子を作製する方法。 - 前記電力部位および接地部位の10%未満は、前記周辺領域内に位置する、請求項6に記載の方法。
- 前記信号パッドの10%未満は、前記内部領域内に位置する、請求項6に記載の方法。
- 周辺列で、または前記基板の縁とほぼ平行な周辺アレイで、前記信号パッドを配設することをさらに含む、請求項6に記載の方法。
- 前記基板の中心付近のアレイに前記電力部位および接地部位を配設することをさらに含む、請求項6に記載の方法。
- 半導体ダイであって、該半導体ダイは、主に該半導体ダイの周辺領域中に位置する信号パッドと、主に該信号パッドから該半導体ダイの内部領域中に位置する電力パッドおよび接地パッドとを有するダイパッドレイアウトを有する、半導体ダイと、
基板と、
該基板上に形成される、相互接続部位を有する複数の伝導性トレースと、
該半導体ダイと、複数の相互接続部位の頂面および側面とに接着された複数のバンプと、
該半導体ダイと基板との間に堆積させられた封入材と
を備える、半導体素子。 - 前記バンプは、可融性部分と、非可融性部分とを含む、請求項11に記載の半導体素子。
- 前記電力パッドおよび接地パッドの10%未満は、前記周辺領域内に位置する、請求項11に記載の半導体素子。
- 前記信号パッドの10%未満は、前記内部領域内に位置する、請求項11に記載の半導体素子。
- 前記信号パッドは、交互配設または直交配設で隣接する列に配設されている、請求項11に記載の半導体素子。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/959,709 | 2010-12-03 | ||
US12/959,709 US8853001B2 (en) | 2003-11-08 | 2010-12-03 | Semiconductor device and method of forming pad layout for flipchip semiconductor die |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012119648A JP2012119648A (ja) | 2012-06-21 |
JP2012119648A5 true JP2012119648A5 (ja) | 2014-01-16 |
Family
ID=43779400
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011010288A Pending JP2012119648A (ja) | 2010-12-03 | 2011-01-20 | フリップチップ半導体ダイのパッドレイアウトを形成する半導体素子および方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US8853001B2 (ja) |
JP (1) | JP2012119648A (ja) |
KR (1) | KR101798657B1 (ja) |
CN (1) | CN102487021B (ja) |
SG (2) | SG10201402301RA (ja) |
TW (2) | TWI528515B (ja) |
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