TWI456675B - 半導體元件、半導體封裝元件及其製作方法 - Google Patents
半導體元件、半導體封裝元件及其製作方法 Download PDFInfo
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- TWI456675B TWI456675B TW101103221A TW101103221A TWI456675B TW I456675 B TWI456675 B TW I456675B TW 101103221 A TW101103221 A TW 101103221A TW 101103221 A TW101103221 A TW 101103221A TW I456675 B TWI456675 B TW I456675B
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Claims (10)
- 一種半導體元件,包括:一積體電路;以及多個銅柱,耦接至該積體電路的一表面,其中該些銅柱在平行於該表面的一平面呈條狀,且至少50%的該些銅柱大體上呈向心排列。
- 如申請專利範圍第1項所述之半導體元件,其中所有耦接至該積體電路的該表面的該些銅柱大體上呈對稱排列、或向心排列。
- 如申請專利範圍第1項所述之半導體元件,其中所有位於該積體電路的該表面的一周邊區或一中心區中的該些銅柱大體上呈對稱排列、或向心排列。
- 如申請專利範圍第1項所述之半導體元件,其中位於該積體電路的該表面的一周邊區中且接近多個角落的該些銅柱之至少其中之一係呈對角線方向排列,多個接近該積體電路的該表面的一第一邊緣的銅柱係呈水平方向排列,且多個接近該積體電路的該表面的一第二邊緣的銅柱係呈垂直方向排列。
- 一種半導體封裝元件,包括如申請專利範圍第1項所述之半導體元件,且更包括一凸塊導線直連封裝耦接至該積體電路,該凸塊導線直連封裝包括一基板以及多個配置於該基板上的接合導線,其中位於該積體電路上的該些銅柱係耦接至該凸塊導線直連封裝的該些接合導線。
- 一種半導體元件的製作方法,包括: 提供一積體電路;於該積體電路的一表面上形成多個接墊;以及於該積體電路的該表面上的該些接墊上形成多個銅柱,其中該些銅柱呈條狀,且至少50%的該些銅柱大體上呈向心排列。
- 如申請專利範圍第6項所述之半導體元件的製作方法,其中形成該些銅柱的步驟包括:形成多個銅柱,其中至少一些的該些銅柱係於該積體電路的該表面上排列成一對稱圖案。
- 如申請專利範圍第6項所述之半導體元件的製作方法,其中形成該些銅柱的步驟包括:形成多個銅柱,該些銅柱排列成一大體上朝向該積體電路的該表面的一中心的向心圖案。
- 一種封裝半導體元件的方法,該半導體元件包括一積體電路,且多個接墊配置於該積體電路的一表面上,其中該方法包括:形成多個呈條狀的銅柱於該積體電路上的該些接墊上,以使至少50%的該些銅柱大體上呈向心排列;提供一凸塊導線直連封裝,該凸塊導線直連封裝包括多個位於其上接合導線;以及使位於該積體電路上的該些銅柱耦接至該凸塊導線直連封裝上的該些接合導線。
- 如申請專利範圍第9項所述之封裝半導體元件的方法,其中提供該凸塊導線直連封裝的步驟包括:提供一凸塊導線直連封裝,其中該些接合導線呈一 第一圖案;其中形成該些銅柱的步驟包括:形成多個銅柱,該些銅柱呈一第二圖案,其中該第二圖案大抵相同於該第一圖案。
Applications Claiming Priority (1)
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US13/228,757 US8598691B2 (en) | 2011-09-09 | 2011-09-09 | Semiconductor devices and methods of manufacturing and packaging thereof |
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TW201312670A TW201312670A (zh) | 2013-03-16 |
TWI456675B true TWI456675B (zh) | 2014-10-11 |
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US (1) | US8598691B2 (zh) |
KR (1) | KR101376257B1 (zh) |
CN (1) | CN103000597B (zh) |
DE (1) | DE102012100793B4 (zh) |
TW (1) | TWI456675B (zh) |
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US8624392B2 (en) | 2011-06-03 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical connection for chip scale packaging |
US8912668B2 (en) | 2012-03-01 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical connections for chip scale packaging |
US9548281B2 (en) | 2011-10-07 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical connection for chip scale packaging |
US9564412B2 (en) * | 2011-12-06 | 2017-02-07 | Intel Corporation | Shaped and oriented solder joints |
US9196573B2 (en) * | 2012-07-31 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump on pad (BOP) bonding structure |
US9673161B2 (en) | 2012-08-17 | 2017-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonded structures for package and substrate |
US8829673B2 (en) * | 2012-08-17 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonded structures for package and substrate |
CN104701290A (zh) * | 2013-12-06 | 2015-06-10 | 上海北京大学微电子研究院 | 一种多圈引线框qfn封装结构 |
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KR20160099440A (ko) * | 2015-02-12 | 2016-08-22 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 기판 분리 및 비도핑 채널을 갖는 집적 회로 구조물 |
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US10163838B2 (en) | 2016-10-14 | 2018-12-25 | Samsung Electronics Co., Ltd. | Semiconductor device |
US10573573B2 (en) | 2018-03-20 | 2020-02-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package and package-on-package structure having elliptical conductive columns |
US20200335466A1 (en) * | 2019-04-18 | 2020-10-22 | STMicroelectronics (Alps) SAS | Centripetal bumping layout and method |
FR3095298A1 (fr) * | 2019-12-09 | 2020-10-23 | Stmicroelectronics (Grenoble 2) Sas | Disposition centripète de bossages et procédé |
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CN212303653U (zh) * | 2020-03-26 | 2021-01-05 | 北京小米移动软件有限公司 | 芯片、电路板、电路板组件及电子设备 |
JP2022011066A (ja) * | 2020-06-29 | 2022-01-17 | 日本電気株式会社 | 量子デバイス |
US11705378B2 (en) * | 2020-07-20 | 2023-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of forming the same |
FR3113982A1 (fr) * | 2020-09-10 | 2022-03-11 | Commissariat à l'Energie Atomique et aux Energies Alternatives | procédé d’assemblage par hybridation de deux composants microélectroniques |
US11830800B2 (en) * | 2021-03-25 | 2023-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metallization structure and package structure |
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TW201312670A (zh) | 2013-03-16 |
DE102012100793A1 (de) | 2013-03-14 |
CN103000597A (zh) | 2013-03-27 |
KR101376257B1 (ko) | 2014-03-21 |
DE102012100793B4 (de) | 2022-02-10 |
US20130062741A1 (en) | 2013-03-14 |
US8598691B2 (en) | 2013-12-03 |
CN103000597B (zh) | 2015-11-25 |
KR20130028607A (ko) | 2013-03-19 |
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