JP2011524647A5 - - Google Patents

Download PDF

Info

Publication number
JP2011524647A5
JP2011524647A5 JP2011514614A JP2011514614A JP2011524647A5 JP 2011524647 A5 JP2011524647 A5 JP 2011524647A5 JP 2011514614 A JP2011514614 A JP 2011514614A JP 2011514614 A JP2011514614 A JP 2011514614A JP 2011524647 A5 JP2011524647 A5 JP 2011524647A5
Authority
JP
Japan
Prior art keywords
microelectronic device
microelectronic
conductive element
conductive
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011514614A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011524647A (ja
JP5639052B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/US2009/003643 external-priority patent/WO2009154761A1/en
Publication of JP2011524647A publication Critical patent/JP2011524647A/ja
Publication of JP2011524647A5 publication Critical patent/JP2011524647A5/ja
Application granted granted Critical
Publication of JP5639052B2 publication Critical patent/JP5639052B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2011514614A 2008-06-16 2009-06-15 ウェハレベルでの縁部の積重ね Active JP5639052B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US6195308P 2008-06-16 2008-06-16
US61/061,953 2008-06-16
PCT/US2009/003643 WO2009154761A1 (en) 2008-06-16 2009-06-15 Stacking of wafer-level chip scale packages having edge contacts

Publications (3)

Publication Number Publication Date
JP2011524647A JP2011524647A (ja) 2011-09-01
JP2011524647A5 true JP2011524647A5 (enExample) 2012-07-19
JP5639052B2 JP5639052B2 (ja) 2014-12-10

Family

ID=40974425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011514614A Active JP5639052B2 (ja) 2008-06-16 2009-06-15 ウェハレベルでの縁部の積重ね

Country Status (7)

Country Link
US (1) US8680662B2 (enExample)
EP (1) EP2308087B1 (enExample)
JP (1) JP5639052B2 (enExample)
KR (1) KR101655897B1 (enExample)
CN (1) CN102067310B (enExample)
TW (1) TWI425611B (enExample)
WO (1) WO2009154761A1 (enExample)

Families Citing this family (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US8723332B2 (en) 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
CN101809739B (zh) 2007-07-27 2014-08-20 泰塞拉公司 具有后应用的衬垫延长部分的重构晶片堆封装
CN101861646B (zh) 2007-08-03 2015-03-18 泰塞拉公司 利用再生晶圆的堆叠封装
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US8704379B2 (en) 2007-09-10 2014-04-22 Invensas Corporation Semiconductor die mount by conformal die coating
JP5763924B2 (ja) 2008-03-12 2015-08-12 インヴェンサス・コーポレーション ダイアセンブリを電気的に相互接続して取り付けられたサポート
US9153517B2 (en) * 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
US7863159B2 (en) 2008-06-19 2011-01-04 Vertical Circuits, Inc. Semiconductor die separation method
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
TWI446498B (zh) 2009-03-13 2014-07-21 泰斯拉公司 具有延伸穿越銲墊之通孔的堆疊微電子總成
CN102473697B (zh) 2009-06-26 2016-08-10 伊文萨思公司 曲折配置的堆叠裸片的电互连
US8242543B2 (en) * 2009-08-26 2012-08-14 Qualcomm Incorporated Semiconductor wafer-to-wafer bonding for dissimilar semiconductor dies and/or wafers
TWI520213B (zh) 2009-10-27 2016-02-01 英維瑟斯公司 加成法製程之選擇性晶粒電絕緣
TWI544604B (zh) 2009-11-04 2016-08-01 英維瑟斯公司 具有降低應力電互連的堆疊晶粒總成
US20110221053A1 (en) * 2010-03-11 2011-09-15 Qualcomm Incorporated Pre-processing to reduce wafer level warpage
US8796137B2 (en) * 2010-06-24 2014-08-05 Stats Chippac, Ltd. Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnect
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US11830845B2 (en) 2011-05-03 2023-11-28 Tessera Llc Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
CN103515257A (zh) * 2012-06-18 2014-01-15 智瑞达科技（苏州）有限公司 高密度半导体封装结构的封装方法
US9391008B2 (en) * 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US20140306331A1 (en) * 2013-04-11 2014-10-16 Infineon Technologies Austria Ag Chip and chip arrangement
US20140326856A1 (en) * 2013-05-06 2014-11-06 Omnivision Technologies, Inc. Integrated circuit stack with low profile contacts
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US11037904B2 (en) * 2015-11-24 2021-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Singulation and bonding methods and structures formed thereby
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9996725B2 (en) * 2016-11-03 2018-06-12 Optiz, Inc. Under screen sensor assembly
WO2018105201A1 (ja) * 2016-12-08 2018-06-14 株式会社村田製作所 複合部品及びその実装構造
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
DE102017109670B4 (de) * 2017-05-05 2019-12-24 Infineon Technologies Ag Herstellungsverfahren für ein Chippackage mit Seitenwandmetallisierung
KR102435517B1 (ko) * 2018-04-12 2022-08-22 에스케이하이닉스 주식회사 칩 스택 패키지
TWI762052B (zh) * 2019-03-26 2022-04-21 新加坡商Ｐｅｐ創新私人有限公司 封裝方法、面板組件以及晶圓封裝體
US11393791B2 (en) * 2020-01-28 2022-07-19 Micron Technology, Inc. Three-dimensional stacking semiconductor assemblies with near zero bond line thickness
JP2022049485A (ja) 2020-09-16 2022-03-29 キオクシア株式会社 半導体記憶装置

Family Cites Families (253)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074342A (en) 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
US4500905A (en) 1981-09-30 1985-02-19 Tokyo Shibaura Denki Kabushiki Kaisha Stacked semiconductor device with sloping sides
US4954875A (en) 1986-07-17 1990-09-04 Laser Dynamics, Inc. Semiconductor wafer array with electrically conductive compliant material
US4897708A (en) 1986-07-17 1990-01-30 Laser Dynamics, Inc. Semiconductor wafer array
US4765864A (en) 1987-07-15 1988-08-23 Sri International Etching method for producing an electrochemical cell in a crystalline substrate
US4842699A (en) 1988-05-10 1989-06-27 Avantek, Inc. Method of selective via-hole and heat sink plating using a metal mask
JP2876773B2 (ja) * 1990-10-22 1999-03-31 セイコーエプソン株式会社 プログラム命令語長可変型計算装置及びデータ処理装置
US5614766A (en) 1991-09-30 1997-03-25 Rohm Co., Ltd. Semiconductor device with stacked alternate-facing chips
WO1993023982A1 (en) 1992-05-11 1993-11-25 Nchip, Inc. Stacked devices for multichip modules
US5322816A (en) 1993-01-19 1994-06-21 Hughes Aircraft Company Method for forming deep conductive feedthroughs
US5426072A (en) 1993-01-21 1995-06-20 Hughes Aircraft Company Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
FR2704690B1 (fr) 1993-04-27 1995-06-23 Thomson Csf Procédé d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procédé et application à l'interconnexion de pastilles en trois dimensions.
US5343071A (en) 1993-04-28 1994-08-30 Raytheon Company Semiconductor structures having dual surface via holes
DE4314907C1 (de) 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
IL106892A0 (en) 1993-09-02 1993-12-28 Pierre Badehi Methods and apparatus for producing integrated circuit devices
US5412539A (en) 1993-10-18 1995-05-02 Hughes Aircraft Company Multichip module with a mandrel-produced interconnecting decal
US5424245A (en) 1994-01-04 1995-06-13 Motorola, Inc. Method of forming vias through two-sided substrate
IL108359A (en) 1994-01-17 2001-04-30 Shellcase Ltd Method and apparatus for producing integrated circuit devices
US5502333A (en) 1994-03-30 1996-03-26 International Business Machines Corporation Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
US5675180A (en) 1994-06-23 1997-10-07 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US6228686B1 (en) * 1995-09-18 2001-05-08 Tessera, Inc. Method of fabricating a microelectronic assembly using sheets with gaps to define lead regions
IL110261A0 (en) 1994-07-10 1994-10-21 Schellcase Ltd Packaged integrated circuit
US5880010A (en) 1994-07-12 1999-03-09 Sun Microsystems, Inc. Ultrathin electronics
MY114888A (en) 1994-08-22 2003-02-28 Ibm Method for forming a monolithic electronic module by stacking planar arrays of integrated circuit chips
DE4433845A1 (de) 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung
DE4433846C2 (de) 1994-09-22 1999-06-02 Fraunhofer Ges Forschung Verfahren zur Herstellung einer vertikalen integrierten Schaltungsstruktur
US5466634A (en) 1994-12-20 1995-11-14 International Business Machines Corporation Electronic modules with interconnected surface metallization layers and fabrication methods therefore
DE19516487C1 (de) 1995-05-05 1996-07-25 Fraunhofer Ges Forschung Verfahren zur vertikalen Integration mikroelektronischer Systeme
US5608264A (en) 1995-06-05 1997-03-04 Harris Corporation Surface mountable integrated circuit with conductive vias
US5682062A (en) 1995-06-05 1997-10-28 Harris Corporation System for interconnecting stacked integrated circuits
US5646067A (en) 1995-06-05 1997-07-08 Harris Corporation Method of bonding wafers having vias including conductive material
US5814889A (en) 1995-06-05 1998-09-29 Harris Corporation Intergrated circuit with coaxial isolation and method
US5618752A (en) 1995-06-05 1997-04-08 Harris Corporation Method of fabrication of surface mountable integrated circuits
US5604673A (en) 1995-06-07 1997-02-18 Hughes Electronics Low temperature co-fired ceramic substrates for power converters
US5648684A (en) 1995-07-26 1997-07-15 International Business Machines Corporation Endcap chip with conductive, monolithic L-connect for multichip stack
US6002167A (en) 1995-09-22 1999-12-14 Hitachi Cable, Ltd. Semiconductor device having lead on chip structure
JP2743904B2 (ja) 1996-02-16 1998-04-28 日本電気株式会社 半導体基板およびこれを用いた半導体装置の製造方法
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US5817530A (en) 1996-05-20 1998-10-06 Micron Technology, Inc. Use of conductive lines on the back side of wafers and dice for semiconductor interconnects
JP3620936B2 (ja) 1996-10-11 2005-02-16 浜松ホトニクス株式会社 裏面照射型受光デバイスおよびその製造方法
KR100214562B1 (ko) 1997-03-24 1999-08-02 구본준 적층 반도체 칩 패키지 및 그 제조 방법
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
DE69737262T2 (de) 1997-11-26 2007-11-08 Stmicroelectronics S.R.L., Agrate Brianza Herstellungsverfahren für einen Vorder-Hinterseiten-Durchkontakt in mikro-integrierten Schaltungen
US6620731B1 (en) 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US6624505B2 (en) 1998-02-06 2003-09-23 Shellcase, Ltd. Packaged integrated circuits and methods of producing thereof
IL123207A0 (en) 1998-02-06 1998-09-24 Shellcase Ltd Integrated circuit device
EP0985228A1 (en) 1998-03-02 2000-03-15 Koninklijke Philips Electronics N.V. Semiconductor device comprising a glass supporting body onto which a substrate with semiconductor elements and a metallization is attached by means of an adhesive
US6982475B1 (en) 1998-03-20 2006-01-03 Mcsp, Llc Hermetic wafer scale integrated circuit structure
KR100266693B1 (ko) 1998-05-30 2000-09-15 김영환 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법
US6492201B1 (en) 1998-07-10 2002-12-10 Tessera, Inc. Forming microelectronic connection components by electrophoretic deposition
US6103552A (en) 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
US6153929A (en) 1998-08-21 2000-11-28 Micron Technology, Inc. Low profile multi-IC package connector
US6261865B1 (en) 1998-10-06 2001-07-17 Micron Technology, Inc. Multi chip semiconductor package and method of construction
KR100304959B1 (ko) 1998-10-21 2001-09-24 김영환 칩 적층형 반도체 패키지 및 그 제조방법
SG78324A1 (en) 1998-12-17 2001-02-20 Eriston Technologies Pte Ltd Bumpless flip chip assembly with strips-in-via and plating
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
JP3228257B2 (ja) 1999-01-22 2001-11-12 日本電気株式会社 メモリパッケージ
US6130823A (en) 1999-02-01 2000-10-10 Raytheon E-Systems, Inc. Stackable ball grid array module and method
US6204562B1 (en) 1999-02-11 2001-03-20 United Microelectronics Corp. Wafer-level chip scale package
EP1041624A1 (en) 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Method of transferring ultra-thin substrates and application of the method to the manufacture of a multilayer thin film device
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US20030233704A1 (en) 2000-04-17 2003-12-25 Miguel Castellote Air massage system for bathtub
WO2000074134A1 (de) 1999-05-27 2000-12-07 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur vertikalen integration von elektrischen bauelementen mittels rückseitenkontaktierung
JP2001035995A (ja) 1999-07-22 2001-02-09 Seiko Epson Corp 半導体チップの貫通孔形成方法
JP4058607B2 (ja) * 1999-08-19 2008-03-12 セイコーエプソン株式会社 配線基板及びその製造方法、電子部品、回路基板並びに電子機器
US6277669B1 (en) 1999-09-15 2001-08-21 Industrial Technology Research Institute Wafer level packaging method and packages formed
JP2001156250A (ja) * 1999-11-24 2001-06-08 Seiko Epson Corp 半導体チップ、マルチチップパッケージ，および半導体装置と、並びに、それを用いた電子機器
IL133453A0 (en) 1999-12-10 2001-04-30 Shellcase Ltd Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US6376904B1 (en) 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
US6621155B1 (en) 1999-12-23 2003-09-16 Rambus Inc. Integrated circuit device having stacked dies and impedance balanced transmission lines
JP3879351B2 (ja) 2000-01-27 2007-02-14 セイコーエプソン株式会社 半導体チップの製造方法
JP3684978B2 (ja) 2000-02-03 2005-08-17 セイコーエプソン株式会社 半導体装置およびその製造方法ならびに電子機器
JP2001223323A (ja) 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
US6498387B1 (en) 2000-02-15 2002-12-24 Wen-Ken Yang Wafer level package and the process of the same
US6252305B1 (en) 2000-02-29 2001-06-26 Advanced Semiconductor Engineering, Inc. Multichip module having a stacked chip arrangement
US6344401B1 (en) 2000-03-09 2002-02-05 Atmel Corporation Method of forming a stacked-die integrated circuit chip package on a water level
US6396710B1 (en) 2000-05-12 2002-05-28 Raytheon Company High density interconnect module
JP3879816B2 (ja) 2000-06-02 2007-02-14 セイコーエプソン株式会社 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器
US6472247B1 (en) 2000-06-26 2002-10-29 Ricoh Company, Ltd. Solid-state imaging device and method of production of the same
JP3405456B2 (ja) 2000-09-11 2003-05-12 沖電気工業株式会社 半導体装置，半導体装置の製造方法，スタック型半導体装置及びスタック型半導体装置の製造方法
JP3433193B2 (ja) 2000-10-23 2003-08-04 松下電器産業株式会社 半導体チップおよびその製造方法
US6693358B2 (en) 2000-10-23 2004-02-17 Matsushita Electric Industrial Co., Ltd. Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
JP4505983B2 (ja) 2000-12-01 2010-07-21 日本電気株式会社 半導体装置
JP3420748B2 (ja) 2000-12-14 2003-06-30 松下電器産業株式会社 半導体装置及びその製造方法
JP2002184937A (ja) 2000-12-18 2002-06-28 Shinko Electric Ind Co Ltd 半導体装置の実装構造
US20020074637A1 (en) 2000-12-19 2002-06-20 Intel Corporation Stacked flip chip assemblies
JP2004534375A (ja) 2000-12-21 2004-11-11 シェルケース リミティド パケージ集積回路およびその製造方法
JP3915513B2 (ja) 2001-01-12 2007-05-16 コニカミノルタホールディングス株式会社 撮像装置
US20020098620A1 (en) 2001-01-24 2002-07-25 Yi-Chuan Ding Chip scale package and manufacturing method thereof
KR100352236B1 (ko) 2001-01-30 2002-09-12 삼성전자 주식회사 접지 금속층을 갖는 웨이퍼 레벨 패키지
KR100869013B1 (ko) 2001-02-08 2008-11-17 가부시키가이샤 히타치세이사쿠쇼 반도체 집적회로장치 및 그 제조방법
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US6498381B2 (en) 2001-02-22 2002-12-24 Tru-Si Technologies, Inc. Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
US7115986B2 (en) * 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US6528408B2 (en) 2001-05-21 2003-03-04 Micron Technology, Inc. Method for bumped die and wire bonded board-on-chip package
JP3651413B2 (ja) 2001-05-21 2005-05-25 日立電線株式会社 半導体装置用テープキャリア及びそれを用いた半導体装置、半導体装置用テープキャリアの製造方法及び半導体装置の製造方法
US6878608B2 (en) 2001-05-31 2005-04-12 International Business Machines Corporation Method of manufacture of silicon based package
US20030006494A1 (en) 2001-07-03 2003-01-09 Lee Sang Ho Thin profile stackable semiconductor package and method for manufacturing
JP3660918B2 (ja) * 2001-07-04 2005-06-15 松下電器産業株式会社 半導体装置及びその製造方法
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
US6727576B2 (en) 2001-10-31 2004-04-27 Infineon Technologies Ag Transfer wafer level packaging
US6611052B2 (en) 2001-11-16 2003-08-26 Micron Technology, Inc. Wafer level stackable semiconductor package
JP2003163324A (ja) 2001-11-27 2003-06-06 Nec Corp ユニット半導体装置及びその製造方法並びに３次元積層型半導体装置
US6607941B2 (en) 2002-01-11 2003-08-19 National Semiconductor Corporation Process and structure improvements to shellcase style packaging technology
US6743660B2 (en) 2002-01-12 2004-06-01 Taiwan Semiconductor Manufacturing Co., Ltd Method of making a wafer level chip scale package
JP4002106B2 (ja) 2002-01-16 2007-10-31 日立オムロンターミナルソリューションズ株式会社 自動取引装置
KR100486832B1 (ko) 2002-02-06 2005-05-03 삼성전자주식회사 반도체 칩과 적층 칩 패키지 및 그 제조 방법
US6806559B2 (en) 2002-04-22 2004-10-19 Irvine Sensors Corporation Method and apparatus for connecting vertically stacked integrated circuit chips
TWI232560B (en) 2002-04-23 2005-05-11 Sanyo Electric Co Semiconductor device and its manufacture
JP2003318178A (ja) 2002-04-24 2003-11-07 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US7340181B1 (en) * 2002-05-13 2008-03-04 National Semiconductor Corporation Electrical die contact structure and fabrication method
JP4215571B2 (ja) * 2002-06-18 2009-01-28 三洋電機株式会社 半導体装置の製造方法
TWI229435B (en) 2002-06-18 2005-03-11 Sanyo Electric Co Manufacture of semiconductor device
US6984545B2 (en) 2002-07-22 2006-01-10 Micron Technology, Inc. Methods of encapsulating selected locations of a semiconductor die assembly using a thick solder mask
JP2004063569A (ja) 2002-07-25 2004-02-26 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US6903442B2 (en) 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
US7329563B2 (en) 2002-09-03 2008-02-12 Industrial Technology Research Institute Method for fabrication of wafer level package incorporating dual compliant layers
SE0202681D0 (sv) 2002-09-10 2002-09-10 Frank Niklaus Hermetic sealing with combined adhesive bonding and sealing rings
US20040061213A1 (en) 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
JP4081666B2 (ja) 2002-09-24 2008-04-30 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US20040104454A1 (en) 2002-10-10 2004-06-03 Rohm Co., Ltd. Semiconductor device and method of producing the same
TWI227050B (en) 2002-10-11 2005-01-21 Sanyo Electric Co Semiconductor device and method for manufacturing the same
US6656827B1 (en) 2002-10-17 2003-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Electrical performance enhanced wafer level chip scale package with ground
US6869824B2 (en) 2002-10-29 2005-03-22 Ultratera Corporation Fabrication method of window-type ball grid array semiconductor package
TWI227550B (en) 2002-10-30 2005-02-01 Sanyo Electric Co Semiconductor device manufacturing method
JP2004153130A (ja) 2002-10-31 2004-05-27 Olympus Corp 半導体装置及びその製造方法
JP2004158536A (ja) 2002-11-05 2004-06-03 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
JP4056854B2 (ja) 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
DE10253163B4 (de) 2002-11-14 2015-07-23 Epcos Ag Bauelement mit hermetischer Verkapselung und Waferscale Verfahren zur Herstellung
US20050012225A1 (en) 2002-11-15 2005-01-20 Choi Seung-Yong Wafer-level chip scale package and method for fabricating and using the same
WO2004055891A1 (ja) 2002-12-17 2004-07-01 Fujitsu Limited 半導体装置および積層型半導体装置
JP3566957B2 (ja) 2002-12-24 2004-09-15 沖電気工業株式会社 半導体装置及びその製造方法
KR20040059742A (ko) 2002-12-30 2004-07-06 동부전자 주식회사 반도체용 멀티 칩 모듈의 패키징 방법
JP4145301B2 (ja) 2003-01-15 2008-09-03 富士通株式会社 半導体装置及び三次元実装半導体装置
JP3680839B2 (ja) 2003-03-18 2005-08-10 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
JP3972846B2 (ja) 2003-03-25 2007-09-05 セイコーエプソン株式会社 半導体装置の製造方法
EP1519410A1 (en) 2003-09-25 2005-03-30 Interuniversitair Microelektronica Centrum vzw ( IMEC) Method for producing electrical through hole interconnects and devices made thereof
US6897148B2 (en) 2003-04-09 2005-05-24 Tru-Si Technologies, Inc. Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby
JP4373695B2 (ja) 2003-04-16 2009-11-25 浜松ホトニクス株式会社 裏面照射型光検出装置の製造方法
SG119185A1 (en) 2003-05-06 2006-02-28 Micron Technology Inc Method for packaging circuits and packaged circuits
JP2004342862A (ja) * 2003-05-16 2004-12-02 Sony Corp 半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びにマルチチップモジュール
EP1482553A3 (en) 2003-05-26 2007-03-28 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
JP4130158B2 (ja) 2003-06-09 2008-08-06 三洋電機株式会社 半導体装置の製造方法、半導体装置
CN100468719C (zh) 2003-06-03 2009-03-11 卡西欧计算机株式会社 可叠置的半导体器件及其制造方法
US6972480B2 (en) 2003-06-16 2005-12-06 Shellcase Ltd. Methods and apparatus for packaging integrated circuit devices
JP3646720B2 (ja) 2003-06-19 2005-05-11 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
KR101086520B1 (ko) 2003-06-20 2011-11-23 엔엑스피 비 브이 전자 장치, 조립체 및 전자 장치 제조 방법
CN100587962C (zh) * 2003-07-03 2010-02-03 泰塞拉技术匈牙利公司 用于封装集成电路器件的方法和设备
JP2005045073A (ja) 2003-07-23 2005-02-17 Hamamatsu Photonics Kk 裏面入射型光検出素子
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7180149B2 (en) 2003-08-28 2007-02-20 Fujikura Ltd. Semiconductor package with through-hole
US7061085B2 (en) 2003-09-19 2006-06-13 Micron Technology, Inc. Semiconductor component and system having stiffener and circuit decal
KR100594229B1 (ko) 2003-09-19 2006-07-03 삼성전자주식회사 반도체 패키지 및 그 제조방법
JP2005101067A (ja) 2003-09-22 2005-04-14 Sharp Corp 基板の配線構造および配線形成方法
US7129576B2 (en) 2003-09-26 2006-10-31 Tessera, Inc. Structure and method of making capped chips including vertical interconnects having stud bumps engaged to surfaces of said caps
SG120123A1 (en) * 2003-09-30 2006-03-28 Micron Technology Inc Castellated chip-scale packages and methods for fabricating the same
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
US7060601B2 (en) 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US7049170B2 (en) 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US20050156330A1 (en) 2004-01-21 2005-07-21 Harris James M. Through-wafer contact to bonding pad
DE102004008135A1 (de) 2004-02-18 2005-09-22 Infineon Technologies Ag Halbleiterbauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben
US7160753B2 (en) 2004-03-16 2007-01-09 Voxtel, Inc. Silicon-on-insulator active pixel sensors
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
JP4285309B2 (ja) 2004-04-13 2009-06-24 パナソニック株式会社 電子回路モジュールの製造方法と多層電子回路モジュールおよびその製造方法
US7952189B2 (en) 2004-05-27 2011-05-31 Chang-Feng Wan Hermetic packaging and method of manufacture and use therefore
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
KR100587081B1 (ko) 2004-06-30 2006-06-08 주식회사 하이닉스반도체 개선된 열방출 특성을 갖는 반도체 패키지
JP4211696B2 (ja) 2004-06-30 2009-01-21 ソニー株式会社 固体撮像装置の製造方法
KR100605314B1 (ko) 2004-07-22 2006-07-28 삼성전자주식회사 재배선 보호 피막을 가지는 웨이퍼 레벨 패키지의 제조 방법
DE102004039906A1 (de) 2004-08-18 2005-08-18 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauelements sowie ein elektronisches Bauelement mit mindestens zwei integrierten Bausteinen
US20060043556A1 (en) 2004-08-25 2006-03-02 Chao-Yuan Su Stacked packaging methods and structures
US7378342B2 (en) 2004-08-27 2008-05-27 Micron Technology, Inc. Methods for forming vias varying lateral dimensions
US7129567B2 (en) 2004-08-31 2006-10-31 Micron Technology, Inc. Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
KR100604049B1 (ko) 2004-09-01 2006-07-24 동부일렉트로닉스 주식회사 반도체 칩 패키지 및 그 제조방법
JP2006073825A (ja) 2004-09-02 2006-03-16 Toshiba Corp 半導体装置及びその実装方法
CN100539135C (zh) 2004-09-08 2009-09-09 松下电器产业株式会社 立体电路装置、使用它的电子机器及其制造方法
TWI288448B (en) 2004-09-10 2007-10-11 Toshiba Corp Semiconductor device and method of manufacturing the same
JP4139803B2 (ja) 2004-09-28 2008-08-27 シャープ株式会社 半導体装置の製造方法
TWI273682B (en) 2004-10-08 2007-02-11 Epworks Co Ltd Method for manufacturing wafer level chip scale package using redistribution substrate
KR100855819B1 (ko) 2004-10-08 2008-09-01 삼성전기주식회사 금속 밀봉부재가 형성된 ｍｅｍｓ 패키지
JP4873517B2 (ja) 2004-10-28 2012-02-08 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
DE102004052921A1 (de) * 2004-10-29 2006-05-11 Infineon Technologies Ag Verfahren zur Herstellung von Halbleiterbauelementen mit externen Kontaktierungen
FR2879347A1 (fr) 2004-12-14 2006-06-16 Commissariat Energie Atomique Dispositif electronique a deux composants assembles et procede de fabrication d'un tel dispositif
US20060138626A1 (en) 2004-12-29 2006-06-29 Tessera, Inc. Microelectronic packages using a ceramic substrate having a window and a conductive surface region
KR20060087273A (ko) 2005-01-28 2006-08-02 삼성전기주식회사 반도체 패키지및 그 제조방법
US7675153B2 (en) 2005-02-02 2010-03-09 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof
US7538032B2 (en) 2005-06-23 2009-05-26 Teledyne Scientific & Imaging, Llc Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method
US7449779B2 (en) 2005-03-22 2008-11-11 Tessera, Inc. Wire bonded wafer level cavity package
US7326592B2 (en) 2005-04-04 2008-02-05 Infineon Technologies Ag Stacked die package
JP4237160B2 (ja) 2005-04-08 2009-03-11 エルピーダメモリ株式会社 積層型半導体装置
JP4308797B2 (ja) 2005-05-02 2009-08-05 株式会社アドバンストシステムズジャパン 半導体パッケージおよびソケット付き回路基板
US7208345B2 (en) 2005-05-11 2007-04-24 Infineon Technologies Ag Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device
JP2007019107A (ja) 2005-07-05 2007-01-25 Shinko Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
KR100629498B1 (ko) 2005-07-15 2006-09-28 삼성전자주식회사 마이크로 패키지, 멀티―스택 마이크로 패키지 및 이들의제조방법
JP4551321B2 (ja) 2005-07-21 2010-09-29 新光電気工業株式会社 電子部品実装構造及びその製造方法
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US7419853B2 (en) 2005-08-11 2008-09-02 Hymite A/S Method of fabrication for chip scale package for a micro component
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
US7485969B2 (en) 2005-09-01 2009-02-03 Micron Technology, Inc. Stacked microelectronic devices and methods for manufacturing microelectronic devices
US20070052050A1 (en) 2005-09-07 2007-03-08 Bart Dierickx Backside thinned image sensor with integrated lens stack
KR20070048952A (ko) 2005-11-07 2007-05-10 삼성전자주식회사 내부 접속 단자를 갖는 멀티 칩 패키지
US20070126085A1 (en) 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
JP4934053B2 (ja) 2005-12-09 2012-05-16 スパンション エルエルシー 半導体装置およびその製造方法
US7981726B2 (en) 2005-12-12 2011-07-19 Intel Corporation Copper plating connection for multi-die stack in substrate package
US7632708B2 (en) 2005-12-27 2009-12-15 Tessera, Inc. Microelectronic component with photo-imageable substrate
US20070158807A1 (en) * 2005-12-29 2007-07-12 Daoqiang Lu Edge interconnects for die stacking
US20070190747A1 (en) 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
US7741707B2 (en) 2006-02-27 2010-06-22 Stats Chippac Ltd. Stackable integrated circuit package system
US7510928B2 (en) 2006-05-05 2009-03-31 Tru-Si Technologies, Inc. Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques
US8102039B2 (en) 2006-08-11 2012-01-24 Sanyo Semiconductor Co., Ltd. Semiconductor device and manufacturing method thereof
US7888185B2 (en) 2006-08-17 2011-02-15 Micron Technology, Inc. Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device
US7531445B2 (en) 2006-09-26 2009-05-12 Hymite A/S Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US7829438B2 (en) * 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US7759166B2 (en) 2006-10-17 2010-07-20 Tessera, Inc. Microelectronic packages fabricated at the wafer level and methods therefor
US7935568B2 (en) 2006-10-31 2011-05-03 Tessera Technologies Ireland Limited Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
US7807508B2 (en) 2006-10-31 2010-10-05 Tessera Technologies Hungary Kft. Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
US7394152B2 (en) 2006-11-13 2008-07-01 China Wafer Level Csp Ltd. Wafer level chip size packaged chip device with an N-shape junction inside and method of fabricating the same
US7663213B2 (en) 2006-11-13 2010-02-16 China Wafer Level Csp Ltd. Wafer level chip size packaged chip device with a double-layer lead structure and method of fabricating the same
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US20080157327A1 (en) 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Package on package structure for semiconductor devices and method of the same
JP5584474B2 (ja) 2007-03-05 2014-09-03 インヴェンサス・コーポレイション 貫通ビアによって前面接点に接続された後面接点を有するチップ
US20080284041A1 (en) 2007-05-18 2008-11-20 Samsung Electronics Co., Ltd. Semiconductor package with through silicon via and related method of fabrication
KR100914977B1 (ko) 2007-06-18 2009-09-02 주식회사 하이닉스반도체 스택 패키지의 제조 방법
US20080315407A1 (en) 2007-06-20 2008-12-25 Vertical Circuits, Inc. Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication
US20110024890A1 (en) 2007-06-29 2011-02-03 Stats Chippac, Ltd. Stackable Package By Using Internal Stacking Modules
US8766910B2 (en) 2007-07-04 2014-07-01 Cypress Semiconductor Corporation Capacitive sensing control knob
JP2009032929A (ja) 2007-07-27 2009-02-12 Sanyo Electric Co Ltd 半導体装置及びその製造方法
CN101809739B (zh) 2007-07-27 2014-08-20 泰塞拉公司 具有后应用的衬垫延长部分的重构晶片堆封装
US8193615B2 (en) 2007-07-31 2012-06-05 DigitalOptics Corporation Europe Limited Semiconductor packaging process using through silicon vias
KR101387701B1 (ko) 2007-08-01 2014-04-23 삼성전자주식회사 반도체 패키지 및 이의 제조방법
CN101861646B (zh) 2007-08-03 2015-03-18 泰塞拉公司 利用再生晶圆的堆叠封装
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
WO2009023462A1 (en) 2007-08-10 2009-02-19 Spansion Llc Semiconductor device and method for manufacturing thereof
KR100905784B1 (ko) 2007-08-16 2009-07-02 주식회사 하이닉스반도체 반도체 패키지용 관통 전극 및 이를 갖는 반도체 패키지
KR20090047776A (ko) 2007-11-08 2009-05-13 삼성전자주식회사 반도체 소자 및 그 형성 방법
KR101465948B1 (ko) 2007-12-27 2014-12-10 삼성전자주식회사 웨이퍼 레벨 스택 패키지 및 웨이퍼 레벨 스택 패키지 제조방법
US8084854B2 (en) 2007-12-28 2011-12-27 Micron Technology, Inc. Pass-through 3D interconnect for microelectronic dies and associated systems and methods
US20090212381A1 (en) 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US20100053407A1 (en) 2008-02-26 2010-03-04 Tessera, Inc. Wafer level compliant packages for rear-face illuminated solid state image sensors
US7973416B2 (en) 2008-05-12 2011-07-05 Texas Instruments Incorporated Thru silicon enabled die stacking scheme
US7863721B2 (en) 2008-06-11 2011-01-04 Stats Chippac, Ltd. Method and apparatus for wafer level integration using tapered vias
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US20100065949A1 (en) 2008-09-17 2010-03-18 Andreas Thies Stacked Semiconductor Chips with Through Substrate Vias
KR100990943B1 (ko) 2008-11-07 2010-11-01 주식회사 하이닉스반도체 반도체 패키지
TWI446498B (zh) 2009-03-13 2014-07-21 泰斯拉公司 具有延伸穿越銲墊之通孔的堆疊微電子總成

Similar Documents

Publication Publication Date Title
JP2011524647A5 (enExample)
JP2013544445A5 (enExample)
TWI441297B (zh) 具有阻抗控制引線接合及參考引線接合之微電子總成
CN106098663B (zh) 基板结构
JP2014078558A5 (enExample)
JP2011210773A5 (enExample)
JP6314731B2 (ja) 半導体装置及び半導体装置の製造方法
JP2015523145A5 (enExample)
JP6726821B2 (ja) 半導体装置の製造方法
JP2011009514A5 (enExample)
JP2014127706A5 (ja) 半導体装置の製造方法
JP2012099352A5 (enExample)
CN215299222U (zh) 模块
TWI430717B (zh) 基板結構、半導體裝置陣列及其半導體裝置
JP6287789B2 (ja) パワーモジュール及びその製造方法
JP2013131592A5 (enExample)
CN102217059A (zh) 一种封装用绝缘环、绝缘环组合件和封装体
JP2014503992A5 (enExample)
JP2009191185A5 (enExample)
JP2017530556A5 (enExample)
CN104851861A (zh) 半导体组件及制造半导体组件的方法
CN101677488B (zh) 高导热基板结构及其制作方法
TWI504320B (zh) 線路結構及其製法
JP2017028155A5 (enExample)
JP2013051389A5 (enExample)