CN104851861A - 半导体组件及制造半导体组件的方法 - Google Patents

半导体组件及制造半导体组件的方法 Download PDF

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CN104851861A
CN104851861A CN201410759400.0A CN201410759400A CN104851861A CN 104851861 A CN104851861 A CN 104851861A CN 201410759400 A CN201410759400 A CN 201410759400A CN 104851861 A CN104851861 A CN 104851861A
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semiconductor chip
area
cream
pressure
sintering
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山寄优
钉宫哲也
广畑贤治
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Toshiba Corp
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Toshiba Corp
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Abstract

根据一个实施例，半导体组件包括电路板、半导体芯片和接合部件，所述接合部件通过烧结包含金属颗粒的膏形成在所述电路板和所述半导体芯片之间，以接合所述电路板和所述半导体芯片。所述接合部件包括紧接在所述半导体芯片之下的第一区域和邻近于所述第一区域的第二区域。所述第二区域具有等于或者低于所述第一区域的孔隙度。

Description

半导体组件及制造半导体组件的方法
相关申请的交叉引用
本申请基于2013年12月12日提交的日本专利申请No.2013-256839并且要求其优先权；通过引用将该日本专利申请的整个内容被并入于此。
技术领域
在此描述的实施例一般涉及半导体组件以及用于制造半导体组件的方法。
背景技术
对于高效率和高速度半导体功率器件，已经全球范围地开发了不同于现有技术的硅功率器件的SiC功率器件和GaN功率器件。这样的下一代功率器件的一个特性是高温操作。由于耐热性的限制，硅功率器件在150℃或者更低的温度下操作。然而，对于下一代功率器件，在200℃或者更高温度的高温操作是可能的。
因此，还需要与现有技术中相比更耐热的用于管芯安装的接合材料。已经开发了多种新的材料和新的接合方法，诸如耐热性以及高温下的可靠性优秀并具有与现有技术的不同的成分的焊料材料，以及在其中形成具有高熔点的金属间化合物层的接合方法。
最期望的接合方法包括使用金属颗粒烧结材料的绕结方法，通过对金属颗粒膏加热和加压来烧结所述材料，所述金属颗粒膏包含具有纳米或者微米量级的颗粒大小的金属颗粒以及有机保护膜等。
然而，对于现有的技术，出于例如压力没有适当地施加到金属颗粒膏这样的原因，接合可靠性会降低。
发明内容
实施例的一个目的是提供能够改善接合可靠性的半导体组件和用于制造半导体组件的方法。
根据一个实施例，一种半导体组件包括电路板、半导体芯片和接合部件，所述结合部分通过烧结包含金属颗粒的膏在所述电路板和所述半导体芯片之间形成，以接合所述电路板和所述半导体芯片。所述接合部件包括紧接在所述半导体芯片之下的第一区域和邻近于所述第一区域的第二区域。所述第二区域具有等于或者低于所述第一区域的孔隙度(porosity)。
根据上面描述的半导体组件，可以改善接合可靠性。
附图说明
图1是用于说明根据第一实施例的半导体组件的截面图；
图2是示出了用于形成半导体组件的压力施加的状态的图；
图3是示出了没有施加压力到半导体芯片附近的外围的状态的图；
图4是示出了半导体组件的示例的截面图；
图5是示出了在烧结过程中加压方法的示例的图；
图6是示出了根据实施例的在烧结过程中加压方法的示例的图；
图7是示出了在离半导体芯片的端部的距离和应力值之间的关系的图；
图8是示出了接近半导体芯片的金属颗粒烧结材料的形状的示例的图。
图9是用于说明根据第二实施例的半导体组件的截面图；
图10是示出了具有围绕半导体芯片的形状的辅助部件的示例的图；
图11是示出了将辅助部件沿着半导体芯片的边安装的示例的图。
图12是示出了将辅助部件沿着半导体芯片的边安装的示例的图。
图13是用于说明根据第三实施例的半导体组件的截面图；
图14是从上方观察的根据第三实施例的半导体组件的图；
图15是用于说明在线结构中引起断开的示例的图；以及
图16是用于说明根据第四实施例的半导体组件的截面图。
具体实施方式
下面将参考附图详细描述半导体组件和制造半导体组件的方法的优选实施例。
在下文中，将描述使用金属颗粒烧结材料的接合方法。使用具有纳米或者微米级颗粒大小的金属颗粒烧结材料，其允许利用比块状金属低得多的熔点进行烧结。烧结结构在导热性和导电性方面具有优秀的特性以及高熔点。金属颗粒的示例包括银颗粒和铜颗粒。
烧结之后的金属结构是纳米颗粒或者微米颗粒连接的多孔结构。该结构因此完全不同于通过现有技术的焊料接合或者类似方法得到的结构(其除了混入空隙等之外基本上是致密结构。因此，一个目标是通过金属颗粒烧结确保接合的高的接合可靠性。
在金属颗粒烧结的烧结期间的烧结温度以及施加的压力对接合可靠性的影响的研究中，已发现随着烧结温度越高由烧结得到的结构的拉伸强度越高，以及随着烧结期间施加的压力越高由烧结得到的结构的剪切强度越高。
不同于在接合过程中由于浸润性而引起的自对准效应的焊料接合，在通过金属颗粒烧结的接合中不能期望自对准效应。因此，为增加可靠性，将金属颗粒膏施加到比芯片大小大的区域。然而，通过施加压力使得烧结结构更致密来改善接合强度，仅仅在紧接在将被安装的芯片之下的区域中是有效的，没有对其施加压力述金属颗粒烧结结构保留在芯片的外围区域中。因此，这对于破裂模式不一定是有效的，在所述破裂模式中裂缝在芯片周围的低强度烧结结构处产生并从其生长。
如上所述，通过金属颗粒烧结的接合所具有的结构完全不同于焊料接合等的结构。因此，一个目的是确保通过金属颗粒烧结的接合的高的接合可靠性。
根据下面的实施例的半导体组件是具有通过使用金属颗粒烧结材料管芯安装在衬底(电路板)上的半导体芯片的半导体组件。实施例的半导体组件可以具有半导体封装等形式。
实施例的半导体组件每个都具有半导体芯片、延伸到半导体芯片附近的外围的金属颗粒烧结接合层、以及在其上安装半导体芯片的衬底。在实施例中，在加热和加压过程中，将压力充足地不仅施加到存在于半导体芯片之上的金属颗粒膏而且施加到存在于半导体芯片的外部区域中的金属颗粒膏。结果，形成这样的金属颗粒烧结接合层，其具有在半导体芯片附近的外围中的、平均孔隙度等于或者低于紧接在半导体芯片之下金属颗粒烧结结合层(第一区域)的平均孔隙度的第二区域。这改善了在衬底和半导体芯片之间的接合的可靠性。
第一实施例
图1是用于说明根据第一实施例的半导体组件的截面图。如图1示出的，半导体组件具有利用通过金属颗粒烧结的接合，管芯安装在衬底2上的半导体芯片1。通过金属颗粒烧结的接合得到的接合部件包括烧结结构3和烧结结构4。烧结结构3是具有由压力施加导致的低孔隙度的部分。烧结结构4是由于不充分的压力施加而具有比烧结结构3高的孔隙度的部分。
图2是示出了在半导体组件形成中压力施加的状态的图。如图2中所示出的，在本实施例中，将压力施加到半导体芯片1以及半导体芯片1附近的外围下的金属颗粒膏的区域202。因此，在区域202中和半导体芯片1之下形成致密的烧结结构3。
区域202是与紧接在半导体芯片1之下的区域201(第一区域)邻近的金属颗粒膏的区域(第二区域)。由于压力施加，区域202的孔隙度(平均孔隙度)等于或者低于紧接在半导体芯片1之下的区域201的孔隙度。另外，区域202包括厚度等于或者小于区域201的厚度(平均厚度)的区域。区域202可以具有任何可以改善接合可靠性的预定的宽度(离半导体芯片1的端部的距离)。如稍后将描述的，例如，区域202的大小可以在离半导体芯片1的端部的100μm内。
图3是示出了没有将压力施加到半导体芯片附近的外围的状态的图。图4是示出了在该情况下生产半导体组件的示例的截面图。在如图3中所示出地在烧结过程中，没有将压力施加到半导体芯片101附近的外围的情况下，图4示出了在烧结之后的截面图。在衬底102上形成的金属颗粒烧结结构包括致密的烧结结构103和在半导体芯片101附近的外围中的具有低强度的稀疏的结构104。
由于应力很可能集中在半导体芯片101的端部附近，在该区域中很可能引起裂缝。因此，在如图4生产的半导体组件中，可能在具有低强度的烧结结构104中引起裂缝并从那里生长。
相比之下，在本实施例中，通过将压力施加到外围，如图1中所示出的，半导体芯片1附近的外围中也形成了致密金属颗粒烧结结构。因此，能够改善半导体芯片1的端部附近(在所述端部附近产生裂缝的风险高)的强度，以及能够降低在接合部件处的风险。
图5是示出了在烧结过程中加压方法的示例的图。在烧结过程中，将金属颗粒膏5放置在衬底2上，以及将半导体芯片1放置在金属颗粒膏5上。之后通过压力加持具(pressure jig)8经由缓冲器部件6a从半导体芯片1上方施加压力。
在需要施加压力的通过金属颗粒烧结的接合中，如图5中所示出的，在压力加持具8和半导体芯片1的上表面之间通常设置软的缓冲器部件6a，以使在半导体芯片1的整个表面上施加的压力均匀。当施加压力时缓冲器部件6a极大地变形，但是在半导体芯片1的附近保留空间。结果，压力没有施加到半导体芯片1的外围区域，半导体芯片1附近的外围的金属颗粒烧结结构如图4中那样稀疏。
接下来，将描述如图2中所示出的将压力施加到外围的方法。图6是示出了根据本实施例在烧结过程中加压方法的示例的图。图6示出了其中设计缓冲器部件的形状的方法的示例。如图6中所示出的，在本实施例中，在缓冲器部件6a中设置了具有基本上和半导体芯片1一样大小的凹陷。这允许在半导体芯片1附近的外围之下的金属颗粒膏被加压。选择用于缓冲器部件6a的材料是不与金属颗粒烧结材料接合的弹性优秀的软材料，诸如橡胶或者石墨烯。
在半导体芯片1的外围中被加压的区域的大小对应于应力和应变所集中到的半导体芯片1的端部的范围。图7是示出了在离半导体芯片1的端部的距离与应力值(冯米塞斯应力(von Mises stress))之间的关系的示例的图。该应力值是在金属颗粒烧结结构中引起的应力的值。图7是通过仿真模拟的管芯安装结构的温度变化得到的图，其中横轴代表离半导体芯片1的端部的距离，纵轴代表应力值。该图示出了在半导体芯片1的端部处的应力是大的区域的范围是在100μm内。由于这个原因，压力施加有效的半导体芯片1的外围区域的大小可以确定为离半导体芯片1的端部100μm。
注意，100μm的值仅仅是示例，并且大小不限于此。可以根据用于金属颗粒等等的材料，使用任何适合于改善接合可靠性的值。例如，可以通过实验或者仿真得到应力值变为预定的阈值或者更低的距离(离半导体芯片1的端部的长度)，以及可以在所得到的离半导体芯片1的端部距离的区域中将压力施加到金属颗粒膏。
图8是示出了半导体芯片1附近的金属颗粒烧结材料的形状的示例的图。图8示出了这样的一个示例，其中半导体芯片1的端部附近的烧结结构3具有当压力被施加时由于缓冲器部件6b的泊松(Poisson)变形导致的圆角形状(fillet shape)。例如，通过适当地控制用于缓冲器部件6b的材料以及在烧结期间施加的压力，可以形成具有如图8中所示出的形状的烧结结构3。作为形成具有这样的形状的烧结结构3的结果，可以降低到半导体芯片1的端部的应力集中，以及可以进一步改善接合可靠性。
例如，如下生产本实施例的半导体组件。首先，将金属颗粒膏放置在衬底上。随后，将半导体芯片1放置在金属颗粒膏上。随后，从半导体芯片1上方对半导体芯片1施加压力，从金属颗粒膏的其中没有放置半导体芯片1的区域(半导体芯片1附近的外围)的上方对金属颗粒膏施加压力，以及使金属颗粒膏经受加压烧结。
第二实施例
在第一实施例中，通过设计缓冲器部件等的形状实现将压力施加到半导体芯片1附近的外围。替代地，可以通过在外围安装另一个部件(辅助部件)在外围下类似地形成致密金属颗粒烧结结构。
图9是用于说明根据第二实施例的半导体组件的截面图。图9示出了辅助部件9安装在半导体芯片1附近的外围上的情况的截面图。辅助部件9形成在与紧接在半导体芯片1之下的金属颗粒烧结接合层(第一区域)邻近的区域(第二区域)的面向半导体芯片1的表面上。即使在安装了辅助部件9时，也优选通过缓冲器部件施加压力以使得压力均匀。辅助部件9可以具有多种多样的形状。
图10是示出了具有围绕半导体芯片1的形状的辅助部件的示例的图。作为使用这样的辅助部件9的结果，可以改善在半导体芯片1的整个外围之上的接合可靠性。
图11是示出了将辅助部件分成沿着半导体芯片1的边安装的多个辅助部件的示例的图。作为如图11中所示，将辅助部件分成多个辅助部件9-2，以及将辅助部件9-2布置在接合部件10上的结果，可以降低由在安装的辅助部件9-2和衬底之间的热膨胀系数的差引起的负荷。此外，随着离半导体芯片1的中心的距离越大，当温度改变时由于热膨胀系数的差引起的负荷越大。因此，在半导体芯片1的角部附近，负荷达到最大值。因此，如图12中所示出的将L-形辅助部件9-3安装在半导体芯片1的其中负荷达到最大值的角部附近的方法也是有效的。
第三实施例
在第二实施例中，将辅助部件安装在半导体芯片1附近的外围上，以使外围之下的金属颗粒烧结结构更致密。在第三实施例中，说明了其中辅助部件被用于检测接合部件的失效的预征(predictor)。图13和14示出了辅助部件被用于检测失效预征的示例。图13是用于说明根据第三实施例的半导体组件的截面图。图14是从半导体芯片1的上方观察的根据第三实施例的半导体组件的图。
为检测断开信号，如图14中所示出的，在接合部件10中形成槽11以将接合部件10分成中心区域10a和外围区域10b。此外，如图13中所示出的，辅助部件9被用来形成针对检测半导体芯片1的外围中的断开的布线结构12(连接路径)。在这种情况下，导电部件被用于辅助部件9。
例如，设置在半导体组件的内部或者外部的测量单元(未示出)测量布线结构12的电学特性，以检测布线结构12中的连接断开。电学特性的示例包括电阻、电流和电压。
图15是用于说明在布线结构12中引起断开的示例的图。如果如图15中所示出的，在辅助部件9的下部中引起了裂缝13，以及在线结构12中发生断开，可以检测到断开信号，诸如电阻变化。因此，能够检测接合部件10的失效的预示因素。失效的预征的检测可以被用于早期的维护工作，其有利于改善使用半导体封装的系统的鲁棒性。
第四实施例
在第四实施例中，将描述用于在紧接在管芯安装在衬底上的接合部件之下的区域中形成凹陷的方法，作为用于使半导体芯片1附近的外围中的金属颗粒烧结结构更致密的另一个实施例。
图16是用于说明根据第四实施例的半导体组件的截面图。衬底2-4的凹陷至少具有比半导体芯片1大的形状。例如，本实施例的半导体组件如下生产。首先，用金属颗粒膏填充衬底的凹陷。随后，将半导体芯片1放置在金属颗粒膏的顶部上。随后，从半导体芯片1上方将压力施加到半导体芯片1以执行加压烧结。利用这样的方法，由于凹陷的受限制的壁，压力还可以被施加到半导体芯片1附近的外围中的金属颗粒烧结材料，这可以实现更致密的烧结结构。
如上所述，根据第一到第四实施例，可以在还将压力施加到存在于半导体芯片的外部的区域中的金属颗粒膏的情况下执行烧结。因此，可以改善半导体芯片的端部附近的强度，以及可以改善在衬底和半导体芯片之间的接合的可靠性。
虽然已经描述了某些实施例，但是这些实施例仅仅通过示例的方式被呈现，并且不意图限制本发明的范围。实际上，在此描述的新颖的实施例可以以多种其它形式具体实现；此外，可以进行在此描述的实施例的形式中的各种省略、置换和修改而不脱离本发明的精神。所附的权利要求和它们的等同物意图覆盖落入本发明的范围和精神内的这些形式或者修改。

Claims (8)

1.一种半导体组件，包含：
电路板；
半导体芯片；以及
接合部件，所述接合部件通过烧结包含金属颗粒的膏在所述电路板和所述半导体芯片之间形成，以接合所述电路板和所述半导体芯片，其中
所述接合部件包括紧接在所述半导体芯片之下的第一区域和邻近于所述第一区域的第二区域，并且
所述第二区域具有等于或者低于所述第一区域的孔隙度。
2.根据权利要求1所述的组件，其中所述第二区域包括厚度等于或者低于所述第一区域的平均厚度的区域。
3.根据权利要求1所述的组件，进一步包括在所述第二区域的面向所述半导体芯片的表面上形成的辅助部件。
4.根据权利要求3所述的组件，其中
所述辅助部件是导电的，以及
所述接合部件和所述辅助部件构成具有可测量的电气特性的连接路径。
5.根据权利要求1所述的组件，其中
所述电路板具有凹陷，以及
通过烧结填充所述凹陷的膏形成所述接合部件。
6.根据权利要求1所述的组件，其中所述第二区域具有100μm或者更小的宽度。
7.一种用于制造半导体组件的方法，包括：
将包含金属颗粒的膏放置在电路板上；
将半导体芯片放置在所述膏上；以及
从半导体芯片上方施加压力到半导体芯片，从没有放置所述半导体芯片的膏的区域的上方将压力施加到所述膏，并烧结所述膏。
8.根据权利要求7所述的方法，其中
施加压力到所述半导体芯片和所述膏包括：
将压力施加到所述半导体芯片和所述膏，使得第二区域具有等于或者低于第一区域的孔隙度，所述第一区域是紧接在所述半导体芯片之下的膏的区域，所述第二区域是邻近于所述第一区域的膏的区域。
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