JP7123688B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP7123688B2 JP7123688B2 JP2018147942A JP2018147942A JP7123688B2 JP 7123688 B2 JP7123688 B2 JP 7123688B2 JP 2018147942 A JP2018147942 A JP 2018147942A JP 2018147942 A JP2018147942 A JP 2018147942A JP 7123688 B2 JP7123688 B2 JP 7123688B2
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Description
[第1の実施の形態に係る半導体装置の構造]
まず、第1の実施の形態に係る半導体装置の構造について説明する。図1は、第1の実施の形態に係る半導体装置を例示する図であり、図1(a)は平面図、図1(b)は図1(a)のA-A線に沿う断面図である。
次に、第1の実施の形態に係る半導体装置の製造方法について説明する。図2~図4は、第1の実施の形態に係る半導体装置の製造工程を例示する図である。なお、図2及び図3において、(a)は平面図、(b)は(a)のA-A線に沿う断面図である。又、図4は、図1(b)に対応する断面を示している。
第2の実施の形態では、第1の実施の形態と同様の金属焼結材を有する半導体装置の他の例を示す。なお、第2の実施の形態において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第3の実施の形態では、第1の実施の形態と同様の金属焼結材を有する半導体装置の他の例を示す。なお、第3の実施の形態において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
10 絶縁基板
10a、10b、11a、30a 面
11、11A、11B、11C、12 配線層
13、13A、13B 金属焼結材
14、14A、14B 半導体チップ
21、31 金属線
22、23、32 外部接続端子
25 ベースプレート
26 樹脂ケース
30 ダイパッド
33 モールド樹脂
130 ペースト
130c 中央部
130p 周縁部
131、131A、131B、132、132A、132B 領域
132a 第1面
132b 第2面
140 チップ搭載予定領域
Claims (17)
- チップ搭載部と、
前記チップ搭載部に金属焼結材を介して接合された半導体チップと、を有し、
前記金属焼結材は、平面視で前記半導体チップと重複する第1領域と、平面視で前記半導体チップの周囲を囲む第2領域と、を含み、
前記第1領域の空隙率は1%以上15%未満であり、前記第2領域の空隙率は15%以上50%以下である半導体装置。 - 前記第2領域において、前記チップ搭載部と接する第1面と、前記第1面の反対面である第2面とは平行である請求項1に記載の半導体装置。
- 前記第2領域は、前記半導体チップの側面に接している請求項1又は2に記載の半導体装置。
- 前記第1領域の厚さは、前記第2領域の厚さより薄い請求項1乃至3の何れか一項に記載の半導体装置。
- 前記金属焼結材は、銀又は銅を含む請求項1乃至4の何れか一項に記載の半導体装置。
- 絶縁基板と、前記絶縁基板上に設けられた配線層と、を有し、
前記配線層は、前記チップ搭載部である請求項1乃至5の何れか一項に記載の半導体装置。 - ダイパッドが設けられたリードフレームを有し、
前記ダイパッドは、前記チップ搭載部である請求項1乃至5の何れか一項に記載の半導体装置。 - チップ搭載部のチップ搭載予定領域内、及び前記チップ搭載予定領域の周囲に金属焼結材のペーストを印刷し、乾燥させる工程と、
前記ペーストの周縁部を加圧する工程と、
前記チップ搭載予定領域内に位置する前記ペーストを、加熱雰囲気中で半導体チップを介して加圧し、前記チップ搭載予定領域内及び前記チップ搭載予定領域の周囲に位置する前記ペーストを焼結して金属焼結材を作製し、前記チップ搭載部に前記金属焼結材を介して前記半導体チップを接合する工程と、を有し、
前記金属焼結材は、平面視で前記半導体チップと重複する第1領域と、平面視で前記半導体チップの周囲に位置する第2領域と、を含み、
前記第1領域の空隙率は1%以上15%未満であり、前記第2領域の空隙率は15%以上50%以下である半導体装置の製造方法。 - 前記第2領域の空隙率は、前記ペーストを印刷する工程で印刷された前記ペーストの空隙率よりも低い請求項8に記載の半導体装置の製造方法。
- 前記第2領域は、前記ペーストを印刷する工程で印刷された前記ペーストの最厚部の厚さよりも薄く、
前記第1領域は、前記第2領域よりも薄い請求項8又は9に記載の半導体装置の製造方法。 - 前記第2領域において、前記チップ搭載部と接する第1面と、前記第1面の反対面である第2面とは平行である請求項8乃至10の何れか一項に記載の半導体装置の製造方法。
- 前記ペーストの周縁部を加圧する工程で加圧される領域は、平面視で、前記ペーストの前記チップ搭載予定領域の最外周よりも内側から、前記ペーストの最外周に至る額縁状の領域である請求項8乃至11の何れか一項に記載の半導体装置の製造方法。
- 前記ペーストの周縁部を加圧する工程では、前記ペーストの周縁部を加熱しながら加圧し、
前記ペーストの周縁部を加圧する工程の加熱温度は、前記半導体チップを接合する工程の加熱温度よりも低い請求項8乃至12の何れか一項に記載の半導体装置の製造方法。 - 前記半導体チップを接合する工程において、前記第2領域は、前記半導体チップの側面に接する請求項8乃至13の何れか一項に記載の半導体装置の製造方法。
- 前記ペーストは、銀又は銅を含む請求項8乃至14の何れか一項に記載の半導体装置の製造方法。
- 絶縁基板と、前記絶縁基板上に設けられた配線層と、を有し、
前記配線層は、前記チップ搭載部である請求項8乃至15の何れか一項に記載の半導体装置の製造方法。 - ダイパッドが設けられたリードフレームを有し、
前記ダイパッドは、前記チップ搭載部である請求項8乃至15の何れか一項に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2018147942A JP7123688B2 (ja) | 2018-08-06 | 2018-08-06 | 半導体装置及びその製造方法 |
US16/510,087 US11239196B2 (en) | 2018-08-06 | 2019-07-12 | Semiconductor device |
US17/645,815 US12009333B2 (en) | 2018-08-06 | 2021-12-23 | Semiconductor device |
Applications Claiming Priority (1)
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