TWI425611B - 微電子總成及製造一經堆疊微電子總成之方法 - Google Patents

微電子總成及製造一經堆疊微電子總成之方法 Download PDF

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TWI425611B
TWI425611B TW098120145A TW98120145A TWI425611B TW I425611 B TWI425611 B TW I425611B TW 098120145 A TW098120145 A TW 098120145A TW 98120145 A TW98120145 A TW 98120145A TW I425611 B TWI425611 B TW I425611B
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Taiwan
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microelectronic
microelectronic device
conductive
edge
conductive element
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TW098120145A
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English (en)
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TW201005918A (en
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Belgacem Haba
Ilyas Mohammed
Laura Mirkarimi
Moshe Kriman
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Tessera Inc
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Description

微電子總成及製造一經堆疊微電子總成之方法
本發明係關於經封裝微電子元件及其製造方法，且更特定而言係關於一可堆疊的經封裝微電子晶粒總成。
本申請案主張2008年6月16日申請之第61/061,953號美國臨時專利申請案之申請日期之權利，該申請案之揭示內容以引用之方式併入本文中。
微電子晶片通常係扁平體，其具有相對的一般係平面之前表面及後表面且具有在此等表面之間延伸之邊緣。晶片通常在前表面上具有電連接至晶片內之電路之觸點，有時亦稱為墊或接合墊。通常藉由用一合適材料包圍晶片以形成具有電連接至晶片觸點之端子之微電子封裝來封裝該等晶片。然後，可將該封裝連接至測試設備以確定該經封裝裝置是否符合一期望效能標準。測試之後，該封裝可藉由透過一合適連接方法(例如焊接)將該等封裝端子連接至一印刷電路板(PCB)上之匹配著陸點而連接至一較大電路，例如一電子產品(例如一電腦或一行動電話)中之一電路。
可在晶圓層級製造微電子封裝；亦即，構成封裝之外殼、終端及其他特徵在晶片或晶粒仍處於一晶圓形式時進行製造。在晶粒形成之後，晶圓經受若干個額外製程步驟以在晶圓上形成封裝結構，且然後切分晶圓以釋放經個別封裝之晶粒。晶圓層級處理可係一較佳製造方法，此乃因其可提供一節省成本之優勢，而且可使每一晶粒封裝之佔用面積與晶粒本身之大小相同或幾乎相同，從而導致非常有效地利用經封裝晶粒附接至其之印刷電路板上之區域。以此方式封裝之一晶粒通常稱為晶圓層級晶片尺寸封裝或晶圓層級晶片大小封裝(WLCSP)。
為節省一經封裝晶粒安裝至其之基板上之額外空間，可藉由垂直堆疊晶片而將多個晶片組合於一單一封裝中。堆疊中之每一晶粒通常必須向該堆疊中之一個或多個其他晶粒或者向其上安裝有該堆疊之基板或者向兩者提供一電連接機構。此允許經垂直堆疊之多個晶粒封裝佔據一基板上小於該封裝中之所有晶片加在一起所佔據之總表面區域的一表面區域。一由於通常當使用一晶粒堆疊時比當封裝一單一晶粒時存在更多電連接，因此堆疊之各個晶粒之間的電連接必須係極其強大及可靠。
一種微電子總成(300)可包含一第一微電子裝置(200)及一第二微電子裝置(200)。每一微電子裝置皆具有包含至少一個半導體晶粒(104)之一晶粒結構且該等微電子裝置中之每一者皆具有一第一表面(201)、遙對該第一表面之一第二表面(203)、及以非直角之一角度遠離該第一及該第二表面(201、203)延伸之至少一個邊緣表面(134)。至少一個導電元件(其可包含部分110、124、122、126)沿該第一表面延伸至該等邊緣表面之至少一者上及至該第二表面(203)上。可將該第一微電子裝置之至少一個導電元件導電地接合至該第二微電子裝置之至少一個導電元件以在其之間提供一導電路徑。
根據一個實施例，每一微電子裝置之導電元件可包含藉由鍍敷至第一及第二表面中之一者上而形成之第一元件，及藉由鍍敷至第一及第二表面中之另一者上及至少一個邊緣表面上而形成之第二元件。在一個實施例中，可將第二元件鍍敷至第一元件之部分上。舉例而言，第二元件沿第一元件之第二元件鍍敷於其上部分延伸。
第二元件可沿第一元件之邊緣延伸以在此等邊緣處與第一元件導電地結合。
舉例而言，可藉由使用一可熔金屬或使用導電膏來接合第一及第二微電子裝置之導電元件。在一個實施例中，第一微電子裝置之第一及第二表面中之一者可面對第二微電子裝置之第一及第二表面中之一者且將曝露在面對表面處之導電元件之部分接合在一起。舉例而言，導電元件可包含曝露在每一微電子裝置之第一或第二表面中之至少一者處之導電墊且將該等導電墊接合在一起。
導電元件可包含迹線及導電墊，其中至少一個導電墊經設置距該至少一個邊緣表面達一間隔距離。在一特定實施例中，每一微電子裝置之一導電元件包含接近至少一個邊緣表面或可延伸至該至少一個邊緣表面之一導電墊。
在一特定實施例中，該等微電子裝置中之一者或多者可包含複數個晶粒。在此情形中，包含於至少一個微電子裝置中之半導體晶粒中之至少兩者之接合墊-承載表面可面向相同的方向或其可面向不同的方向。
可以相對於第一及第二表面中之至少一者呈介於50度與89度之間的一角度設置至少一個導電元件沿其延伸之至少一個邊緣表面。
在微電子總成中，可以一垂直方向堆疊第一及第二微電子裝置，且第一及第二微電子裝置之至少一個邊緣表面可彼此偏移。
第一及第二微電子裝置之第一表面可在橫向方向上延伸且在橫向方向上具有第一尺寸。在一個實施例中，第一及第二微電子裝置之第一表面之橫向尺寸可係不同。
在一個實施例中，提供一種微電子總成，該微電子總成包含第一微電子裝置及第二微電子裝置。該等微電子裝置中之每一者皆可包含一晶粒結構，該晶粒結構具有至少一個半導體晶粒。該等微電子裝置中之每一者可具有一第一表面、遙對該第一表面之一第二表面、及遠離該第一表面延伸之至少一個邊緣表面。一導電元件可沿該第一表面延伸且至該等邊緣表面中之至少一者上。可將第一微電子裝置之至少一個導電元件導電地接合至第二微電子裝置之至少一個導電元件以在其之間提供一導電路徑。
在一個實施例中，該至少一個邊緣表面以非直角之一角度遠離第一及第二表面延伸。可導電地接合導電元件之曝露在至少一個邊緣表面處之邊緣部分以提供導電路徑。可使用一可熔金屬或可使用導電膏來接合此等邊緣部分。
根據一個實施例提供一種製造一經堆疊微電子總成之方 法。在此實施例中，可配置一第一微電子裝置之一主表面以面對一第二微電子裝置之一主表面。可導電地接合曝露在該第一微電子裝置之該主表面處之一導電元件與曝露在該第二微電子裝置之該主表面處之一導電元件以在其之間提供一導電路徑。每一微電子裝置皆可包含包含至少一個半導體晶粒之一晶粒結構，且該等微電子裝置中之每一者皆可具有一第一主表面、遙對該第一表面之一第二主表面、至少一個邊緣表面及至少一個導電元件，該至少一個導電元件沿該第一表面延伸至該等邊緣表面中之至少一者上及至該第二主表面上。
根據一個實施例，可製造一經堆疊微電子總成。可形成包含與一第二微電子裝置堆疊之一第一微電子裝置之一堆疊。該等微電子裝置中之每一者皆可包含一晶粒結構，該晶粒結構包含至少一個半導體晶粒。該等微電子裝置中之每一者皆可具有一第一表面、遙對該第一表面之一第二表面及遠離該第一表面延伸之至少一個邊緣表面。至少一個導電元件可沿該第一表面延伸且至該等邊緣表面中之至少一者上。可導電地接合曝露在該等邊緣表面處之導電元件之部分以在其之間提供一導電路徑。
在此實施例中，可將一第一微電子裝置設置於第二微電子裝置上方，且可藉由加熱接近曝露在該第一微電子裝置之至少一個邊緣表面處之導電元件之一可熔金屬來執行該接合步驟。以此方式，該可熔金屬可流動至曝露在該第二微電子裝置之至少一個邊緣表面處之導電元件上。在此實施例中，該可熔金屬可橋接該第一微電子裝置及該第二微電子裝置之導電元件之間的一間隙。
在此實施例中，可將第一微電子裝置設置於第二微電子裝置上方，且可藉由將一可流動導電材料分配至曝露在該第一微電子裝置之至少一個邊緣表面處之導電元件上來執行該接合步驟。然後，該導電材料可流動至曝露在該第二微電子裝置之至少一個邊緣表面處之導電元件上。
如在本揭示內容中所使用，一導電結構「曝露在」一介電結構之一表面處之一陳述指示該導電結構可用於接觸一理論點，該理論點沿一垂直於該介電結構之該表面之方向自該介電結構之外側朝向該介電結構之該表面移動。因此，曝露在一介電結構之一表面處之一端子或其他導電結構可自此表面伸出；可與此表面齊平；或可相對於此表面凹進且透過電介質中之一孔或凹坑曝露。
圖1A顯示一含有若干個微電子晶片之晶圓100之一透視圖。晶圓基板102通常係一半導體材料(例如矽)但可由其他材料製成或係某一類型之一複合物。將該晶圓劃分為包括一微電子晶片之工作部分之一部分或全部之個別晶粒104；在額外處理之後該等晶粒以虛線103彼此分離開。每一晶片可具有一個或多個功能且使用為熟悉半導體處理技術者熟知之技術形成於基板表面上或基板表面下。此等實例並非意欲限定-經處理晶圓100可表示任何數量類型之裝置，包含記憶體、處理器、影像感測器或其他可能裝置。接合墊106電連接至基板上或基板中之電路。圖1B顯示一晶圓(例如圖1A中所圖解說明之晶圓100)之一部分之一剖視圖。為清晰起見，將接合墊106曝露在基板102之一「前」表面或觸點承載表面101處。接合墊106可突出高於表面101，可與該表面齊平或可相對於該表面凹進。虛線103指示每一晶粒之間的切分路線。儘管本文中所述之晶圓可係一其中形成有工作部分之半導體材料，但在其他情形下該晶圓可係一重新組成之晶圓，其中該晶圓由若干個經放置以形成個別晶粒且由一黏合劑(例如，一環氧樹脂)固持在一起之組件形成。另一選擇係，替代一晶圓100，該結構可係在虛線103處所顯示之晶粒之邊緣處連接在一起之複數個晶粒，該結構在形狀上可係矩形，例如一面板。晶粒之邊緣可在虛線處會合且該半導體材料可係一連續未切割結構，或晶粒之邊緣可彼此間隔開且藉助一黏合劑結合成一重新組成的結構。
圖1C-1I顯示用於根據一個實施例處理晶圓之步驟。注意，可按所述次序，或，另一選擇係，按一不同次序執行所圖解說明之步驟。在某些實施方案中，所述步驟中之兩者或更多者可組合為一單一步驟。在其他實施方案中，一所述步驟可自製程中完全排除。在又其他變體中，可需要額外處理步驟。
圖1C係晶圓100之一單一晶粒108之一透視圖，該晶粒108具有一接觸接合墊之第一金屬化層110。可以某一方式(例如沈積或鍍敷)將一金屬膜沈積在晶圓之一表面101上，且然後可圖案化該膜以形成該金屬化層。在一特定實施例中，可在該表面上形成一晶種層，然後進行圖案化且隨後進行鍍敷以形成該金屬化層。該金屬化層之一部分經組態以形成將用來連接所堆疊組件之連接墊112。可將該金屬化層組態為一重分佈層。額外地，金屬化層之部分作為導電(例如)金屬迹線自接合墊106延伸至晶粒之邊緣。圖1D係一晶圓(例如圖1A中所顯示之晶圓100(但添加有金屬化層110))之一剖視圖。為簡明起見，此圖僅顯示與每一晶粒上之每一組接合墊106接觸之一個連接墊區域112。注意，端視所需佈置一特定剖視圖可包含一個或多個單獨連接區域。
圖1E顯示處理晶圓中之下一個步驟。在圖1E中，翻轉圖1D中所示之總成以使得金屬化層110面向下且附接至一單獨臨時載體基板114。使用一黏合劑層116將臨時基板114固持至主要基板102。此後，可使用例如研磨或拋光之技術使主要基板102薄化至一所需厚度，其結果顯示為在圖1F中之結構117。
在圖1G中顯示處理晶圓中之一後續步驟。在圖1G中，在基板102中切割或蝕刻一通道118以敞開一孔以曝露第一金屬化層110之一部分。在一個實施例中，此蝕刻可藉由一製程執行，該製程經控制以停止在半導體基板與金屬化層之間的一中間層上，且然後繼續移除該中間層之一部分以曝露金屬化層110。該中間層可係一介電層。通道118可係用來曝露連接至一個或多個晶粒之複數個接合墊之金屬化層部分之渠溝。圖1H顯示在基板102之表面上形成一介電層120之步驟。除其他目的之外，該介電層用來保護基板102之最新經曝露之表面。該介電層使基板102與隨後形成之導電結構絕緣。通道118之底部係藉由一鈍化層之一經圖案化沈積而變得清晰可見，或係留下來覆蓋可能在一進一步步驟中被曝露之第一金屬化層之金屬迹線之材料。在任一情形下，圖1H之結構經形成曝露該第一金屬化層之一部分。
圖1I圖解說明形成沿基板102之後邊緣表面134及後表面132延伸之一第二金屬化層122之步驟。同樣，虛線顯示晶粒104可彼此分離開之位置。與第一金屬化層相似，第二金屬化層122可包含連接墊126及其他迹線。亦如圖1C中所示，連接墊126可距晶粒104之邊緣表面達一間隔距離107。亦即，連接墊本身沒有達到邊緣表面。需要特別注意的係導電元件124，其沿晶粒結構之邊緣延伸，使第一金屬化層及第二金屬化層之部分彼此電連接。在一個實施例中，導電元件124形成為第二金屬化層122之一部分且與第二金屬化層之連接墊126及相關聯迹線同時形成。另一選擇係，金屬化層122及導電元件124可在單獨步驟中形成。在形成導電元件及金屬化層之後，可將基板切成複數個如下文所述且相對於圖2A-2D所圖解說明之個別晶粒結構200。在圖2E中可看到一概括上述用以形成裝置200之步驟之流程。
儘管第二金屬化層之連接墊之大小、形狀及位置可與第一金屬化層110之連接墊之大小、形狀及位置相同或類似，但其他組態亦係可能的。各種層上之連接墊之對準可促進後來堆疊個別晶粒結構以形成一經堆疊微電子總成，舉例而言(例如)下文參照圖3所述。
圖2A係顯示一微電子裝置200在與鄰近元件分離開之後其一最終結構之一個實施例之一截面圖。圖2D係朝向該裝置之與表面201(接合墊106最初曝露在其上)相對之一表面203看去之一對應透視圖。圖2B圖解說明一導電元件124與第一金屬化層110之間的一實例連接之一詳細視圖。圖2B顯示若如先前針對實施例所述已完成該製程該等層之間的結合之結構。在美國專利6,972,480及7,192,796中闡述了用於形成類似金屬化層及該等金屬化層之間的結合之製程，其揭示內容以引用的方式併入本文中。在此實例中，導電元件124沿第一金屬化層沿表面201水平延伸之方向延伸。可將導電元件鍍敷至金屬化層上。端視如何執行單一化切割或其他因素，導電元件之延伸超出邊緣表面134之部分可在長度上變化。在一變體中，導電元件124'與金屬化層110'之間的結合可係如圖2C中所示，其中導電元件124'沿金屬化層110'之一邊緣208延伸，邊緣208沿層110'之一厚度214之一方向遠離表面201延伸。在美國專利6,646,289及6,777,767中闡述用於形成具有導電元件之間的類似結合之類似結構之製程，其揭示內容以引用的方式併入本文中。若將通道118蝕刻得較深且形成完全穿過第一金屬化層的其相交之部分之一間隙，則可產生此結構。在一個實施例中，可堆疊並連接類似於圖2A中所示之微電子裝置之微電子裝置以形成一經堆疊晶粒裝置。此之一實例可在圖3中看到。在此實例中，一晶粒堆疊總成300由四個大致相同之微電子裝置200組成。在堆疊中之各種裝置200可取自一單一晶圓，或其可來自不同晶圓。為改良可靠性及良率，在堆疊之前可測試每一晶粒裝置以在組裝前確保其功能完全。藉由使用已知良好裝置來構成堆疊，可減輕晶粒堆疊之複合良率問題之問題。如所述，可認知此堆疊方法為一晶粒層級製程，其中在晶粒自晶圓分離之後將其堆疊。
在一個實施例中，晶粒堆疊300在功能上係完全的，但可需要額外步驟以將其封裝為其最終形式。任何額外封裝步驟皆涉及彼等熟悉此項技術者所熟知之技術。
在一替代實施例中，可在晶圓層級進行結合。在將晶圓結合在一起成為一堆疊之後，可然後分離所完成之晶粒堆疊。
可以各種方式達成將一個晶粒實際結合至下一層。圖4A及圖4B圖解說明兩種實例性方法。在圖4A中，其顯示一與在圖2A中所圖解說明之彼等微電子裝置相似之一微電子裝置。在圖4B中，已將一導電接合材料層412(例如，其可係一可熔冶金結合金屬)放置在上部連接墊402上。可以一不同方式鍍敷或沈積可係焊料、錫、銦之結合金屬、此金屬之一低共熔物或合金或其他此金屬組合。如所顯示，可將結合金屬僅施加至曝露在後表面403處之連接墊402，但可以想像該製程可將金屬置於經曝露金屬表面之一者或多者上，包含側面導電元件或晶粒表面處之其他墊。在任一情形下，然後對準並堆疊具有結合金屬之晶粒。然後可加熱該堆疊以完成面與面結合。另一選擇係，可將一導電膏(例如，經銀填充之膏、金膏、銲膏，等等)用作導電接合材料以在該堆疊中之微電子裝置之導電元件之間形成一導電路徑。如在圖3中所圖解說明，某些微電子裝置之前表面201面對其他微電子裝置之後表面203。某些微電子裝置200之前表面201處之導電元件導電地接合至其他微電子裝置200之後表面203處之導電元件。在一特定實施例中，兩個微電子裝置可經配置以使得其前表面401(圖4A)彼此面對。然後，可將曝露在一微電子裝置400之一前表面401處之連接墊與曝露在另一微電子裝置之一前表面401處之連接墊結合。在另一實施例中，兩個微電子裝置之後表面可彼此面對且此等後表面上之接合墊可藉由上述方法結合。在一特定實施例中，可在微電子裝置200仍以晶圓形式附胺時在彼此面對之表面處進行導電元件之接合。
在另一晶粒堆疊實施例中，晶粒堆疊可由具有不同功能性之異類晶粒組成。圖5A顯示此一晶粒堆疊結構500。晶粒堆疊結構500類似於圖3中之晶粒堆疊結構；然而，堆疊中之個別裝置係不同的。在此實例中，在堆疊中之頂部兩個晶粒502係相同，但底部兩個晶粒(504及506)係不同。舉例而言，晶粒502可係一記憶體元件，晶粒504可係一記憶體控制器，且晶粒506可係一處理單元。在此堆疊組態中，個別晶粒之橫向大小係大致相同，且各種晶粒重疊之間的連接墊基本係相同位置。儘管可在一晶粒層級組裝晶粒堆疊500，但在替代實施例中，亦可在晶圓層級組裝晶粒堆疊500，其中很少浪費任一給定晶圓上之晶圓區域。不必限制晶粒之大小。實際上，圖5B顯示一其中晶粒堆疊結構510由功能及大小兩者皆異同之晶粒組成之實施例。在一個實施例中，對堆疊晶粒之唯一限制係毗鄰面應在相同位置中具有連接墊。在圖5B中所示之實例中，晶粒514在頂部及底部表面兩者上具有彼此不匹配之連接墊，但其經組態以分別匹配晶粒512及516上之彼等連接墊。
在一個實施例中，將一微電子裝置之連接墊定位在一晶片之接合墊處或其附近。對於某些組態，此可提供足夠可用之金屬表面區域以與一晶粒堆疊中之一第二微電子裝置形成一連接。圖6A顯示具有曝露在一前表面(亦即，觸點承載表面)601處之接合墊606之一晶粒600之一透視圖。此視圖類似於圖1C中之彼視圖。該晶粒係具有一個或多個晶粒的可等效於圖1A之晶圓之一晶圓之一部分。金屬化層可包含形成於晶片之接合墊上方或與晶片之接合墊接觸之連接墊604。在諸多情形下，晶片之接合墊之間隔可已經係如此近以便防止接合墊上方之金屬化層之寬度大致比接合墊自身寬。在此實施例之一變體中，在接合墊上方不提供任一金屬化層，此可在圖6B中看到。在圖6B中，接合墊係接近邊緣且可延伸至晶粒區域之邊緣以使得一第二金屬化步驟可經由一導電元件將每一接合墊連接至晶片之另一表面。在其他方面中，該製程之後續步驟類似於針對圖6A之結構之步驟。
再次參照圖6A，以一類似於圖2E中概述之製程之方式處理一基板602，例如，一晶圓。圖6C顯示一實例基板602之一剖視圖，該基板含有若干個晶粒600，其中一金屬化層604覆蓋下面的接合墊606，但在於接合墊上方不存在金屬化之情形(圖6B)中，可繞過第一金屬化步驟。在圖6D中，根據一個實施例，翻轉基板且用一黏合劑層608將其接合至一臨時基板610。圖6E顯示晶粒之後面薄化之後之基板602。圖6F顯示經切割或蝕刻以曝露第一金屬化層604(或變體中之接合墊)之後之基板602。然後，根據一個實施例，如在圖6G中所圖解說明，在經薄化及經蝕刻之基板上用一介電鈍化層614覆蓋該基板，使第一金屬化層之一部分曝露。根據一個實施例，沈積一第二金屬化層，從而形成連接第一金屬化層及第二金屬化層之連接墊616及導電元件618兩者。所得結構顯示於圖6H中。在沿虛線切分之後，可在圖6I中看到微電子裝置620之最終結構。
類似於先前實施例，可結合微電子裝置620以提供一晶粒堆疊。圖7顯示一實例性晶粒堆疊總成700。可藉由(例如)圖4A及圖4B中所示之方法結合一個微電子裝置之一前面處之連接墊604與曝露在毗鄰此裝置之該微電子裝置之一後面處之連接墊616來結合晶粒堆疊中之個別裝置。另一選擇係，可前面彼此面對地配置該等微電子裝置且藉由此等方法結合前面上之墊。在另一變體中，該等微電子裝置可經配置以使得後面彼此面對且結合其上之墊。由於裝置620之連接墊處之接合區域通常小於一個此裝置200(圖2)，因此額外注意對於每一裝置彼此之間的適當對準係必要的。此處使用同質元件顯示晶粒堆疊700，但其亦可由具有不同大小及/或功能性之裝置形成。
在又一實施例中，可在結合步驟之後進行一堆疊中之晶粒之間的連接。圖8A顯示一單一微電子裝置800。裝置800之形成類似於圖2及圖7中之裝置之彼形成。曝露在邊緣804處之導電元件812不用來提供至晶粒之另一表面之一環繞橋，但替代地係連接元件(例如，接合條、迹線或墊)以為以後導電接合提供表面區域。圖8B顯示一由裝置800形成之晶粒堆疊810之一個實施例。堆疊中之每一裝置使用一黏合劑層802附接至下一個裝置。此時，該等裝置可不係彼此電接觸。為導電地結合該等裝置，可將一焊料或其他可回流材料806球沈積在堆疊之靠近側邊緣的頂部上。在施加熱之後，可回流材料806向下流動以潤濕堆疊中之微電子裝置之邊緣表面處所曝露之連接元件並將其結合在一起。可看到之結果為圖8B中之晶粒堆疊總成810。
在另一實施例中，可將上文製造方法(圖1A-1I)同時應用至兩個或更多個結合在一起之基板以形成具有內部堆疊之晶粒之微電子裝置。在圖9中提供一實例流程。在此實施例中，在添加側面導電元件之前可在後表面處結合兩個或更多個基板。為此，使一基板圖案化有一第一金屬化層且將其附接至一臨時載體晶圓。藉由研磨、拋光或某些其他方法來薄化該基板。此製程之結果顯示於圖10A中，其類似於圖1F之結構117。在圖10B中，顛倒翻轉一第二結構117且用一黏合劑層1002將其附接至第一結構117。圖10C顯示在移除上部臨時載體晶圓及一上部黏合劑層之後之中間晶圓堆疊1000。下一步，如圖10D顯示，穿過兩個基板及中心黏合劑層1002切割或蝕刻通道1004以曝露下部基板之第一金屬化層。
在此實施例中，一單獨鈍化步驟可係不必要的，此乃因基板之經薄化表面向內朝向中心黏合劑層。然而，在通道形成之後可添加此作為一選用之步驟，此乃因端視通道之形成方式在通道內可存在基板之某些未受保護區域。圖10E顯示在沈積且圖案化一金屬化層以在邊緣表面處形成側面導電元件1012之後之晶圓結構1010，該等側面導電元件將每一裝置1020之一第一表面1001上之導體(例如迹線、連接墊)與該裝置之一第二表面1003上之導電元件連接在一起。注意，雖然第三金屬化層形成將堆疊之頂部連接至底部之側面導電元件1012，但其亦與上部基板之經圖案化金屬化層重疊以在金屬化層之間形成導電路徑。儘管存在此等金屬層之某些重疊，但藉助此方法所達成之整個製程係簡化且成本節省，此乃因相同結構可用作該製程之一部分。在虛線處分離之後形成中間晶粒堆疊裝置1020且其顯示於圖10F中。類似於先前實施例，可使用例如上文相對於圖4B、7或8A-C所述之方法將晶粒堆疊裝置1020結合至一複合堆疊1030中之其他類似裝置。儘管裝置1020稱為一中間晶粒堆疊裝置，但期望可單獨封裝及使用此裝置，而不進行後續堆疊。
在一變體中，可省略上部基板上之第一金屬化層。此一實例係圖10H中所示之結構1040。在此變體中，用一黏合劑層將結構1040結合至下部基板且然後形成通道1004。沈積一金屬化層及後續進行圖案化將導致在外觀及功能方面與圖10E之結構1010大致相同之一結構，然後進一步以一等效方式對其進行處理及堆疊。可稍微不同地形成此變體中之兩個晶圓基板，從而消除製程中所需金屬化步驟中之一者。
在此實施例之一其他變體中(此處未描繪)，可翻轉一第二晶圓堆疊1000且用另一黏合劑層附接至一第一晶圓堆疊1000，且然後再次移除上部載體晶圓。然後可切割並金屬化此總成以形成一四層級連接堆疊裝置。
在又一實施例中，在電連接兩個基板之前可以一面向下之方式處理該兩個基板。圖11A顯示欲結合之兩個晶圓結構，該兩個晶圓基板與圖1D之結構111及圖1F之結構117大致相同。不是將結構111附接至一臨時載體晶圓以進行薄化(如在圖1E中顯示)，替代地直接將其附接至結構117之後面。此在圖11B中圖解說明，其中該兩個結構用一黏合劑層1102附接在一起。圖11C顯示薄化上部基板之結果。在此之後，如在圖11D中所繪示，穿過兩個基板及中心金屬化層形成通道。在圖11E中，沈積且圖案化一第三金屬化層以形成結構1110。此處注意，第三金屬化層之側面導電元件1112與其他兩個金屬化層接觸。最後，移除下部載體且分離裝置1120，如圖11F中所看到。可將此等裝置堆疊為如圖11G中所示之一晶粒堆疊總成1130或以某些其他方式堆疊此等裝置。
儘管本文已參照特定實施例對本發明進行了闡述，但應理解該等實施例僅圖解闡釋本發明之原理及應用。因此，應理解，可對說明性實施例進行眾多修改且可在不背離隨附申請專利範圍所界定之本發明之精神及範疇之條件下設計其他配置。
100．．．晶圓
101．．．觸點承載表面
102．．．晶圓基板
104．．．半導體晶粒
106．．．接合墊
107．．．間隔距離
108．．．單一晶圓
110．．．第一金屬化層
110'．．．金屬化層
111．．．結構
112．．．連接墊
114．．．單獨臨時載體基板
116．．．黏合劑層
117．．．結構
118．．．通道
120．．．介電層
122．．．第二金屬化層
124．．．導電元件
124'．．．導電元件
126．．．連接墊
132．．．後表面
134．．．後邊緣表面
200．．．第一微電子裝置(第二微電子裝置)
201．．．第一表面
203．．．第二表面
208．．．邊緣
300．．．微電子總成
400．．．微電子裝置
401．．．前表面
402．．．導電接合材料層(連接墊)
403．．．後表面
500．．．晶粒堆疊結構
502．．．晶粒
504．．．晶粒
506．．．晶粒
510．．．晶粒堆疊結構
512．．．晶粒
514．．．晶粒
516．．．晶粒
600．．．晶粒
601．．．觸點承載表面
602．．．基板
604．．．連接墊
606．．．接合墊
608．．．黏合劑層
610．．．臨時基板
614．．．介電鈍化層
616．．．連接墊
618．．．導電元件
620．．．微電子裝置
700．．．晶粒堆疊總成
800．．．單一微電子裝置
802．．．黏合劑層
804．．．邊緣
806．．．可回流材料球
810‧‧‧晶粒堆疊總成
1000‧‧‧中間晶圓堆疊
1001‧‧‧第一表面
1002‧‧‧黏合劑層
1003‧‧‧第二表面
1004‧‧‧通道
1010‧‧‧晶圓結構
1012‧‧‧側面導電元件
1020‧‧‧裝置
1030‧‧‧複合堆疊
1040‧‧‧結構
1102‧‧‧黏合劑層
1110‧‧‧結構
1112‧‧‧側面導電元件
1120‧‧‧裝置
1130‧‧‧晶粒堆疊總成
當結合其中相同參考編號在整個圖式中用來指代相同或類似部件之隨附圖式閱讀數個經圖解說明之實施例之下述說明時可最佳理解本文中所闡述之裝置及方法。該等圖式未必按比例繪製；而替代地將重點置於圖解說明所述實施例之原理上。
圖1A顯示一含有若干個微電子晶片之晶圓之一透視圖；
圖1B顯示該晶圓之一部分之一剖視圖。
圖1C圖解說明根據一個實施例具有一設置在接合墊上方之第一金屬化層之晶圓之一單一晶粒之一透視圖。
圖1D-1I顯示經歷額外處理步驟的類似於圖1B之晶圓之晶圓之一部分的剖視圖。
圖2A顯示根據一個實施例之一經分離微電子裝置之一剖視圖。
圖2B及圖2C顯示根據一個實施例圖2A之結合結構之變體之一詳細視圖。
圖2D係一顯示圖2A之微電子裝置之透視圖。
圖2E概述根據一個實施例用來形成一成品微電子裝置之一流程。
圖3顯示根據一個實施例形成一晶粒堆疊結構之數個晶粒之一剖視圖。
圖4A及圖4B顯示根據一個實施例形成圖3之裝置之結合方法之兩個變體之剖視圖。
圖5A顯示根據一個實施例包括異類元件之一晶粒堆疊結構之一剖視圖。
圖5B顯示根據一個實施例包括具有各種大小之晶粒之異類元件之一晶粒堆疊結構之一剖視圖。
圖6A圖解說明根據一個實施例具有一設置在接合墊上方之第一金屬化層之晶圓之一單一晶粒之一透視圖。
圖6B顯示根據一個實施例具有延伸至邊緣之接合墊之一晶圓之一單一晶粒之透視圖。
圖6C-6I顯示根據一個實施例經歷額外處理步驟的具有類似於圖6A之晶粒之晶粒的晶圓之一部分之剖視圖。
圖7顯示根據一個實施例所形成之一晶粒堆疊結構之一剖視圖。
圖8A顯示根據一個實施例之一晶粒結構之一剖視圖。
圖8B顯示根據一個實施例一添加有額外可回流材料之一晶粒堆疊之一剖視圖。
圖8C顯示根據一個實施例之一晶粒堆疊結構之一剖視圖。
圖9概述根據一個實施例用來形成一成品裝置晶粒之一流程。
圖10A-10E顯示根據一個實施例導致形成具有兩個或更多個晶粒之一晶粒堆疊之製程步驟之一剖視圖。
圖10F顯示根據一個實施例包括兩個或更多個晶粒之一晶粒結構之一剖視圖。
圖10G顯示根據一個實施例包括圖10F之多個晶粒結構之一晶粒堆疊結構之一剖視圖。
圖10H顯示根據一個實施例在圖10A中開始之流程之一部分之一變體的一剖視圖。
圖11A-11E顯示根據一個實施例導致形成一晶粒堆疊之製程步驟之一剖視圖。
圖11F顯示根據一個實施例包括兩個或更多個晶粒之一晶粒結構之一剖視圖。
圖11G顯示根據一個實施例包括圖11F之多個晶粒結構之一晶粒堆疊結構之一剖視圖。
200．．．第一微電子裝置(第二微電子裝置)
201．．．第一表面
203．．．第二表面
300．．．微電子總成

Claims (27)

  1. 一種微電子總成，其包括：一第一微電子裝置及一第二微電子裝置，該等微電子裝置之每一者皆包含一晶粒結構，該晶粒結構包含至少一個半導體晶粒，且該等微電子裝置之每一者皆具有：一第一表面；相對該第一表面之一第二表面；以非直角之一角度遠離該第一表面及該第二表面延伸之至少一個邊緣表面；及至少一個第一導電元件，該至少一個第一導電元件沿該第一表面延伸且延伸到該至少一個邊緣表面上並與至少一個第二導電元件接觸，該至少一個第二導電元件沿該第二表面延伸，該第一微電子裝置之該等第一及第二導電元件之至少一者導電地接合至該第二微電子裝置之該等第一及第二導電元件之至少一者以在其之間提供一導電路徑。
  2. 如請求項1之微電子總成，其中該等微電子裝置之每一者之該至少一個第一導電元件包含一第一元件，該第一元件係藉由鍍敷至該等微電子裝置之每一者之該第一表面及該至少一個邊緣表面上而形成；且該等微電子裝置之每一者之該至少一個第二導電元件包含一第二元件，該第二元件係藉由鍍敷至該等微電子裝置之每一者之該第二表面上而形成，其中該等微電子裝置之每一者之該第一元件鍍敷在該等微電子裝置之每一者之該第二元件之部分上。
  3. 如請求項2之微電子總成，其中該等微電子裝置之每一者之該第一元件沿該第一元件鍍敷在該等微電子裝置之每一者之該第二元件之該部分上延伸。
  4. 如請求項2之微電子總成，其中該等微電子裝置之每一者之該第一元件沿該等微電子裝置之每一者之該第二元件之一邊緣而延伸。
  5. 如請求項1之微電子總成，其中使用一可熔金屬將該第一微電子裝置之該至少一個導電元件導電地接合至該第二微電子裝置之該至少一個導電元件。
  6. 如請求項1之微電子總成，其中使用導電膏將該第一微電子裝置之該至少一個導電元件導電地接合至該第二微電子裝置之該至少一個導電元件。
  7. 如請求項1之微電子總成，其中該第一微電子裝置之該第一表面及該第二表面中之一者面對該第二微電子裝置之該第一表面及該第二表面中之一者，且該等導電元件之曝露在該等面對表面處之部分被接合在一起。
  8. 如請求項7之微電子總成，其中該第一微電子裝置及該第二微電子裝置之該等第一導電元件或該等第二導電元件之至少一者包含對應地曝露在該等微電子裝置之每一者之該第一表面或該第二表面處之導電墊，該等導電墊被接合在一起。
  9. 如請求項7之微電子總成，其中該第一微電子裝置或該第二微電子裝置之該等第一導電元件或該等第二導電元件之至少一者包含迹線及導電墊，其中該等導電墊之至 少一者經設置距該至少一個微電子裝置之該至少一個邊緣表面達一間隔距離。
  10. 如請求項7之微電子總成，其中該等微電子裝置之每一者之該等導電元件之至少一者包含接近該等微電子裝置之每一者之該至少一個邊緣表面之一導電墊。
  11. 如請求項10之微電子總成，其中該等微電子裝置之每一者之該導電墊延伸至該等微電子裝置之每一者之該至少一個邊緣表面。
  12. 如請求項1之微電子總成，其中該等晶粒結構中之至少一者包含複數個半導體晶粒。
  13. 如請求項12之微電子總成，其中包含於該至少一個晶粒結構中之該等半導體晶粒中之至少兩者之接合墊承載表面面向相同方向。
  14. 如請求項12之微電子總成，其中包含於該至少一個晶粒結構中之該等半導體晶粒中之至少兩者之接合墊承載表面面向不同方向。
  15. 如請求項1之微電子總成，其中該第一微電子裝置或該第二微電子裝置之至少一者之該邊緣表面以相對於該第一微電子裝置或該第二微電子裝置之該第一表面及該第二表面中之至少一者呈50度與89度之間的一角度延伸。
  16. 如請求項1之微電子總成，其中該第一微電子裝置及該第二微電子裝置沿一垂直方向堆疊且該第一微電子裝置及該第二微電子裝置之該至少一個邊緣表面在遠離該垂直方向之一方向上彼此偏移。
  17. 如請求項1之微電子總成，其中該第一微電子裝置及該第二微電子裝置之該等第一表面在橫向方向上延伸且在該等橫向方向上具有第一尺寸，其中該第一微電子裝置及該第二微電子裝置之該等第一表面之該等橫向尺寸係不同。
  18. 一種微電子總成，其包括：一第一微電子裝置及一第二微電子裝置，該等微電子裝置之每一者皆包含一晶粒結構，該晶粒結構包含至少一個半導體晶粒，且該等微電子裝置之每一者皆具有：一第一表面；相對該第一表面之一第二表面；以非直角之一角度遠離該第一表面延伸之至少一個邊緣表面；及至少一個第一導電元件，該至少一個第一導電元件沿該第一表面延伸且延伸到該至少一個邊緣表面上並與至少一個第二導電元件接觸，該至少一個第二導電元件沿該第二表面延伸，該第一微電子裝置之該等第一及第二導電元件之至少一者導電地接合至該第二微電子裝置之該等第一及第二導電元件之至少一者以在其之間提供一導電路徑。
  19. 如請求項18之微電子總成，其中該至少一個邊緣表面以非直角之一角度遠離該第一表面及該第二表面延伸。
  20. 如請求項18之微電子總成，其中該等導電元件之曝露在該第一微電子裝置之該至少一個邊緣表面處之至少邊緣部分經導電地接合至該等導電元件曝露在該第二微電子裝置之該至少一個邊緣表面處的至少邊緣部分以提供該 導電路徑。
  21. 如請求項20之微電子總成，其中使用一可熔金屬將該第一微電子裝置之該等導電元件之該等至少邊緣部分導電地接合至該第二微電子裝置之該等導電元件之該等至少邊緣部分。
  22. 如請求項20之微電子總成，其中使用導電膏將該第一微電子裝置之該等導電元件之該等至少邊緣部分導電地接合至該第二微電子裝置之該等導電元件之該等至少邊緣部分。
  23. 一種製造一經堆疊微電子總成之方法，其包括：配置一第一微電子裝置之一主表面以面對一第二微電子裝置之一主表面，且將曝露在該第一微電子裝置之該主表面處之至少一個導電元件與曝露在該第二微電子裝置之該主表面處之至少一個導電元件導電地接合以在其之間提供一導電路徑，其中該等微電子裝置之每一者皆包含一晶粒結構，該晶粒結構包含至少一個半導體晶粒，且該等微電子裝置之每一者皆具有一第一主表面、相對該第一主表面之一第二主表面、以非直角之一角度遠離該第一主表面延伸之至少一個邊緣表面、及至少一個第一導電元件，該至少一個第一導電元件沿該第一主表面延伸且延伸到該至少一個邊緣表面上並於該第一主表面處與至少一個第二導電元件接觸，該至少一個第二導電元件沿該第二主表面延伸。
  24. 一種製造一經堆疊微電子總成之方法，其包括：形成包含一第一微電子裝置及一第二微電子裝置之一堆疊，該等微電子裝置中之每一者皆包含一晶粒結構，該晶粒結構包含至少一個半導體晶粒，且該等微電子裝置中之每一者皆具有：一第一表面；相對該第一表面之一第二表面；以非直角之一角度遠離該第一表面延伸之至少一個邊緣表面；至少一個第一導電元件，其沿該第一表面延伸且延伸至該至少一個邊緣表面上並與至少一個第二導電元件接觸，該至少一個第二導電元件沿該第二表面延伸；及將曝露在該第一微電子裝置之該邊緣表面處之該等導電元件之至少一者之部分導電地接合至曝露在該第二微電子裝置之該邊緣表面處之該等導電元件之至少一者以在其之間提供一導電路徑。
  25. 如請求項24之方法，其中將該第一微電子裝置設置在該第二微電子裝置上方，且藉由加熱接近曝露在該第一微電子裝置之該至少一個邊緣表面處之該導電元件之一可熔金屬，以使得該可熔金屬流動至曝露在該第二微電子裝置之該至少一個邊緣表面處之該導電元件上來執行該接合步驟。
  26. 如請求項25之方法，其中該可熔金屬橋接該第一微電子裝置及該第二微電子裝置之該等導電元件之間的一間隙。
  27. 如請求項24之方法，其中將該第一微電子裝置設置於該 第二微電子裝置上方，且藉由將一可流動導電材料分配至曝露在該第一微電子裝置之該至少一個邊緣表面處之該導電元件上以使得該導電材料流動至曝露在該第二微電子裝置之該至少一個邊緣表面處之該導電元件上來執行該接合步驟。
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