JP2001068650A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JP2001068650A
JP2001068650A JP24315499A JP24315499A JP2001068650A JP 2001068650 A JP2001068650 A JP 2001068650A JP 24315499 A JP24315499 A JP 24315499A JP 24315499 A JP24315499 A JP 24315499A JP 2001068650 A JP2001068650 A JP 2001068650A
Authority
JP
Japan
Prior art keywords
circuit
clock signal
signal
semiconductor integrated
variable delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24315499A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001068650A5 (https=
Inventor
Yuichi Okuda
裕一 奥田
Masaru Kokubo
優 小久保
Yoshinobu Nakagome
儀延 中込
Hideji Yahata
秀治 矢幡
Hiromoto Miyashita
広基 宮下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP24315499A priority Critical patent/JP2001068650A/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to TW089115183A priority patent/TW503564B/zh
Priority to US09/629,173 priority patent/US6377511B1/en
Priority to KR1020000048250A priority patent/KR100686631B1/ko
Publication of JP2001068650A publication Critical patent/JP2001068650A/ja
Priority to US10/036,374 priority patent/US6463008B2/en
Priority to US10/185,044 priority patent/US6594197B2/en
Priority to US10/614,242 priority patent/US6819626B2/en
Priority to US10/965,845 priority patent/US7072242B2/en
Priority to KR1020050076726A priority patent/KR100675199B1/ko
Publication of JP2001068650A5 publication Critical patent/JP2001068650A5/ja
Priority to US11/298,514 priority patent/US7411805B2/en
Priority to US12/169,253 priority patent/US7602665B2/en
Priority to US12/577,365 priority patent/US7936621B2/en
Priority to US13/080,958 priority patent/US8179733B2/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0898—Details of the current generators the source or sink current values being variable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1072—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the charge pump, e.g. changing the gain
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/14—Preventing false-lock or pseudo-lock of the PLL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP24315499A 1999-08-30 1999-08-30 半導体集積回路装置 Pending JP2001068650A (ja)

Priority Applications (13)

Application Number Priority Date Filing Date Title
JP24315499A JP2001068650A (ja) 1999-08-30 1999-08-30 半導体集積回路装置
TW089115183A TW503564B (en) 1999-08-30 2000-07-28 Semiconductor integrated circuit apparatus
US09/629,173 US6377511B1 (en) 1999-08-30 2000-07-31 Semiconductor integrated circuit device
KR1020000048250A KR100686631B1 (ko) 1999-08-30 2000-08-21 반도체 집적회로장치
US10/036,374 US6463008B2 (en) 1999-08-30 2002-01-07 Semiconductor integrated circuit device
US10/185,044 US6594197B2 (en) 1999-08-30 2002-07-01 Semiconductor integrated circuit device
US10/614,242 US6819626B2 (en) 1999-08-30 2003-07-08 Semiconductor integrated circuit device
US10/965,845 US7072242B2 (en) 1999-08-30 2004-10-18 Semiconductor integrated circuit device
KR1020050076726A KR100675199B1 (ko) 1999-08-30 2005-08-22 반도체 집적회로장치
US11/298,514 US7411805B2 (en) 1999-08-30 2005-12-12 Semiconductor integrated circuit device
US12/169,253 US7602665B2 (en) 1999-08-30 2008-07-08 Semiconductor integrated circuit device
US12/577,365 US7936621B2 (en) 1999-08-30 2009-10-12 Semiconductor integrated circuit device
US13/080,958 US8179733B2 (en) 1999-08-30 2011-04-06 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24315499A JP2001068650A (ja) 1999-08-30 1999-08-30 半導体集積回路装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2005242606A Division JP2006031933A (ja) 2005-08-24 2005-08-24 ダイナミック型半導体記憶装置、ダブル・データ・レート・シンクロナス・ダイナミック型ランダム・アクセス・メモリ、半導体記憶回路装置及び半導体集積回路装置

Publications (2)

Publication Number Publication Date
JP2001068650A true JP2001068650A (ja) 2001-03-16
JP2001068650A5 JP2001068650A5 (https=) 2005-11-04

Family

ID=17099617

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24315499A Pending JP2001068650A (ja) 1999-08-30 1999-08-30 半導体集積回路装置

Country Status (4)

Country Link
US (9) US6377511B1 (https=)
JP (1) JP2001068650A (https=)
KR (2) KR100686631B1 (https=)
TW (1) TW503564B (https=)

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KR100513806B1 (ko) * 2000-12-30 2005-09-13 주식회사 하이닉스반도체 반도체 장치
US6980479B2 (en) 2003-04-29 2005-12-27 Hynix Semiconductor Inc. Semiconductor device for domain crossing
JP2008523737A (ja) * 2004-12-13 2008-07-03 モサイド・テクノロジーズ・コーポレイション 電流ミラー回路を有する電荷ポンプを用いた位相ロックループ回路
JP2010541075A (ja) * 2007-09-27 2010-12-24 マイクロン テクノロジー， インク． 高速ｄｒａｍ中の信号を処理するためのシステムおよび方法
JP2011003250A (ja) * 2009-06-19 2011-01-06 Renesas Electronics Corp 半導体記憶装置
US8971507B2 (en) 2012-09-05 2015-03-03 Kabushiki Kaisha Toshiba Facsimile server, facsimile system, and facsimile transmission method
JP2023147600A (ja) * 2022-03-30 2023-10-13 セイコーエプソン株式会社 回路装置及び発振器

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KR100380409B1 (ko) * 2001-01-18 2003-04-11 삼성전자주식회사 반도체 메모리 소자의 패드배열구조 및 그의 구동방법
US6798259B2 (en) * 2001-08-03 2004-09-28 Micron Technology, Inc. System and method to improve the efficiency of synchronous mirror delays and delay locked loops
US6944040B1 (en) 2001-12-28 2005-09-13 Netlogic Microsystems, Inc. Programmable delay circuit within a content addressable memory
US6650575B1 (en) * 2001-12-28 2003-11-18 Netlogic Microsystems, Inc. Programmable delay circuit within a content addressable memory
KR100418399B1 (ko) * 2002-03-20 2004-02-11 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 데이터 입출력 기준신호출력방법
US6795365B2 (en) * 2002-08-23 2004-09-21 Micron Technology, Inc. DRAM power bus control
JP2005038882A (ja) * 2003-07-15 2005-02-10 Sanyo Electric Co Ltd 半導体装置、及び分圧回路
US7027316B2 (en) * 2003-12-29 2006-04-11 Micron Technology, Inc. Access circuit and method for allowing external test voltage to be applied to isolated wells
DE102004012553A1 (de) * 2004-03-15 2005-10-13 Infineon Technologies Ag Speicherbauelement mit asymmetrischer Kontaktreihe
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KR100639616B1 (ko) * 2004-10-29 2006-10-30 주식회사 하이닉스반도체 반도체 기억 소자에서의 지연 고정 루프 및 그의 록킹 방법
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JP4828203B2 (ja) * 2005-10-20 2011-11-30 エルピーダメモリ株式会社 同期型半導体記憶装置
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KR100960715B1 (ko) * 2008-03-28 2010-05-31 한국전기연구원 씨모스 엑스레이 이미지 센서 모듈
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JP2011146104A (ja) * 2010-01-15 2011-07-28 Elpida Memory Inc 半導体装置及び半導体装置を含む情報処理システム
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US20050052944A1 (en) 2005-03-10
US20060087909A1 (en) 2006-04-27
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US7411805B2 (en) 2008-08-12
US6463008B2 (en) 2002-10-08
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US7602665B2 (en) 2009-10-13
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US6819626B2 (en) 2004-11-16
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US20040004902A1 (en) 2004-01-08
US20080273404A1 (en) 2008-11-06

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