DE69939150D1 - Gehäuse für Scheiben und seine Herstellung - Google Patents

Gehäuse für Scheiben und seine Herstellung

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Publication number
DE69939150D1
DE69939150D1 DE69939150T DE69939150T DE69939150D1 DE 69939150 D1 DE69939150 D1 DE 69939150D1 DE 69939150 T DE69939150 T DE 69939150T DE 69939150 T DE69939150 T DE 69939150T DE 69939150 D1 DE69939150 D1 DE 69939150D1
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DE
Germany
Prior art keywords
discs
manufacture
housing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69939150T
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English (en)
Inventor
Shigeyuki Maruyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
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Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69939150D1 publication Critical patent/DE69939150D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
DE69939150T 1998-12-28 1999-12-21 Gehäuse für Scheiben und seine Herstellung Expired - Lifetime DE69939150D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP37480498A JP4234244B2 (ja) 1998-12-28 1998-12-28 ウエハーレベルパッケージ及びウエハーレベルパッケージを用いた半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE69939150D1 true DE69939150D1 (de) 2008-09-04

Family

ID=18504457

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69939150T Expired - Lifetime DE69939150D1 (de) 1998-12-28 1999-12-21 Gehäuse für Scheiben und seine Herstellung

Country Status (7)

Country Link
US (5) US6228684B1 (de)
EP (1) EP1017094B1 (de)
JP (1) JP4234244B2 (de)
KR (2) KR100690512B1 (de)
CN (1) CN100372109C (de)
DE (1) DE69939150D1 (de)
TW (1) TW457611B (de)

Families Citing this family (104)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6930219B2 (en) * 1999-09-07 2005-08-16 Abb Lummus Global Inc. Mesoporous material with active metals
US6348728B1 (en) * 2000-01-28 2002-02-19 Fujitsu Limited Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer
JP2001308061A (ja) * 2000-04-25 2001-11-02 Nec Corp 半導体装置の製造方法
US6815803B1 (en) 2000-06-16 2004-11-09 Infineon Technologies Ag Multiple chip semiconductor arrangement having electrical components in separating regions
US6730989B1 (en) 2000-06-16 2004-05-04 Infineon Technologies Ag Semiconductor package and method
JP3610887B2 (ja) * 2000-07-03 2005-01-19 富士通株式会社 ウエハレベル半導体装置の製造方法及び半導体装置
US6603323B1 (en) * 2000-07-10 2003-08-05 Formfactor, Inc. Closed-grid bus architecture for wafer interconnect structure
JP2002033361A (ja) 2000-07-17 2002-01-31 Mitsumi Electric Co Ltd 半導体ウェハ
TW525216B (en) * 2000-12-11 2003-03-21 Semiconductor Energy Lab Semiconductor device, and manufacturing method thereof
JP3619773B2 (ja) * 2000-12-20 2005-02-16 株式会社ルネサステクノロジ 半導体装置の製造方法
SG111923A1 (en) 2000-12-21 2005-06-29 Semiconductor Energy Lab Light emitting device and method of manufacturing the same
US6590225B2 (en) * 2001-01-19 2003-07-08 Texas Instruments Incorporated Die testing using top surface test pads
US7498196B2 (en) 2001-03-30 2009-03-03 Megica Corporation Structure and manufacturing method of chip scale package
JP2003068806A (ja) * 2001-08-29 2003-03-07 Hitachi Ltd 半導体装置及びその製造方法
DE10146176B4 (de) * 2001-09-19 2009-04-02 Qimonda Ag Verfahren zur Umverdrahtung von Pads bei einem Waferlevel-Package, Waferlevel-Package und Halbleiterchip
DE10157008B4 (de) * 2001-11-21 2004-03-04 Infineon Technologies Ag Halbleiterbauteil mit einem Halbleiterplättchen
TW544882B (en) * 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
US6908791B2 (en) * 2002-04-29 2005-06-21 Texas Instruments Incorporated MEMS device wafer-level package
US7579681B2 (en) * 2002-06-11 2009-08-25 Micron Technology, Inc. Super high density module with integrated wafer level packages
SG107595A1 (en) * 2002-06-18 2004-12-29 Micron Technology Inc Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assembles and packages including such semiconductor devices or packages and associated methods
SG111069A1 (en) * 2002-06-18 2005-05-30 Micron Technology Inc Semiconductor devices including peripherally located bond pads, assemblies, packages, and methods
US7026646B2 (en) * 2002-06-20 2006-04-11 Micron Technology, Inc. Isolation circuit
US6967348B2 (en) * 2002-06-20 2005-11-22 Micron Technology, Inc. Signal sharing circuit with microelectric die isolation features
JP2004138391A (ja) * 2002-10-15 2004-05-13 Renesas Technology Corp 半導体装置の製造方法
US7265045B2 (en) * 2002-10-24 2007-09-04 Megica Corporation Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
JP3808030B2 (ja) * 2002-11-28 2006-08-09 沖電気工業株式会社 半導体装置及びその製造方法
US7435990B2 (en) * 2003-01-15 2008-10-14 International Business Machines Corporation Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer
JP4601910B2 (ja) * 2003-03-28 2010-12-22 パナソニック株式会社 半導体集積回路装置及び半導体集積回路装置の製造方法
JP3983205B2 (ja) 2003-07-08 2007-09-26 沖電気工業株式会社 半導体装置及びその製造方法
DE10343578B4 (de) * 2003-09-18 2007-01-18 Infineon Technologies Ag Umverdrahtungssubstratstreifen mit mehreren Halbleiterbauteilpositionen und Verfahren zu seiner Herstellung
US7345350B2 (en) * 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
SG120123A1 (en) * 2003-09-30 2006-03-28 Micron Technology Inc Castellated chip-scale packages and methods for fabricating the same
JP4462903B2 (ja) * 2003-11-18 2010-05-12 パナソニック株式会社 半導体ウェハ
DE102004001956B4 (de) * 2004-01-13 2007-02-01 Infineon Technologies Ag Umverdrahtungssubstratstreifen mit mehreren Halbleiterbauteilpositionen
GB0329516D0 (en) * 2003-12-19 2004-01-28 Univ Kent Canterbury Integrated circuit with debug support interface
US7316063B2 (en) * 2004-01-12 2008-01-08 Micron Technology, Inc. Methods of fabricating substrates including at least one conductive via
DE102004020187B4 (de) * 2004-04-22 2006-07-13 Infineon Technologies Ag Umverdrahtungssubstratstreifen mit mehreren Halbleiterbauteilpositionen
JP4654598B2 (ja) * 2004-04-30 2011-03-23 ソニー株式会社 半導体装置およびその製造方法
US7808115B2 (en) 2004-05-03 2010-10-05 Broadcom Corporation Test circuit under pad
US7061123B1 (en) * 2004-05-03 2006-06-13 National Semiconductor Corporation Wafer level ball grid array
KR100648260B1 (ko) * 2004-08-09 2006-11-23 삼성전자주식회사 자기 차폐 기능을 갖는 반도체 웨이퍼 및 그것의 테스트방법
FR2875623A1 (fr) * 2004-09-23 2006-03-24 St Microelectronics Sa Generation d'un identifiant d'un circuit integre
US7471098B2 (en) * 2004-10-28 2008-12-30 Seagate Technology Llc Testing device and method for an integrated circuit
JP2006140338A (ja) * 2004-11-12 2006-06-01 Matsushita Electric Ind Co Ltd 半導体装置
CN101151544B (zh) 2005-03-28 2011-08-03 株式会社半导体能源研究所 半导体器件、其制造方法、及其测量方法
US20060258051A1 (en) * 2005-05-10 2006-11-16 Texas Instruments Incorporated Method and system for solder die attach
TWI251861B (en) * 2005-06-16 2006-03-21 Etron Technology Inc Re-entrant Routing method and circuit structure
JP2007034275A (ja) * 2005-06-21 2007-02-08 Canon Inc 電子部品およびその製造方法
JP4289335B2 (ja) * 2005-08-10 2009-07-01 セイコーエプソン株式会社 電子部品、回路基板及び電子機器
KR100710185B1 (ko) * 2005-11-14 2007-04-20 동부일렉트로닉스 주식회사 반도체 소자의 검사장치
US7405585B2 (en) * 2006-02-14 2008-07-29 Taiwan Semiconductor Manufacturing Co., Ltd. Versatile semiconductor test structure array
US20070263472A1 (en) * 2006-05-11 2007-11-15 Anderson Brent A Process environment variation evaluation
US20080057677A1 (en) * 2006-09-06 2008-03-06 International Business Machines Corporation Chip location identification
US7707380B2 (en) * 2006-09-29 2010-04-27 Qimonda Ag Memories, method of storing data in memory and method of determining memory cell sector quality
JP4274576B2 (ja) * 2007-01-12 2009-06-10 エルピーダメモリ株式会社 半導体装置
JP5254569B2 (ja) * 2007-05-22 2013-08-07 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置のヒューズ溶断方法
US8106476B2 (en) * 2007-08-13 2012-01-31 Broadcom Corporation Semiconductor die with fuse window and a monitoring window over a structure which indicates fuse integrity
JP5071084B2 (ja) * 2007-12-10 2012-11-14 パナソニック株式会社 配線用基板とそれを用いた積層用半導体装置および積層型半導体モジュール
SG156550A1 (en) * 2008-05-06 2009-11-26 Gautham Viswanadam Wafer level integration module with interconnects
EP2324499B1 (de) * 2008-08-07 2012-01-18 STMicroelectronics Srl Schaltung zur parallelversorgung mit strom während des prüfens mehrerer auf einem halbleiterwafer integrierter elektronischer anordnungen
WO2010032350A1 (ja) * 2008-09-17 2010-03-25 パナソニック株式会社 半導体装置及びその製造方法
US8022521B1 (en) * 2008-11-12 2011-09-20 Amkor Technology, Inc. Package failure prognostic structure and method
JP5697842B2 (ja) * 2008-11-18 2015-04-08 ラピスセミコンダクタ株式会社 半導体装置の製造方法及びこれに用いるｓｏｑ基板
US8093700B2 (en) * 2008-12-16 2012-01-10 Freescale Semiconductor, Inc. Packaging millimeter wave modules
WO2010070964A1 (ja) * 2008-12-16 2010-06-24 株式会社村田製作所 回路モジュール及びその管理方法
US20100264522A1 (en) * 2009-04-20 2010-10-21 Chien-Pin Chen Semiconductor device having at least one bump without overlapping specific pad or directly contacting specific pad
JP5478133B2 (ja) * 2009-07-03 2014-04-23 株式会社日本マイクロニクス 集積回路の試験に用いるテストチップ
KR101143398B1 (ko) * 2009-07-30 2012-05-22 에스케이하이닉스 주식회사 반도체 집적회로
EP2290686A3 (de) 2009-08-28 2011-04-20 STMicroelectronics S.r.l. Verfahren zum elektrischen Testen und zur Montage elektronischer Bauelemente
KR20110049067A (ko) * 2009-11-04 2011-05-12 삼성전자주식회사 패키지 기판, 패키지 기판을 갖는 반도체 패키지, 및 반도체 패키지의 제조 방법
JP5533063B2 (ja) 2010-03-15 2014-06-25 富士通セミコンダクター株式会社 半導体集積回路
US20120007211A1 (en) * 2010-07-06 2012-01-12 Aleksandar Aleksov In-street die-to-die interconnects
US8664540B2 (en) * 2011-05-27 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer testing using dummy connections
CN102891132A (zh) * 2011-07-22 2013-01-23 微创高科有限公司 一种电子设备
ITMI20111418A1 (it) * 2011-07-28 2013-01-29 St Microelectronics Srl Architettura di testing di circuiti integrati su un wafer
CN102543960A (zh) * 2012-02-10 2012-07-04 上海宏力半导体制造有限公司 一种测试用集成电路
CN103377961A (zh) * 2012-04-25 2013-10-30 南亚科技股份有限公司 三维堆叠的随机存取存储器的测试与制造方法以及晶圆的测试方法
US20130299947A1 (en) * 2012-05-14 2013-11-14 Freescale Semiconductor, Inc. Passivated test structures to enable saw singulation of wafer
US8933448B2 (en) * 2012-07-27 2015-01-13 Infineon Technologies Ag Wafers and chips comprising test structures
US9099420B2 (en) * 2012-11-30 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Test structures for post-passivation interconnect
US8901739B2 (en) 2012-12-05 2014-12-02 Infineon Technologies Ag Embedded chip package, a chip package, and a method for manufacturing an embedded chip package
KR101984831B1 (ko) 2013-01-31 2019-05-31 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
CN103197227A (zh) * 2013-03-25 2013-07-10 西安华芯半导体有限公司 一种用于设计分析目的的晶圆测试方法
US10015916B1 (en) 2013-05-21 2018-07-03 Xilinx, Inc. Removal of electrostatic charges from an interposer via a ground pad thereof for die attach for formation of a stacked die
US9960227B2 (en) * 2013-09-11 2018-05-01 Xilinx, Inc. Removal of electrostatic charges from interposer for die attachment
MY193922A (en) * 2013-12-30 2022-11-01 Celerint Llc Method for testing semiconductor wafers using temporary sacrificial bond pads
TWI665771B (zh) * 2014-10-31 2019-07-11 矽品精密工業股份有限公司 不著檢出測試方法及其所用之基板
CN105137317A (zh) * 2015-08-10 2015-12-09 华进半导体封装先导技术研发中心有限公司 快速测试晶圆电性用的转接板工艺和转接板结构
CN105329850B (zh) * 2015-10-21 2017-03-08 美新半导体（无锡）有限公司 圆片级芯片尺寸封装的测试方法
CN105575845B (zh) * 2016-02-04 2018-12-21 北京锐洁机器人科技有限公司 伸缩型晶圆扫描装置及晶圆扫描系统
JP2019021777A (ja) * 2017-07-18 2019-02-07 浜松ホトニクス株式会社 半導体ウェハ
US10261123B2 (en) * 2017-08-24 2019-04-16 Micron Technology, Inc. Semiconductor device structures for burn-in testing and methods thereof
KR102497570B1 (ko) 2018-01-18 2023-02-10 삼성전자주식회사 반도체 장치
CN109449098B (zh) * 2018-11-19 2023-12-26 北京燕东微电子科技有限公司 半导体结构、测试系统、测试方法及半导体结构的制造方法
CN109300799B (zh) * 2018-11-19 2024-02-02 北京燕东微电子科技有限公司 半导体结构、测试系统、测试方法及半导体结构的制作方法
KR102648090B1 (ko) * 2019-05-17 2024-03-18 삼성전자주식회사 배선기판 및 이를 포함하는 반도체 패키지
EP4060720A4 (de) 2019-11-15 2023-08-16 Kioxia Corporation Speichervorrichtung und speichersystem
CN114624557A (zh) * 2020-12-11 2022-06-14 高端电子有限公司 半导体组件的测试方法
CN114646781A (zh) * 2020-12-21 2022-06-21 长鑫存储技术有限公司 测试机台及测试方法
US11892499B2 (en) 2020-12-21 2024-02-06 Changxin Memory Technologies, Inc. Testing machine and testing method
US20230298952A1 (en) * 2022-03-16 2023-09-21 Psemi Corporation Wafer fabrication process and devices with extended peripheral die area

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US158326A (en) * 1874-12-29 Improvement in beer-faucets
US24118A (en) * 1859-05-24 Machine fob filing saws
JPH0245339B2 (ja) * 1982-09-20 1990-10-09 Mitsubishi Electric Corp Handotaishusekikairosochi
DE3526485A1 (de) * 1985-07-24 1987-02-05 Heinz Krug Schaltungsanordnung zum pruefen integrierter schaltungseinheiten
JPS62219942A (ja) 1986-03-20 1987-09-28 Sharp Corp ウエハ−状態における半導体集積回路
EP0408586A1 (de) 1988-02-15 1991-01-23 TUTHILL, Roy Douglas Werkzeughalterungsvorrichtung für tafel mit werkzeugumrisszeichnung
JPH01215040A (ja) 1988-02-24 1989-08-29 Hitachi Ltd 半導体集積回路
JPH023948A (ja) 1988-06-20 1990-01-09 Mitsubishi Electric Corp 不揮発性メモリを有するｉｃのウエハテスト方法
JP2585799B2 (ja) * 1989-06-30 1997-02-26 株式会社東芝 半導体メモリ装置及びそのバーンイン方法
JPH03266446A (ja) 1990-03-15 1991-11-27 Nec Corp 半導体装置の製造方法
US5059899A (en) * 1990-08-16 1991-10-22 Micron Technology, Inc. Semiconductor dies and wafers and methods for making
US6828812B2 (en) * 1991-06-04 2004-12-07 Micron Technology, Inc. Test apparatus for testing semiconductor dice including substrate with penetration limiting contacts for making electrical connections
US5323051A (en) * 1991-12-16 1994-06-21 Motorola, Inc. Semiconductor wafer level package
JPH065677A (ja) 1992-06-18 1994-01-14 Nec Corp 半導体装置
US5442282A (en) * 1992-07-02 1995-08-15 Lsi Logic Corporation Testing and exercising individual, unsingulated dies on a wafer
JPH0669298A (ja) 1992-08-19 1994-03-11 Nec Yamaguchi Ltd 集積回路の製造方法
US5489538A (en) * 1992-08-21 1996-02-06 Lsi Logic Corporation Method of die burn-in
US5366906A (en) * 1992-10-16 1994-11-22 Martin Marietta Corporation Wafer level integration and testing
US5535101A (en) * 1992-11-03 1996-07-09 Motorola, Inc. Leadless integrated circuit package
US5342999A (en) * 1992-12-21 1994-08-30 Motorola, Inc. Apparatus for adapting semiconductor die pads and method therefor
US5654588A (en) * 1993-07-23 1997-08-05 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure
JPH07263508A (ja) 1994-03-25 1995-10-13 Kawasaki Steel Corp バーイン試験用回路を有するウエハーおよびバーイン試験方法
US5532174A (en) * 1994-04-22 1996-07-02 Lsi Logic Corporation Wafer level integrated circuit testing with a sacrificial metal layer
DE69432016T2 (de) * 1994-09-13 2004-01-08 Stmicroelectronics S.R.L., Agrate Brianza Verfahren zur Herstellung integrierter Schaltungen und erzeugte Halbleiterscheibe
TW396480B (en) * 1994-12-19 2000-07-01 Matsushita Electric Ind Co Ltd Semiconductor chip and semiconductor wafer with power pads used for probing test
JP3522426B2 (ja) 1994-12-19 2004-04-26 松下電器産業株式会社 プローブ試験用の電源パッドを有する半導体チップ及び半導体ウエハ
US6204074B1 (en) * 1995-01-09 2001-03-20 International Business Machines Corporation Chip design process for wire bond and flip-chip package
JPH0955411A (ja) 1995-08-17 1997-02-25 Fujitsu Ltd 半導体ウェハの試験方法および半導体ウェハ
US5808947A (en) * 1995-08-21 1998-09-15 Sgs-Thomson Microelectronics, Inc. Integrated circuit that supports and method for wafer-level testing
US6072236A (en) * 1996-03-07 2000-06-06 Micron Technology, Inc. Micromachined chip scale package
US5965933A (en) * 1996-05-28 1999-10-12 Young; William R. Semiconductor packaging apparatus
KR100231276B1 (ko) * 1996-06-21 1999-11-15 황인길 반도체패키지의 구조 및 제조방법
US6121065A (en) * 1997-09-26 2000-09-19 Institute Of Microelectronics Wafer scale burn-in testing
US6427222B1 (en) * 1997-09-30 2002-07-30 Jeng-Jye Shau Inter-dice wafer level signal transfer methods for integrated circuits
US6114878A (en) * 1998-02-13 2000-09-05 Micron Technology, Inc. Circuit for contact pad isolation
JPH11354721A (ja) * 1998-06-04 1999-12-24 Mitsubishi Electric Corp 半導体装置
JP2000021939A (ja) * 1998-06-29 2000-01-21 Mitsubishi Electric Corp 突起電極付半導体チップおよびその検査方法
US6008523A (en) * 1998-08-26 1999-12-28 Siemens Aktiengesellschaft Electrical fuses with tight pitches and method of fabrication in semiconductors
US6373143B1 (en) * 1998-09-24 2002-04-16 International Business Machines Corporation Integrated circuit having wirebond pads suitable for probing
KR100313185B1 (ko) * 1998-09-29 2001-11-07 포만 제프리 엘 집적 회로 소자의 전기적 액세스 및 상호 접속 방법과 그 장치
US6436802B1 (en) * 1998-11-30 2002-08-20 Adoamtest Corp. Method of producing contact structure
US6043109A (en) * 1999-02-09 2000-03-28 United Microelectronics Corp. Method of fabricating wafer-level package
JP2001056346A (ja) * 1999-08-19 2001-02-27 Fujitsu Ltd プローブカード及び複数の半導体装置が形成されたウエハの試験方法
JP3711341B2 (ja) * 2001-04-27 2005-11-02 沖電気工業株式会社 半導体装置
US6744067B1 (en) * 2003-01-17 2004-06-01 Micron Technology, Inc. Wafer-level testing apparatus and method

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US7642551B2 (en) 2010-01-05
US6228684B1 (en) 2001-05-08
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US7399990B2 (en) 2008-07-15
US20060202201A1 (en) 2006-09-14
EP1017094A2 (de) 2000-07-05
CN1259767A (zh) 2000-07-12
EP1017094A3 (de) 2002-08-21
US20010042901A1 (en) 2001-11-22
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US20040206954A1 (en) 2004-10-21

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