DE69824972T2 - Integrierter halbleiterschaltkreis - Google Patents

Integrierter halbleiterschaltkreis Download PDF

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Publication number
DE69824972T2
DE69824972T2 DE69824972T DE69824972T DE69824972T2 DE 69824972 T2 DE69824972 T2 DE 69824972T2 DE 69824972 T DE69824972 T DE 69824972T DE 69824972 T DE69824972 T DE 69824972T DE 69824972 T2 DE69824972 T2 DE 69824972T2
Authority
DE
Germany
Prior art keywords
circuit
voltage
substrate
substrate bias
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69824972T
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German (de)
English (en)
Other versions
DE69824972D1 (de
Inventor
Hiroyuki Mizuno
Koichiro Kokubunji-shi ISHIBASHI
Takanori Kokubunji-shi SHIMURA
Toshihiro Kodaira-shi HATTORI
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Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
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Publication of DE69824972D1 publication Critical patent/DE69824972D1/de
Publication of DE69824972T2 publication Critical patent/DE69824972T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10Integrated device layouts
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146Substrate bias generators
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0016Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • H10D84/859Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
    • H10D84/907CMOS gate arrays
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69824972T 1997-12-26 1998-12-21 Integrierter halbleiterschaltkreis Expired - Lifetime DE69824972T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP35927197A JP4109340B2 (ja) 1997-12-26 1997-12-26 半導体集積回路装置
JP35927197 1997-12-26
PCT/JP1998/005770 WO1999034445A1 (fr) 1997-12-26 1998-12-21 Circuit integre semi-conducteur

Publications (2)

Publication Number Publication Date
DE69824972D1 DE69824972D1 (de) 2004-08-12
DE69824972T2 true DE69824972T2 (de) 2005-07-14

Family

ID=18463648

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69824972T Expired - Lifetime DE69824972T2 (de) 1997-12-26 1998-12-21 Integrierter halbleiterschaltkreis

Country Status (9)

Country Link
US (8) US6483374B1 (enExample)
EP (1) EP1043774B1 (enExample)
JP (1) JP4109340B2 (enExample)
KR (1) KR100625153B1 (enExample)
CN (1) CN1195324C (enExample)
DE (1) DE69824972T2 (enExample)
MY (1) MY118314A (enExample)
TW (1) TW426988B (enExample)
WO (1) WO1999034445A1 (enExample)

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US20030016076A1 (en) 2003-01-23
EP1043774A4 (en) 2002-01-02
US20050218965A1 (en) 2005-10-06
US6337593B1 (en) 2002-01-08
US7321252B2 (en) 2008-01-22
US20060176101A1 (en) 2006-08-10
US6987415B2 (en) 2006-01-17
CN1283308A (zh) 2001-02-07
US6707334B2 (en) 2004-03-16
EP1043774A1 (en) 2000-10-11
KR20010033614A (ko) 2001-04-25
JP4109340B2 (ja) 2008-07-02
US6600360B2 (en) 2003-07-29
US20080136502A1 (en) 2008-06-12
JPH11191611A (ja) 1999-07-13
TW426988B (en) 2001-03-21
CN1195324C (zh) 2005-03-30
MY118314A (en) 2004-09-30
US7046075B2 (en) 2006-05-16
EP1043774B1 (en) 2004-07-07
US20040183585A1 (en) 2004-09-23
US6483374B1 (en) 2002-11-19
KR100625153B1 (ko) 2006-09-20
US20030206049A1 (en) 2003-11-06
WO1999034445A1 (fr) 1999-07-08
US7598796B2 (en) 2009-10-06
DE69824972D1 (de) 2004-08-12

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